1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include "k3-j7200-som-p0.dtsi" 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/net/ti-dp83867.h> 11#include <dt-bindings/mux/ti-serdes.h> 12#include <dt-bindings/phy/phy.h> 13 14/ { 15 compatible = "ti,j7200-evm", "ti,j7200"; 16 model = "Texas Instruments J7200 EVM"; 17 18 chosen { 19 stdout-path = "serial2:115200n8"; 20 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; 21 }; 22 23 evm_12v0: fixedregulator-evm12v0 { 24 /* main supply */ 25 compatible = "regulator-fixed"; 26 regulator-name = "evm_12v0"; 27 regulator-min-microvolt = <12000000>; 28 regulator-max-microvolt = <12000000>; 29 regulator-always-on; 30 regulator-boot-on; 31 }; 32 33 vsys_3v3: fixedregulator-vsys3v3 { 34 /* Output of LM5140 */ 35 compatible = "regulator-fixed"; 36 regulator-name = "vsys_3v3"; 37 regulator-min-microvolt = <3300000>; 38 regulator-max-microvolt = <3300000>; 39 vin-supply = <&evm_12v0>; 40 regulator-always-on; 41 regulator-boot-on; 42 }; 43 44 vsys_5v0: fixedregulator-vsys5v0 { 45 /* Output of LM5140 */ 46 compatible = "regulator-fixed"; 47 regulator-name = "vsys_5v0"; 48 regulator-min-microvolt = <5000000>; 49 regulator-max-microvolt = <5000000>; 50 vin-supply = <&evm_12v0>; 51 regulator-always-on; 52 regulator-boot-on; 53 }; 54 55 vdd_mmc1: fixedregulator-sd { 56 /* Output of TPS22918 */ 57 compatible = "regulator-fixed"; 58 regulator-name = "vdd_mmc1"; 59 regulator-min-microvolt = <3300000>; 60 regulator-max-microvolt = <3300000>; 61 regulator-boot-on; 62 enable-active-high; 63 vin-supply = <&vsys_3v3>; 64 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 65 }; 66 67 vdd_sd_dv: gpio-regulator-TLV71033 { 68 /* Output of TLV71033 */ 69 compatible = "regulator-gpio"; 70 regulator-name = "tlv71033"; 71 pinctrl-names = "default"; 72 pinctrl-0 = <&vdd_sd_dv_pins_default>; 73 regulator-min-microvolt = <1800000>; 74 regulator-max-microvolt = <3300000>; 75 regulator-boot-on; 76 vin-supply = <&vsys_5v0>; 77 gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>; 78 states = <1800000 0x0>, 79 <3300000 0x1>; 80 }; 81}; 82 83&wkup_pmx0 { 84 mcu_cpsw_pins_default: mcu-cpsw-pins-default { 85 pinctrl-single,pins = < 86 J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */ 87 J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */ 88 J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */ 89 J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */ 90 J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */ 91 J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */ 92 J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */ 93 J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */ 94 J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */ 95 J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */ 96 J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */ 97 J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */ 98 >; 99 }; 100 101 mcu_mdio_pins_default: mcu-mdio1-pins-default { 102 pinctrl-single,pins = < 103 J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ 104 J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ 105 >; 106 }; 107}; 108 109&main_pmx0 { 110 main_i2c0_pins_default: main-i2c0-pins-default { 111 pinctrl-single,pins = < 112 J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */ 113 J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */ 114 >; 115 }; 116 117 main_i2c1_pins_default: main-i2c1-pins-default { 118 pinctrl-single,pins = < 119 J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */ 120 J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */ 121 >; 122 }; 123 124 main_mmc1_pins_default: main-mmc1-pins-default { 125 pinctrl-single,pins = < 126 J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */ 127 J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */ 128 J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ 129 J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */ 130 J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */ 131 J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */ 132 J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */ 133 J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ 134 >; 135 }; 136 137 main_usbss0_pins_default: main-usbss0-pins-default { 138 pinctrl-single,pins = < 139 J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ 140 >; 141 }; 142 143 vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { 144 pinctrl-single,pins = < 145 J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */ 146 >; 147 }; 148}; 149 150&wkup_uart0 { 151 /* Wakeup UART is used by System firmware */ 152 status = "reserved"; 153}; 154 155&main_uart0 { 156 /* Shared with ATF on this platform */ 157 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 158}; 159 160&main_uart2 { 161 /* MAIN UART 2 is used by R5F firmware */ 162 status = "reserved"; 163}; 164 165&main_uart3 { 166 /* UART not brought out */ 167 status = "disabled"; 168}; 169 170&main_uart4 { 171 /* UART not brought out */ 172 status = "disabled"; 173}; 174 175&main_uart5 { 176 /* UART not brought out */ 177 status = "disabled"; 178}; 179 180&main_uart6 { 181 /* UART not brought out */ 182 status = "disabled"; 183}; 184 185&main_uart7 { 186 /* UART not brought out */ 187 status = "disabled"; 188}; 189 190&main_uart8 { 191 /* UART not brought out */ 192 status = "disabled"; 193}; 194 195&main_uart9 { 196 /* UART not brought out */ 197 status = "disabled"; 198}; 199 200&main_gpio2 { 201 status = "disabled"; 202}; 203 204&main_gpio4 { 205 status = "disabled"; 206}; 207 208&main_gpio6 { 209 status = "disabled"; 210}; 211 212&wkup_gpio1 { 213 status = "disabled"; 214}; 215 216&mcu_cpsw { 217 pinctrl-names = "default"; 218 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; 219}; 220 221&davinci_mdio { 222 phy0: ethernet-phy@0 { 223 reg = <0>; 224 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 225 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 226 }; 227}; 228 229&cpsw_port1 { 230 phy-mode = "rgmii-rxid"; 231 phy-handle = <&phy0>; 232}; 233 234&main_i2c0 { 235 pinctrl-names = "default"; 236 pinctrl-0 = <&main_i2c0_pins_default>; 237 clock-frequency = <400000>; 238 239 exp1: gpio@20 { 240 compatible = "ti,tca6416"; 241 reg = <0x20>; 242 gpio-controller; 243 #gpio-cells = <2>; 244 }; 245 246 exp2: gpio@22 { 247 compatible = "ti,tca6424"; 248 reg = <0x22>; 249 gpio-controller; 250 #gpio-cells = <2>; 251 }; 252}; 253 254/* 255 * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be 256 * swapped on the CPB. 257 * 258 * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3. 259 * The i2c1 of the CPB (as it is labeled) is not connected to j7200. 260 */ 261&main_i2c1 { 262 pinctrl-names = "default"; 263 pinctrl-0 = <&main_i2c1_pins_default>; 264 clock-frequency = <400000>; 265 266 exp3: gpio@20 { 267 compatible = "ti,tca6408"; 268 reg = <0x20>; 269 gpio-controller; 270 #gpio-cells = <2>; 271 gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn", 272 "UB926_LOCK", "UB926_PWR_SW_CNTRL", 273 "UB926_TUNER_RESET", "UB926_GPIO_SPARE", ""; 274 }; 275}; 276 277&main_sdhci0 { 278 /* eMMC */ 279 non-removable; 280 ti,driver-strength-ohm = <50>; 281 disable-wp; 282}; 283 284&main_sdhci1 { 285 /* SD card */ 286 pinctrl-0 = <&main_mmc1_pins_default>; 287 pinctrl-names = "default"; 288 vmmc-supply = <&vdd_mmc1>; 289 vqmmc-supply = <&vdd_sd_dv>; 290 ti,driver-strength-ohm = <50>; 291 disable-wp; 292}; 293 294&serdes_ln_ctrl { 295 idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>, 296 <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>; 297}; 298 299&usb_serdes_mux { 300 idle-states = <1>; /* USB0 to SERDES lane 3 */ 301}; 302 303&usbss0 { 304 pinctrl-names = "default"; 305 pinctrl-0 = <&main_usbss0_pins_default>; 306 ti,vbus-divider; 307 ti,usb2-only; 308}; 309 310&usb0 { 311 dr_mode = "otg"; 312 maximum-speed = "high-speed"; 313}; 314 315&tscadc0 { 316 adc { 317 ti,adc-channels = <0 1 2 3 4 5 6 7>; 318 }; 319}; 320 321&serdes_refclk { 322 clock-frequency = <100000000>; 323}; 324 325&serdes0 { 326 serdes0_pcie_link: phy@0 { 327 reg = <0>; 328 cdns,num-lanes = <2>; 329 #phy-cells = <0>; 330 cdns,phy-type = <PHY_TYPE_PCIE>; 331 resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; 332 }; 333 334 serdes0_qsgmii_link: phy@1 { 335 reg = <2>; 336 cdns,num-lanes = <1>; 337 #phy-cells = <0>; 338 cdns,phy-type = <PHY_TYPE_QSGMII>; 339 resets = <&serdes_wiz0 3>; 340 }; 341}; 342 343&pcie1_rc { 344 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; 345 phys = <&serdes0_pcie_link>; 346 phy-names = "pcie-phy"; 347 num-lanes = <2>; 348}; 349 350&pcie1_ep { 351 phys = <&serdes0_pcie_link>; 352 phy-names = "pcie-phy"; 353 num-lanes = <2>; 354 status = "disabled"; 355}; 356