1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * Design Files: https://www.ti.com/lit/zip/SPRR466 6 * TRM: https://www.ti.com/lit/zip/spruj52 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/net/ti-dp83867.h> 12#include <dt-bindings/gpio/gpio.h> 13#include "k3-j784s4.dtsi" 14 15/ { 16 compatible = "ti,am69-sk", "ti,j784s4"; 17 model = "Texas Instruments AM69 SK"; 18 19 chosen { 20 stdout-path = "serial2:115200n8"; 21 }; 22 23 aliases { 24 serial0 = &wkup_uart0; 25 serial1 = &mcu_uart0; 26 serial2 = &main_uart8; 27 mmc0 = &main_sdhci0; 28 mmc1 = &main_sdhci1; 29 i2c0 = &wkup_i2c0; 30 i2c3 = &main_i2c0; 31 ethernet0 = &mcu_cpsw_port1; 32 }; 33 34 memory@80000000 { 35 device_type = "memory"; 36 bootph-all; 37 /* 32G RAM */ 38 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 39 <0x00000008 0x80000000 0x00000007 0x80000000>; 40 }; 41 42 reserved_memory: reserved-memory { 43 #address-cells = <2>; 44 #size-cells = <2>; 45 ranges; 46 47 secure_ddr: optee@9e800000 { 48 reg = <0x00 0x9e800000 0x00 0x01800000>; 49 no-map; 50 }; 51 52 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 53 compatible = "shared-dma-pool"; 54 reg = <0x00 0xa0000000 0x00 0x100000>; 55 no-map; 56 }; 57 58 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 59 compatible = "shared-dma-pool"; 60 reg = <0x00 0xa0100000 0x00 0xf00000>; 61 no-map; 62 }; 63 64 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 65 compatible = "shared-dma-pool"; 66 reg = <0x00 0xa1000000 0x00 0x100000>; 67 no-map; 68 }; 69 70 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 71 compatible = "shared-dma-pool"; 72 reg = <0x00 0xa1100000 0x00 0xf00000>; 73 no-map; 74 }; 75 76 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 77 compatible = "shared-dma-pool"; 78 reg = <0x00 0xa2000000 0x00 0x100000>; 79 no-map; 80 }; 81 82 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 83 compatible = "shared-dma-pool"; 84 reg = <0x00 0xa2100000 0x00 0xf00000>; 85 no-map; 86 }; 87 88 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 89 compatible = "shared-dma-pool"; 90 reg = <0x00 0xa3000000 0x00 0x100000>; 91 no-map; 92 }; 93 94 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 95 compatible = "shared-dma-pool"; 96 reg = <0x00 0xa3100000 0x00 0xf00000>; 97 no-map; 98 }; 99 100 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 101 compatible = "shared-dma-pool"; 102 reg = <0x00 0xa4000000 0x00 0x100000>; 103 no-map; 104 }; 105 106 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 107 compatible = "shared-dma-pool"; 108 reg = <0x00 0xa4100000 0x00 0xf00000>; 109 no-map; 110 }; 111 112 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 113 compatible = "shared-dma-pool"; 114 reg = <0x00 0xa5000000 0x00 0x100000>; 115 no-map; 116 }; 117 118 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 119 compatible = "shared-dma-pool"; 120 reg = <0x00 0xa5100000 0x00 0xf00000>; 121 no-map; 122 }; 123 124 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { 125 compatible = "shared-dma-pool"; 126 reg = <0x00 0xa6000000 0x00 0x100000>; 127 no-map; 128 }; 129 130 main_r5fss2_core0_memory_region: r5f-memory@a6100000 { 131 compatible = "shared-dma-pool"; 132 reg = <0x00 0xa6100000 0x00 0xf00000>; 133 no-map; 134 }; 135 136 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { 137 compatible = "shared-dma-pool"; 138 reg = <0x00 0xa7000000 0x00 0x100000>; 139 no-map; 140 }; 141 142 main_r5fss2_core1_memory_region: r5f-memory@a7100000 { 143 compatible = "shared-dma-pool"; 144 reg = <0x00 0xa7100000 0x00 0xf00000>; 145 no-map; 146 }; 147 148 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 149 compatible = "shared-dma-pool"; 150 reg = <0x00 0xa8000000 0x00 0x100000>; 151 no-map; 152 }; 153 154 c71_0_memory_region: c71-memory@a8100000 { 155 compatible = "shared-dma-pool"; 156 reg = <0x00 0xa8100000 0x00 0xf00000>; 157 no-map; 158 }; 159 160 c71_1_dma_memory_region: c71-dma-memory@a9000000 { 161 compatible = "shared-dma-pool"; 162 reg = <0x00 0xa9000000 0x00 0x100000>; 163 no-map; 164 }; 165 166 c71_1_memory_region: c71-memory@a9100000 { 167 compatible = "shared-dma-pool"; 168 reg = <0x00 0xa9100000 0x00 0xf00000>; 169 no-map; 170 }; 171 172 c71_2_dma_memory_region: c71-dma-memory@aa000000 { 173 compatible = "shared-dma-pool"; 174 reg = <0x00 0xaa000000 0x00 0x100000>; 175 no-map; 176 }; 177 178 c71_2_memory_region: c71-memory@aa100000 { 179 compatible = "shared-dma-pool"; 180 reg = <0x00 0xaa100000 0x00 0xf00000>; 181 no-map; 182 }; 183 184 c71_3_dma_memory_region: c71-dma-memory@ab000000 { 185 compatible = "shared-dma-pool"; 186 reg = <0x00 0xab000000 0x00 0x100000>; 187 no-map; 188 }; 189 190 c71_3_memory_region: c71-memory@ab100000 { 191 compatible = "shared-dma-pool"; 192 reg = <0x00 0xab100000 0x00 0xf00000>; 193 no-map; 194 }; 195 }; 196 197 vusb_main: regulator-vusb-main5v0 { 198 /* USB MAIN INPUT 5V DC */ 199 compatible = "regulator-fixed"; 200 regulator-name = "vusb-main5v0"; 201 regulator-min-microvolt = <5000000>; 202 regulator-max-microvolt = <5000000>; 203 regulator-always-on; 204 regulator-boot-on; 205 }; 206 207 vsys_5v0: regulator-vsys5v0 { 208 /* Output of LM61460 */ 209 compatible = "regulator-fixed"; 210 regulator-name = "vsys_5v0"; 211 regulator-min-microvolt = <5000000>; 212 regulator-max-microvolt = <5000000>; 213 vin-supply = <&vusb_main>; 214 regulator-always-on; 215 regulator-boot-on; 216 }; 217 218 vsys_3v3: regulator-vsys3v3 { 219 /* Output of LM5143 */ 220 compatible = "regulator-fixed"; 221 regulator-name = "vsys_3v3"; 222 regulator-min-microvolt = <3300000>; 223 regulator-max-microvolt = <3300000>; 224 vin-supply = <&vusb_main>; 225 regulator-always-on; 226 regulator-boot-on; 227 }; 228 229 vdd_mmc1: regulator-sd { 230 /* Output of TPS22918 */ 231 compatible = "regulator-fixed"; 232 regulator-name = "vdd_mmc1"; 233 regulator-min-microvolt = <3300000>; 234 regulator-max-microvolt = <3300000>; 235 regulator-boot-on; 236 enable-active-high; 237 vin-supply = <&vsys_3v3>; 238 gpio = <&exp1 2 GPIO_ACTIVE_HIGH>; 239 }; 240 241 vdd_sd_dv: regulator-tlv71033 { 242 /* Output of TLV71033 */ 243 compatible = "regulator-gpio"; 244 regulator-name = "tlv71033"; 245 pinctrl-names = "default"; 246 pinctrl-0 = <&vdd_sd_dv_pins_default>; 247 regulator-min-microvolt = <1800000>; 248 regulator-max-microvolt = <3300000>; 249 regulator-boot-on; 250 vin-supply = <&vsys_5v0>; 251 gpios = <&main_gpio0 49 GPIO_ACTIVE_HIGH>; 252 states = <1800000 0x0>, 253 <3300000 0x1>; 254 }; 255 256 dp0_pwr_3v3: regulator-dp0-pwr { 257 compatible = "regulator-fixed"; 258 regulator-name = "dp0-pwr"; 259 regulator-min-microvolt = <3300000>; 260 regulator-max-microvolt = <3300000>; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&dp_pwr_en_pins_default>; 263 gpio = <&main_gpio0 4 0>; /* DP0_3V3 _EN */ 264 enable-active-high; 265 }; 266 267 dp0: connector-dp0 { 268 compatible = "dp-connector"; 269 label = "DP0"; 270 type = "full-size"; 271 dp-pwr-supply = <&dp0_pwr_3v3>; 272 273 port { 274 dp0_connector_in: endpoint { 275 remote-endpoint = <&dp0_out>; 276 }; 277 }; 278 }; 279 280 connector-hdmi { 281 compatible = "hdmi-connector"; 282 label = "hdmi"; 283 type = "a"; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&hdmi_hpd_pins_default>; 286 ddc-i2c-bus = <&mcu_i2c1>; 287 hpd-gpios = <&main_gpio0 0 GPIO_ACTIVE_HIGH>; /* HDMI_HPD */ 288 289 port { 290 hdmi_connector_in: endpoint { 291 remote-endpoint = <&tfp410_out>; 292 }; 293 }; 294 }; 295 296 bridge-dvi { 297 compatible = "ti,tfp410"; 298 pinctrl-names = "default"; 299 pinctrl-0 = <&hdmi_pdn_pins_default>; 300 powerdown-gpios = <&wkup_gpio0 14 GPIO_ACTIVE_LOW>; /* HDMI_PDn */ 301 ti,deskew = <0>; 302 303 ports { 304 #address-cells = <1>; 305 #size-cells = <0>; 306 307 port@0 { 308 reg = <0>; 309 310 tfp410_in: endpoint { 311 remote-endpoint = <&dpi1_out0>; 312 pclk-sample = <1>; 313 }; 314 }; 315 316 port@1 { 317 reg = <1>; 318 319 tfp410_out: endpoint { 320 remote-endpoint = <&hdmi_connector_in>; 321 }; 322 }; 323 }; 324 }; 325 326 csi_mux: mux-controller { 327 compatible = "gpio-mux"; 328 #mux-state-cells = <1>; 329 mux-gpios = <&exp2 1 GPIO_ACTIVE_HIGH>; 330 idle-state = <0>; 331 }; 332 333 transceiver1: can-phy0 { 334 compatible = "ti,tcan1042"; 335 #phy-cells = <0>; 336 max-bitrate = <5000000>; 337 }; 338 339 transceiver2: can-phy1 { 340 compatible = "ti,tcan1042"; 341 #phy-cells = <0>; 342 max-bitrate = <5000000>; 343 }; 344 345 transceiver3: can-phy2 { 346 compatible = "ti,tcan1042"; 347 #phy-cells = <0>; 348 max-bitrate = <5000000>; 349 }; 350 351 transceiver4: can-phy3 { 352 compatible = "ti,tcan1042"; 353 #phy-cells = <0>; 354 max-bitrate = <5000000>; 355 }; 356 357}; 358 359&main_pmx0 { 360 bootph-all; 361 main_uart8_pins_default: main-uart8-default-pins { 362 bootph-all; 363 pinctrl-single,pins = < 364 J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ 365 J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ 366 >; 367 }; 368 369 main_i2c0_pins_default: main-i2c0-default-pins { 370 pinctrl-single,pins = < 371 J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ 372 J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ 373 >; 374 }; 375 376 main_i2c1_pins_default: main-i2c1-default-pins { 377 pinctrl-single,pins = < 378 J784S4_IOPAD(0x0ac, PIN_INPUT_PULLUP, 13) /* (AE34) MCASP0_AXR15.I2C1_SCL */ 379 J784S4_IOPAD(0x0b0, PIN_INPUT_PULLUP, 13) /* (AL33) MCASP1_AXR3.I2C1_SDA */ 380 >; 381 }; 382 383 main_mmc1_pins_default: main-mmc1-default-pins { 384 bootph-all; 385 pinctrl-single,pins = < 386 J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ 387 J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ 388 J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ 389 J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ 390 J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ 391 J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ 392 J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ 393 J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ 394 >; 395 }; 396 397 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 398 pinctrl-single,pins = < 399 J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */ 400 >; 401 }; 402 403 rpi_header_gpio0_pins_default: rpi-header-gpio0-default-pins { 404 pinctrl-single,pins = < 405 J784S4_IOPAD(0x0BC, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */ 406 J784S4_IOPAD(0x06C, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */ 407 J784S4_IOPAD(0x0B4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */ 408 J784S4_IOPAD(0x0C0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */ 409 J784S4_IOPAD(0x00C, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */ 410 J784S4_IOPAD(0x0B8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */ 411 J784S4_IOPAD(0x090, PIN_INPUT, 7) /* (AC35) MCASP0_AXR8.GPIO0_36 */ 412 J784S4_IOPAD(0x0A8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */ 413 J784S4_IOPAD(0x0A4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */ 414 J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */ 415 J784S4_IOPAD(0x0CC, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */ 416 J784S4_IOPAD(0x08C, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */ 417 J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */ 418 J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */ 419 >; 420 }; 421 422 dp0_pins_default: dp0-default-pins { 423 pinctrl-single,pins = < 424 J784S4_IOPAD(0x014, PIN_INPUT, 13) /* (AG33) MCAN14_TX.DP0_HPD */ 425 >; 426 }; 427 428 dp_pwr_en_pins_default: dp-pwr-en-default-pins { 429 pinctrl-single,pins = < 430 J784S4_IOPAD(0x010, PIN_INPUT, 7) /* (AH33) MCAN13_RX.GPIO0_4 */ 431 >; 432 }; 433 434 dss_vout0_pins_default: dss-vout0-default-pins { 435 pinctrl-single,pins = < 436 J784S4_IOPAD(0x074, PIN_OUTPUT, 2) /* (AC33) MCAN2_TX.VOUT0_DATA0 */ 437 J784S4_IOPAD(0x070, PIN_OUTPUT, 2) /* (AH38) MCAN1_RX.VOUT0_DATA1 */ 438 J784S4_IOPAD(0x07c, PIN_OUTPUT, 2) /* (AJ38) MCASP0_AXR3.VOUT0_DATA2 */ 439 J784S4_IOPAD(0x068, PIN_OUTPUT, 2) /* (AE38) MCAN0_RX.VOUT0_DATA3 */ 440 J784S4_IOPAD(0x064, PIN_OUTPUT, 2) /* (AF38) MCAN0_TX.VOUT0_DATA4 */ 441 J784S4_IOPAD(0x060, PIN_OUTPUT, 2) /* (AE36) MCASP2_AXR1.VOUT0_DATA5 */ 442 J784S4_IOPAD(0x05c, PIN_OUTPUT, 2) /* (AC36) MCASP2_AXR0.VOUT0_DATA6 */ 443 J784S4_IOPAD(0x058, PIN_OUTPUT, 2) /* (AE37) MCASP2_AFSX.VOUT0_DATA7 */ 444 J784S4_IOPAD(0x054, PIN_OUTPUT, 2) /* (AD37) MCASP2_ACLKX.VOUT0_DATA8 */ 445 J784S4_IOPAD(0x050, PIN_OUTPUT, 2) /* (AC37) MCASP1_AXR2.VOUT0_DATA9 */ 446 J784S4_IOPAD(0x04c, PIN_OUTPUT, 2) /* (AC32) MCASP1_AXR1.VOUT0_DATA10 */ 447 J784S4_IOPAD(0x048, PIN_OUTPUT, 2) /* (AK33) MCASP0_AXR2.VOUT0_DATA11 */ 448 J784S4_IOPAD(0x044, PIN_OUTPUT, 2) /* (AG37) MCASP0_AXR1.VOUT0_DATA12 */ 449 J784S4_IOPAD(0x040, PIN_OUTPUT, 2) /* (AF37) MCASP0_AXR0.VOUT0_DATA13 */ 450 J784S4_IOPAD(0x03c, PIN_OUTPUT, 2) /* (AK38) MCASP0_AFSX.VOUT0_DATA14 */ 451 J784S4_IOPAD(0x038, PIN_OUTPUT, 2) /* (AK35) MCASP0_ACLKX.VOUT0_DATA15 */ 452 J784S4_IOPAD(0x0c8, PIN_OUTPUT, 2) /* (AJ32) EXT_REFCLK1.VOUT0_DATA16 */ 453 J784S4_IOPAD(0x030, PIN_OUTPUT, 2) /* (AK37) GPIO0_12.VOUT0_DATA17 */ 454 J784S4_IOPAD(0x02c, PIN_OUTPUT, 2) /* (AL32) GPIO0_11.VOUT0_DATA18 */ 455 J784S4_IOPAD(0x028, PIN_OUTPUT, 2) /* (AE33) MCAN16_RX.VOUT0_DATA19 */ 456 J784S4_IOPAD(0x024, PIN_OUTPUT, 2) /* (AH34) MCAN16_TX.VOUT0_DATA20 */ 457 J784S4_IOPAD(0x020, PIN_OUTPUT, 2) /* (AJ35) MCAN15_RX.VOUT0_DATA21 */ 458 J784S4_IOPAD(0x01c, PIN_OUTPUT, 2) /* (AG34) MCAN15_TX.VOUT0_DATA22 */ 459 J784S4_IOPAD(0x018, PIN_OUTPUT, 2) /* (AK36) MCAN14_RX.VOUT0_DATA23 */ 460 J784S4_IOPAD(0x084, PIN_OUTPUT, 2) /* (AG38) MCASP0_AXR5.VOUT0_DE */ 461 J784S4_IOPAD(0x080, PIN_OUTPUT, 2) /* (AK34) MCASP0_AXR4.VOUT0_HSYNC */ 462 J784S4_IOPAD(0x078, PIN_OUTPUT, 2) /* (AH37) MCAN2_RX.VOUT0_PCLK */ 463 J784S4_IOPAD(0x088, PIN_OUTPUT, 2) /* (AF36) MCASP0_AXR6.VOUT0_VSYNC */ 464 >; 465 }; 466 467 hdmi_hpd_pins_default: hdmi-hpd-default-pins { 468 pinctrl-single,pins = < 469 J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTN.GPIO0_0 */ 470 >; 471 }; 472 473 main_mcan6_pins_default: main-mcan6-default-pins { 474 pinctrl-single,pins = < 475 J784S4_IOPAD(0x098, PIN_INPUT, 0) /* (AH36) MCAN6_RX */ 476 J784S4_IOPAD(0x094, PIN_OUTPUT, 0) /* (AG35) MCAN6_TX */ 477 >; 478 }; 479 480 main_mcan7_pins_default: main-mcan7-default-pins { 481 pinctrl-single,pins = < 482 J784S4_IOPAD(0x0A0, PIN_INPUT, 0) /* (AD34) MCAN7_RX */ 483 J784S4_IOPAD(0x09C, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */ 484 >; 485 }; 486 487 main_usbss0_pins_default: main-usbss0-default-pins { 488 pinctrl-single,pins = < 489 J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */ 490 >; 491 }; 492 493}; 494 495&wkup_pmx0 { 496 bootph-all; 497 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 498 pinctrl-single,pins = < 499 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ 500 J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ 501 J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ 502 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ 503 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ 504 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ 505 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ 506 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ 507 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ 508 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ 509 J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ 510 >; 511 }; 512}; 513 514&wkup_pmx2 { 515 bootph-all; 516 pmic_irq_pins_default: pmic-irq-default-pins { 517 pinctrl-single,pins = < 518 /* (AA37) MCU_ADC1_AIN4.WKUP_GPIO0_83 */ 519 J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 7) 520 >; 521 }; 522 523 wkup_uart0_pins_default: wkup-uart0-default-pins { 524 bootph-all; 525 pinctrl-single,pins = < 526 J784S4_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_UART0_CTSn */ 527 J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (L36) WKUP_UART0_RTSn */ 528 J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ 529 J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */ 530 >; 531 }; 532 533 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 534 bootph-all; 535 pinctrl-single,pins = < 536 J784S4_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ 537 J784S4_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ 538 >; 539 }; 540 541 mcu_uart0_pins_default: mcu-uart0-default-pins { 542 bootph-all; 543 pinctrl-single,pins = < 544 J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ 545 J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ 546 >; 547 }; 548 549 mcu_i2c0_pins_default: mcu-i2c0-default-pins { 550 pinctrl-single,pins = < 551 J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT_PULLUP, 0) /* (M35) MCU_I2C0_SCL */ 552 J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT_PULLUP, 0) /* (G34) MCU_I2C0_SDA */ 553 >; 554 }; 555 556 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 557 pinctrl-single,pins = < 558 J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ 559 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ 560 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ 561 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ 562 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ 563 J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ 564 J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ 565 J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ 566 J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ 567 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ 568 J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ 569 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ 570 >; 571 bootph-all; 572 }; 573 574 mcu_mdio_pins_default: mcu-mdio-default-pins { 575 pinctrl-single,pins = < 576 J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ 577 J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ 578 >; 579 bootph-all; 580 }; 581 582 mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-default-pins { 583 pinctrl-single,pins = < 584 J784S4_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (N34) WKUP_GPIO0_66 */ 585 J784S4_WKUP_IOPAD(0x05c, PIN_INPUT, 7) /* (J34) WKUP_GPIO0_1 */ 586 J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */ 587 J784S4_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (H38) WKUP_GPIO0_0 */ 588 J784S4_WKUP_IOPAD(0x0b8, PIN_INPUT, 7) /* (M37) WKUP_GPIO0_56 */ 589 J784S4_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (M36) WKUP_GPIO0_57 */ 590 J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (K37) WKUP_GPIO0_15 */ 591 J784S4_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (J36) WKUP_GPIO0_3 */ 592 J784S4_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (M34) WKUP_GPIO0_67 */ 593 >; 594 }; 595 596 mcu_i2c1_pins_default: mcu-i2c1-default-pins { 597 pinctrl-single,pins = < 598 /* (L35) WKUP_GPIO0_8.MCU_I2C1_SCL */ 599 J784S4_WKUP_IOPAD(0x078, PIN_INPUT_PULLUP, 0) 600 /* (L34) WKUP_GPIO0_9.MCU_I2C1_SDA */ 601 J784S4_WKUP_IOPAD(0x07c, PIN_INPUT_PULLUP, 0) 602 >; 603 }; 604 605 hdmi_pdn_pins_default: hdmi-pdn-default-pins { 606 pinctrl-single,pins = < 607 J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 7) /* (H37) WKUP_GPIO0_14 */ 608 >; 609 }; 610 611 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 612 pinctrl-single,pins = < 613 J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ 614 J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ 615 >; 616 }; 617 618 mcu_mcan1_pins_default: mcu-mcan1-default-pins { 619 pinctrl-single,pins = < 620 J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */ 621 J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0)/* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */ 622 >; 623 }; 624 625}; 626 627&wkup_pmx3 { 628 mcu_rpi_hdr2_gpio0_pins_default: mcu-rpi-hdr2-gpio0-default-pins { 629 pinctrl-single,pins = < 630 J784S4_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (M33) WKUP_GPIO0_49 */ 631 >; 632 }; 633}; 634 635&cpsw_mac_syscon { 636 bootph-all; 637}; 638 639&phy_gmii_sel { 640 bootph-all; 641}; 642 643&mailbox0_cluster0 { 644 status = "okay"; 645 interrupts = <436>; 646 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 647 ti,mbox-rx = <0 0 0>; 648 ti,mbox-tx = <1 0 0>; 649 }; 650 651 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 652 ti,mbox-rx = <2 0 0>; 653 ti,mbox-tx = <3 0 0>; 654 }; 655}; 656 657&mailbox0_cluster1 { 658 status = "okay"; 659 interrupts = <432>; 660 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 661 ti,mbox-rx = <0 0 0>; 662 ti,mbox-tx = <1 0 0>; 663 }; 664 665 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 666 ti,mbox-rx = <2 0 0>; 667 ti,mbox-tx = <3 0 0>; 668 }; 669}; 670 671&mailbox0_cluster2 { 672 status = "okay"; 673 interrupts = <428>; 674 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 675 ti,mbox-rx = <0 0 0>; 676 ti,mbox-tx = <1 0 0>; 677 }; 678 679 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 680 ti,mbox-rx = <2 0 0>; 681 ti,mbox-tx = <3 0 0>; 682 }; 683}; 684 685&mailbox0_cluster3 { 686 status = "okay"; 687 interrupts = <424>; 688 mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { 689 ti,mbox-rx = <0 0 0>; 690 ti,mbox-tx = <1 0 0>; 691 }; 692 693 mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { 694 ti,mbox-rx = <2 0 0>; 695 ti,mbox-tx = <3 0 0>; 696 }; 697}; 698 699&mailbox0_cluster4 { 700 status = "okay"; 701 interrupts = <420>; 702 mbox_c71_0: mbox-c71-0 { 703 ti,mbox-rx = <0 0 0>; 704 ti,mbox-tx = <1 0 0>; 705 }; 706 707 mbox_c71_1: mbox-c71-1 { 708 ti,mbox-rx = <2 0 0>; 709 ti,mbox-tx = <3 0 0>; 710 }; 711}; 712 713&mailbox0_cluster5 { 714 status = "okay"; 715 interrupts = <416>; 716 mbox_c71_2: mbox-c71-2 { 717 ti,mbox-rx = <0 0 0>; 718 ti,mbox-tx = <1 0 0>; 719 }; 720 721 mbox_c71_3: mbox-c71-3 { 722 ti,mbox-rx = <2 0 0>; 723 ti,mbox-tx = <3 0 0>; 724 }; 725}; 726 727&wkup_uart0 { 728 /* Firmware usage */ 729 status = "reserved"; 730 pinctrl-names = "default"; 731 pinctrl-0 = <&wkup_uart0_pins_default>; 732}; 733 734&wkup_i2c0 { 735 bootph-all; 736 status = "okay"; 737 pinctrl-names = "default"; 738 pinctrl-0 = <&wkup_i2c0_pins_default>; 739 clock-frequency = <400000>; 740 741 eeprom@51 { 742 /* AT24C512C-MAHM-T */ 743 compatible = "atmel,24c512"; 744 reg = <0x51>; 745 }; 746 747 tps659413: pmic@48 { 748 compatible = "ti,tps6594-q1"; 749 reg = <0x48>; 750 system-power-controller; 751 pinctrl-names = "default"; 752 pinctrl-0 = <&pmic_irq_pins_default>; 753 interrupt-parent = <&wkup_gpio0>; 754 interrupts = <83 IRQ_TYPE_EDGE_FALLING>; 755 gpio-controller; 756 #gpio-cells = <2>; 757 ti,primary-pmic; 758 buck12-supply = <&vsys_3v3>; 759 buck3-supply = <&vsys_3v3>; 760 buck4-supply = <&vsys_3v3>; 761 buck5-supply = <&vsys_3v3>; 762 ldo1-supply = <&vsys_3v3>; 763 ldo2-supply = <&vsys_3v3>; 764 ldo3-supply = <&vsys_3v3>; 765 ldo4-supply = <&vsys_3v3>; 766 767 regulators { 768 bucka12: buck12 { 769 regulator-name = "vdd_ddr_1v1"; 770 regulator-min-microvolt = <1100000>; 771 regulator-max-microvolt = <1100000>; 772 regulator-boot-on; 773 regulator-always-on; 774 bootph-all; 775 }; 776 777 bucka3: buck3 { 778 regulator-name = "vdd_ram_0v85"; 779 regulator-min-microvolt = <850000>; 780 regulator-max-microvolt = <850000>; 781 regulator-boot-on; 782 regulator-always-on; 783 bootph-all; 784 }; 785 786 bucka4: buck4 { 787 regulator-name = "vdd_io_1v8"; 788 regulator-min-microvolt = <1800000>; 789 regulator-max-microvolt = <1800000>; 790 regulator-boot-on; 791 regulator-always-on; 792 bootph-all; 793 }; 794 795 bucka5: buck5 { 796 regulator-name = "vdd_mcu_0v85"; 797 regulator-min-microvolt = <850000>; 798 regulator-max-microvolt = <850000>; 799 regulator-boot-on; 800 regulator-always-on; 801 bootph-all; 802 }; 803 804 ldoa1: ldo1 { 805 regulator-name = "vdd_mcuio_1v8"; 806 regulator-min-microvolt = <1800000>; 807 regulator-max-microvolt = <1800000>; 808 regulator-boot-on; 809 regulator-always-on; 810 bootph-all; 811 }; 812 813 ldoa2: ldo2 { 814 regulator-name = "vdd_mcuio_3v3"; 815 regulator-min-microvolt = <3300000>; 816 regulator-max-microvolt = <3300000>; 817 regulator-boot-on; 818 regulator-always-on; 819 bootph-all; 820 }; 821 822 ldoa3: ldo3 { 823 regulator-name = "vds_dll_0v8"; 824 regulator-min-microvolt = <800000>; 825 regulator-max-microvolt = <800000>; 826 regulator-boot-on; 827 regulator-always-on; 828 bootph-all; 829 }; 830 831 ldoa4: ldo4 { 832 regulator-name = "vda_mcu_1v8"; 833 regulator-min-microvolt = <1800000>; 834 regulator-max-microvolt = <1800000>; 835 regulator-boot-on; 836 regulator-always-on; 837 bootph-all; 838 }; 839 }; 840 }; 841 842 tps62873a: regulator@40 { 843 compatible = "ti,tps62873"; 844 reg = <0x40>; 845 bootph-pre-ram; 846 regulator-name = "VDD_CPU_AVS"; 847 regulator-min-microvolt = <600000>; 848 regulator-max-microvolt = <900000>; 849 regulator-boot-on; 850 regulator-always-on; 851 }; 852 853 tps62873b: regulator@43 { 854 compatible = "ti,tps62873"; 855 reg = <0x43>; 856 regulator-name = "VDD_CORE_0V8"; 857 regulator-min-microvolt = <760000>; 858 regulator-max-microvolt = <840000>; 859 regulator-boot-on; 860 regulator-always-on; 861 }; 862}; 863 864&wkup_gpio0 { 865 status = "okay"; 866 pinctrl-names = "default"; 867 pinctrl-0 = <&mcu_rpi_hdr1_gpio0_pins_default>, <&mcu_rpi_hdr2_gpio0_pins_default>; 868}; 869 870&mcu_uart0 { 871 bootph-all; 872 status = "okay"; 873 pinctrl-names = "default"; 874 pinctrl-0 = <&mcu_uart0_pins_default>; 875}; 876 877&mcu_i2c0 { 878 status = "okay"; 879 pinctrl-names = "default"; 880 pinctrl-0 = <&mcu_i2c0_pins_default>; 881 clock-frequency = <400000>; 882}; 883 884&main_uart8 { 885 bootph-all; 886 status = "okay"; 887 pinctrl-names = "default"; 888 pinctrl-0 = <&main_uart8_pins_default>; 889}; 890 891&main_i2c0 { 892 status = "okay"; 893 pinctrl-names = "default"; 894 pinctrl-0 = <&main_i2c0_pins_default>; 895 clock-frequency = <400000>; 896 897 exp1: gpio@21 { 898 compatible = "ti,tca6416"; 899 reg = <0x21>; 900 gpio-controller; 901 #gpio-cells = <2>; 902 gpio-line-names = "BOARDID_EEPROM_WP", "CAN_STB", "GPIO_uSD_PWR_EN", 903 "IO_EXP_MCU_RGMII_RST#", "IO_EXP_PCIe0_4L_PERST#", 904 "IO_EXP_PCIe1_M.2_RTSz", "IO_EXP_PCIe3_M.2_RTSz", 905 "PM_INA_BUS_EN", "ENET1_EXP_PWRDN", "EXP1_ENET_RSTz", 906 "ENET1_I2CMUX_SEL", "PCIe0_CLKREQ#", "PCIe1_M.2_CLKREQ#", 907 "PCIe3_M2_CLKREQ#", "PCIe0_PRSNT2#_1", "PCIe0_PRSNT2#_2"; 908 }; 909}; 910 911&main_i2c1 { 912 pinctrl-names = "default"; 913 pinctrl-0 = <&main_i2c1_pins_default>; 914 clock-frequency = <400000>; 915 status = "okay"; 916 917 exp2: gpio@21 { 918 compatible = "ti,tca6408"; 919 reg = <0x21>; 920 gpio-controller; 921 #gpio-cells = <2>; 922 gpio-line-names = "CSI_VIO_SEL", "CSI_MUX_SEL_2", "CSI2_RSTz", 923 "IO_EXP_CAM0_GPIO1", "IO_EXP_CAM1_GPIO1"; 924 }; 925 926 i2c-mux@70 { 927 compatible = "nxp,pca9543"; 928 #address-cells = <1>; 929 #size-cells = <0>; 930 reg = <0x70>; 931 932 cam0_i2c: i2c@0 { 933 #address-cells = <1>; 934 #size-cells = <0>; 935 reg = <0>; 936 }; 937 938 cam1_i2c: i2c@1 { 939 #address-cells = <1>; 940 #size-cells = <0>; 941 reg = <1>; 942 }; 943 944 }; 945}; 946 947&main_sdhci0 { 948 bootph-all; 949 /* eMMC */ 950 status = "okay"; 951 non-removable; 952 ti,driver-strength-ohm = <50>; 953}; 954 955&main_sdhci1 { 956 bootph-all; 957 /* SD card */ 958 status = "okay"; 959 pinctrl-0 = <&main_mmc1_pins_default>; 960 pinctrl-names = "default"; 961 disable-wp; 962 vmmc-supply = <&vdd_mmc1>; 963 vqmmc-supply = <&vdd_sd_dv>; 964}; 965 966&main_gpio0 { 967 status = "okay"; 968 pinctrl-names = "default"; 969 pinctrl-0 = <&rpi_header_gpio0_pins_default>; 970}; 971 972&mcu_cpsw { 973 status = "okay"; 974 pinctrl-names = "default"; 975 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; 976}; 977 978&davinci_mdio { 979 mcu_phy0: ethernet-phy@0 { 980 reg = <0>; 981 bootph-all; 982 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 983 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 984 ti,min-output-impedance; 985 }; 986}; 987 988&mcu_cpsw_port1 { 989 status = "okay"; 990 phy-mode = "rgmii-rxid"; 991 phy-handle = <&mcu_phy0>; 992 bootph-all; 993}; 994 995&mcu_r5fss0_core0 { 996 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 997 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 998 <&mcu_r5fss0_core0_memory_region>; 999}; 1000 1001&mcu_r5fss0_core1 { 1002 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 1003 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 1004 <&mcu_r5fss0_core1_memory_region>; 1005}; 1006 1007&main_r5fss0 { 1008 ti,cluster-mode = <0>; 1009}; 1010 1011&main_r5fss1 { 1012 ti,cluster-mode = <0>; 1013}; 1014 1015/* Timers are used by Remoteproc firmware */ 1016&main_timer0 { 1017 status = "reserved"; 1018}; 1019 1020&main_timer1 { 1021 status = "reserved"; 1022}; 1023 1024&main_timer2 { 1025 status = "reserved"; 1026}; 1027 1028&main_timer3 { 1029 status = "reserved"; 1030}; 1031 1032&main_timer4 { 1033 status = "reserved"; 1034}; 1035 1036&main_timer5 { 1037 status = "reserved"; 1038}; 1039 1040&main_timer6 { 1041 status = "reserved"; 1042}; 1043 1044&main_timer7 { 1045 status = "reserved"; 1046}; 1047 1048&main_timer8 { 1049 status = "reserved"; 1050}; 1051 1052&main_timer9 { 1053 status = "reserved"; 1054}; 1055 1056&main_r5fss2 { 1057 ti,cluster-mode = <0>; 1058}; 1059 1060&main_r5fss0_core0 { 1061 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 1062 memory-region = <&main_r5fss0_core0_dma_memory_region>, 1063 <&main_r5fss0_core0_memory_region>; 1064}; 1065 1066&main_r5fss0_core1 { 1067 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 1068 memory-region = <&main_r5fss0_core1_dma_memory_region>, 1069 <&main_r5fss0_core1_memory_region>; 1070}; 1071 1072&main_r5fss1_core0 { 1073 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 1074 memory-region = <&main_r5fss1_core0_dma_memory_region>, 1075 <&main_r5fss1_core0_memory_region>; 1076}; 1077 1078&main_r5fss1_core1 { 1079 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 1080 memory-region = <&main_r5fss1_core1_dma_memory_region>, 1081 <&main_r5fss1_core1_memory_region>; 1082}; 1083 1084&main_r5fss2_core0 { 1085 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; 1086 memory-region = <&main_r5fss2_core0_dma_memory_region>, 1087 <&main_r5fss2_core0_memory_region>; 1088}; 1089 1090&main_r5fss2_core1 { 1091 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; 1092 memory-region = <&main_r5fss2_core1_dma_memory_region>, 1093 <&main_r5fss2_core1_memory_region>; 1094}; 1095 1096&c71_0 { 1097 status = "okay"; 1098 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 1099 memory-region = <&c71_0_dma_memory_region>, 1100 <&c71_0_memory_region>; 1101}; 1102 1103&c71_1 { 1104 status = "okay"; 1105 mboxes = <&mailbox0_cluster4 &mbox_c71_1>; 1106 memory-region = <&c71_1_dma_memory_region>, 1107 <&c71_1_memory_region>; 1108}; 1109 1110&c71_2 { 1111 status = "okay"; 1112 mboxes = <&mailbox0_cluster5 &mbox_c71_2>; 1113 memory-region = <&c71_2_dma_memory_region>, 1114 <&c71_2_memory_region>; 1115}; 1116 1117&c71_3 { 1118 status = "okay"; 1119 mboxes = <&mailbox0_cluster5 &mbox_c71_3>; 1120 memory-region = <&c71_3_dma_memory_region>, 1121 <&c71_3_memory_region>; 1122}; 1123 1124&wkup_gpio_intr { 1125 status = "okay"; 1126}; 1127 1128&mcu_i2c1 { 1129 status = "okay"; 1130 pinctrl-names = "default"; 1131 pinctrl-0 = <&mcu_i2c1_pins_default>; 1132 clock-frequency = <100000>; 1133}; 1134 1135&serdes_refclk { 1136 status = "okay"; 1137 clock-frequency = <100000000>; 1138}; 1139 1140&dss { 1141 status = "okay"; 1142 pinctrl-names = "default"; 1143 pinctrl-0 = <&dss_vout0_pins_default>; 1144 assigned-clocks = <&k3_clks 218 2>, 1145 <&k3_clks 218 5>; 1146 assigned-clock-parents = <&k3_clks 218 3>, 1147 <&k3_clks 218 7>; 1148}; 1149 1150&serdes_wiz4 { 1151 status = "okay"; 1152}; 1153 1154&serdes4 { 1155 status = "okay"; 1156 serdes4_dp_link: phy@0 { 1157 reg = <0>; 1158 cdns,num-lanes = <4>; 1159 #phy-cells = <0>; 1160 cdns,phy-type = <PHY_TYPE_DP>; 1161 resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, 1162 <&serdes_wiz4 3>, <&serdes_wiz4 4>; 1163 }; 1164}; 1165 1166&mhdp { 1167 status = "okay"; 1168 pinctrl-names = "default"; 1169 pinctrl-0 = <&dp0_pins_default>; 1170 phys = <&serdes4_dp_link>; 1171 phy-names = "dpphy"; 1172}; 1173 1174&dss_ports { 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 1178 /* DP */ 1179 port@0 { 1180 reg = <0>; 1181 1182 dpi0_out: endpoint { 1183 remote-endpoint = <&dp0_in>; 1184 }; 1185 }; 1186 1187 /* HDMI */ 1188 port@1 { 1189 reg = <1>; 1190 1191 dpi1_out0: endpoint { 1192 remote-endpoint = <&tfp410_in>; 1193 }; 1194 }; 1195}; 1196 1197&dp0_ports { 1198 1199 port@0 { 1200 reg = <0>; 1201 1202 dp0_in: endpoint { 1203 remote-endpoint = <&dpi0_out>; 1204 }; 1205 }; 1206 1207 port@4 { 1208 reg = <4>; 1209 1210 dp0_out: endpoint { 1211 remote-endpoint = <&dp0_connector_in>; 1212 }; 1213 }; 1214}; 1215 1216&mcu_mcan0 { 1217 status = "okay"; 1218 pinctrl-names = "default"; 1219 pinctrl-0 = <&mcu_mcan0_pins_default>; 1220 phys = <&transceiver1>; 1221}; 1222 1223&mcu_mcan1 { 1224 status = "okay"; 1225 pinctrl-names = "default"; 1226 pinctrl-0 = <&mcu_mcan1_pins_default>; 1227 phys = <&transceiver2>; 1228}; 1229 1230&main_mcan6 { 1231 status = "okay"; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&main_mcan6_pins_default>; 1234 phys = <&transceiver3>; 1235}; 1236 1237&main_mcan7 { 1238 status = "okay"; 1239 pinctrl-names = "default"; 1240 pinctrl-0 = <&main_mcan7_pins_default>; 1241 phys = <&transceiver4>; 1242}; 1243 1244&ospi0 { 1245 status = "okay"; 1246 pinctrl-names = "default"; 1247 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 1248 1249 flash@0 { 1250 compatible = "jedec,spi-nor"; 1251 reg = <0x0>; 1252 spi-tx-bus-width = <8>; 1253 spi-rx-bus-width = <8>; 1254 spi-max-frequency = <25000000>; 1255 cdns,tshsl-ns = <60>; 1256 cdns,tsd2d-ns = <60>; 1257 cdns,tchsh-ns = <60>; 1258 cdns,tslch-ns = <60>; 1259 cdns,read-delay = <4>; 1260 1261 partitions { 1262 bootph-all; 1263 compatible = "fixed-partitions"; 1264 #address-cells = <1>; 1265 #size-cells = <1>; 1266 1267 partition@0 { 1268 label = "ospi.tiboot3"; 1269 reg = <0x0 0x100000>; 1270 }; 1271 1272 partition@100000 { 1273 label = "ospi.tispl"; 1274 reg = <0x100000 0x200000>; 1275 }; 1276 1277 partition@300000 { 1278 label = "ospi.u-boot"; 1279 reg = <0x300000 0x400000>; 1280 }; 1281 1282 partition@700000 { 1283 label = "ospi.env"; 1284 reg = <0x700000 0x40000>; 1285 }; 1286 1287 partition@740000 { 1288 label = "ospi.env.backup"; 1289 reg = <0x740000 0x40000>; 1290 }; 1291 1292 partition@800000 { 1293 label = "ospi.rootfs"; 1294 reg = <0x800000 0x37c0000>; 1295 }; 1296 1297 partition@3fc0000 { 1298 bootph-pre-ram; 1299 label = "ospi.phypattern"; 1300 reg = <0x3fc0000 0x40000>; 1301 }; 1302 }; 1303 }; 1304}; 1305 1306&serdes_ln_ctrl { 1307 idle-states = <J784S4_SERDES0_LANE0_PCIE1_LANE0>, <J784S4_SERDES0_LANE1_PCIE1_LANE1>, 1308 <J784S4_SERDES0_LANE2_PCIE3_LANE0>, <J784S4_SERDES0_LANE3_USB>, 1309 <J784S4_SERDES1_LANE0_PCIE0_LANE0>, <J784S4_SERDES1_LANE1_PCIE0_LANE1>, 1310 <J784S4_SERDES1_LANE2_PCIE0_LANE2>, <J784S4_SERDES1_LANE3_PCIE0_LANE3>, 1311 <J784S4_SERDES2_LANE0_IP2_UNUSED>, <J784S4_SERDES2_LANE1_IP2_UNUSED>, 1312 <J784S4_SERDES2_LANE2_QSGMII_LANE1>, <J784S4_SERDES2_LANE3_QSGMII_LANE2>, 1313 <J784S4_SERDES4_LANE0_EDP_LANE0>, <J784S4_SERDES4_LANE1_EDP_LANE1>, 1314 <J784S4_SERDES4_LANE2_EDP_LANE2>, <J784S4_SERDES4_LANE3_EDP_LANE3>; 1315}; 1316 1317&serdes_wiz0 { 1318 status = "okay"; 1319}; 1320 1321&serdes0 { 1322 status = "okay"; 1323 1324 serdes0_pcie_link: phy@0 { 1325 reg = <0>; 1326 cdns,num-lanes = <3>; 1327 #phy-cells = <0>; 1328 cdns,phy-type = <PHY_TYPE_PCIE>; 1329 resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>, <&serdes_wiz0 3>; 1330 }; 1331 1332 serdes0_usb_link: phy@3 { 1333 reg = <3>; 1334 cdns,num-lanes = <1>; 1335 #phy-cells = <0>; 1336 cdns,phy-type = <PHY_TYPE_USB3>; 1337 resets = <&serdes_wiz0 4>; 1338 }; 1339}; 1340 1341&serdes_wiz1 { 1342 status = "okay"; 1343}; 1344 1345&serdes1 { 1346 status = "okay"; 1347 1348 serdes1_pcie_link: phy@0 { 1349 reg = <0>; 1350 cdns,num-lanes = <4>; 1351 #phy-cells = <0>; 1352 cdns,phy-type = <PHY_TYPE_PCIE>; 1353 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>, <&serdes_wiz1 3>, <&serdes_wiz1 4>; 1354 }; 1355}; 1356 1357&pcie0_rc { 1358 status = "okay"; 1359 reset-gpios = <&exp1 4 GPIO_ACTIVE_HIGH>; 1360 phys = <&serdes1_pcie_link>; 1361 phy-names = "pcie-phy"; 1362}; 1363 1364&pcie1_rc { 1365 status = "okay"; 1366 reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; 1367 phys = <&serdes0_pcie_link>; 1368 phy-names = "pcie-phy"; 1369 num-lanes = <2>; 1370}; 1371 1372&pcie3_rc { 1373 status = "okay"; 1374 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; 1375 phys = <&serdes0_pcie_link>; 1376 phy-names = "pcie-phy"; 1377 num-lanes = <1>; 1378}; 1379 1380&usb_serdes_mux { 1381 idle-states = <0>; /* USB0 to SERDES0 */ 1382}; 1383 1384&usbss0 { 1385 status = "okay"; 1386 pinctrl-0 = <&main_usbss0_pins_default>; 1387 pinctrl-names = "default"; 1388 ti,vbus-divider; 1389}; 1390 1391&usb0 { 1392 status = "okay"; 1393 dr_mode = "otg"; 1394 maximum-speed = "super-speed"; 1395 phys = <&serdes0_usb_link>; 1396 phy-names = "cdns3,usb3-phy"; 1397}; 1398