1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) Siemens AG, 2018-2023 4 * 5 * Authors: 6 * Chao Zeng <chao.zeng@siemens.com> 7 * Jan Kiszka <jan.kiszka@siemens.com> 8 * 9 * AM6548-based (quad-core) IOT2050 M.2 variant (based on Advanced Product 10 * Generation 2), 2 GB RAM, 16 GB eMMC, USB-serial converter on connector X30 11 * 12 * Product homepage: 13 * https://new.siemens.com/global/en/products/automation/pc-based/iot-gateways/simatic-iot2050.html 14 */ 15 16#include "k3-am6548-iot2050-advanced-common.dtsi" 17#include "k3-am65-iot2050-common-pg2.dtsi" 18 19/ { 20 compatible = "siemens,iot2050-advanced-m2", "ti,am654"; 21 model = "SIMATIC IOT2050 Advanced M2"; 22}; 23 24&mcu_r5fss0 { 25 /* lock-step mode not supported on this board */ 26 ti,cluster-mode = <0>; 27}; 28 29&main_pmx0 { 30 main_bkey_pcie_reset: main-bkey-pcie-reset-default-pins { 31 pinctrl-single,pins = < 32 AM65X_IOPAD(0x01bc, PIN_OUTPUT_PULLUP, 7) /* (AG13) GPIO1_15 */ 33 >; 34 }; 35 36 main_pmx0_m2_config_pins_default: main-pmx0-m2-config-default-pins { 37 pinctrl-single,pins = < 38 AM65X_IOPAD(0x01c8, PIN_INPUT_PULLUP, 7) /* (AE13) GPIO1_18 */ 39 AM65X_IOPAD(0x01cc, PIN_INPUT_PULLUP, 7) /* (AD13) GPIO1_19 */ 40 >; 41 }; 42 43 main_m2_pcie_mux_control: main-m2-pcie-mux-control-default-pins { 44 pinctrl-single,pins = < 45 AM65X_IOPAD(0x0148, PIN_INPUT_PULLUP, 7) /* (AG22) GPIO0_82 */ 46 AM65X_IOPAD(0x0160, PIN_INPUT_PULLUP, 7) /* (AE20) GPIO0_88 */ 47 AM65X_IOPAD(0x0164, PIN_INPUT_PULLUP, 7) /* (AF19) GPIO0_89 */ 48 >; 49 }; 50}; 51 52&main_pmx1 { 53 main_pmx1_m2_config_pins_default: main-pmx1-m2-config-default-pins { 54 pinctrl-single,pins = < 55 AM65X_IOPAD(0x0018, PIN_INPUT_PULLUP, 7) /* (B22) GPIO1_88 */ 56 AM65X_IOPAD(0x001c, PIN_INPUT_PULLUP, 7) /* (C23) GPIO1_89 */ 57 >; 58 }; 59}; 60 61&main_gpio0 { 62 pinctrl-names = "default"; 63 pinctrl-0 = <&main_m2_pcie_mux_control>; 64}; 65 66&main_gpio1 { 67 pinctrl-names = "default"; 68 pinctrl-0 = 69 <&main_pcie_enable_pins_default>, 70 <&main_pmx0_m2_config_pins_default>, 71 <&main_pmx1_m2_config_pins_default>, 72 <&cp2102n_reset_pin_default>; 73}; 74 75/* 76 * Base configuration for B-key slot with PCIe x2, E-key with USB 2.0 only. 77 * Firmware switches to other modes via device tree overlays. 78 */ 79 80&serdes0 { 81 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; 82 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; 83}; 84 85&pcie0_rc { 86 pinctrl-names = "default"; 87 pinctrl-0 = <&main_bkey_pcie_reset>; 88 89 num-lanes = <2>; 90 phys = <&serdes0 PHY_TYPE_PCIE 1>, <&serdes1 PHY_TYPE_PCIE 1>; 91 phy-names = "pcie-phy0","pcie-phy1"; 92 reset-gpios = <&main_gpio1 15 GPIO_ACTIVE_HIGH>; 93 status = "okay"; 94}; 95 96&pcie1_rc { 97 status = "disabled"; 98}; 99 100&dwc3_0 { 101 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 102 <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ 103 /delete-property/ phys; 104 /delete-property/ phy-names; 105}; 106 107&usb0 { 108 maximum-speed = "high-speed"; 109 /delete-property/ snps,dis-u1-entry-quirk; 110 /delete-property/ snps,dis-u2-entry-quirk; 111}; 112