1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include "k3-am654.dtsi" 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/net/ti-dp83867.h> 11 12/ { 13 compatible = "ti,am654-evm", "ti,am654"; 14 model = "Texas Instruments AM654 Base Board"; 15 16 chosen { 17 stdout-path = "serial2:115200n8"; 18 bootargs = "earlycon=ns16550a,mmio32,0x02800000"; 19 }; 20 21 memory@80000000 { 22 device_type = "memory"; 23 /* 4G RAM */ 24 reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 25 <0x00000008 0x80000000 0x00000000 0x80000000>; 26 }; 27 28 reserved-memory { 29 #address-cells = <2>; 30 #size-cells = <2>; 31 ranges; 32 33 secure_ddr: secure-ddr@9e800000 { 34 reg = <0 0x9e800000 0 0x01800000>; /* for OP-TEE */ 35 alignment = <0x1000>; 36 no-map; 37 }; 38 39 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 40 compatible = "shared-dma-pool"; 41 reg = <0 0xa0000000 0 0x100000>; 42 no-map; 43 }; 44 45 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 46 compatible = "shared-dma-pool"; 47 reg = <0 0xa0100000 0 0xf00000>; 48 no-map; 49 }; 50 51 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 52 compatible = "shared-dma-pool"; 53 reg = <0 0xa1000000 0 0x100000>; 54 no-map; 55 }; 56 57 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 58 compatible = "shared-dma-pool"; 59 reg = <0 0xa1100000 0 0xf00000>; 60 no-map; 61 }; 62 63 rtos_ipc_memory_region: ipc-memories@a2000000 { 64 reg = <0x00 0xa2000000 0x00 0x00100000>; 65 alignment = <0x1000>; 66 no-map; 67 }; 68 }; 69 70 gpio-keys { 71 compatible = "gpio-keys"; 72 autorepeat; 73 pinctrl-names = "default"; 74 pinctrl-0 = <&push_button_pins_default>; 75 76 sw5 { 77 label = "GPIO Key USER1"; 78 linux,code = <BTN_0>; 79 gpios = <&wkup_gpio0 24 GPIO_ACTIVE_LOW>; 80 }; 81 82 sw6 { 83 label = "GPIO Key USER2"; 84 linux,code = <BTN_1>; 85 gpios = <&wkup_gpio0 27 GPIO_ACTIVE_LOW>; 86 }; 87 }; 88}; 89 90&wkup_pmx0 { 91 wkup_i2c0_pins_default: wkup-i2c0-pins-default { 92 pinctrl-single,pins = < 93 AM65X_WKUP_IOPAD(0x00e0, PIN_INPUT, 0) /* (AC7) WKUP_I2C0_SCL */ 94 AM65X_WKUP_IOPAD(0x00e4, PIN_INPUT, 0) /* (AD6) WKUP_I2C0_SDA */ 95 >; 96 }; 97 98 push_button_pins_default: push-button-pins-default { 99 pinctrl-single,pins = < 100 AM65X_WKUP_IOPAD(0x0030, PIN_INPUT, 7) /* (R5) WKUP_GPIO0_24 */ 101 AM65X_WKUP_IOPAD(0x003c, PIN_INPUT, 7) /* (P2) WKUP_GPIO0_27 */ 102 >; 103 }; 104 105 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { 106 pinctrl-single,pins = < 107 AM65X_WKUP_IOPAD(0x0000, PIN_OUTPUT, 0) /* (V1) MCU_OSPI0_CLK */ 108 AM65X_WKUP_IOPAD(0x0008, PIN_INPUT, 0) /* (U2) MCU_OSPI0_DQS */ 109 AM65X_WKUP_IOPAD(0x000c, PIN_INPUT, 0) /* (U4) MCU_OSPI0_D0 */ 110 AM65X_WKUP_IOPAD(0x0010, PIN_INPUT, 0) /* (U5) MCU_OSPI0_D1 */ 111 AM65X_WKUP_IOPAD(0x0014, PIN_INPUT, 0) /* (T2) MCU_OSPI0_D2 */ 112 AM65X_WKUP_IOPAD(0x0018, PIN_INPUT, 0) /* (T3) MCU_OSPI0_D3 */ 113 AM65X_WKUP_IOPAD(0x001c, PIN_INPUT, 0) /* (T4) MCU_OSPI0_D4 */ 114 AM65X_WKUP_IOPAD(0x0020, PIN_INPUT, 0) /* (T5) MCU_OSPI0_D5 */ 115 AM65X_WKUP_IOPAD(0x0024, PIN_INPUT, 0) /* (R2) MCU_OSPI0_D6 */ 116 AM65X_WKUP_IOPAD(0x0028, PIN_INPUT, 0) /* (R3) MCU_OSPI0_D7 */ 117 AM65X_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* (R4) MCU_OSPI0_CSn0 */ 118 >; 119 }; 120 121 wkup_pca554_default: wkup-pca554-default { 122 pinctrl-single,pins = < 123 AM65X_WKUP_IOPAD(0x0034, PIN_INPUT, 7) /* (T1) MCU_OSPI1_CLK.WKUP_GPIO0_25 */ 124 >; 125 }; 126 127 mcu_cpsw_pins_default: mcu-cpsw-pins-default { 128 pinctrl-single,pins = < 129 AM65X_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */ 130 AM65X_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */ 131 AM65X_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */ 132 AM65X_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */ 133 AM65X_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */ 134 AM65X_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */ 135 AM65X_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */ 136 AM65X_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */ 137 AM65X_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */ 138 AM65X_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */ 139 AM65X_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */ 140 AM65X_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */ 141 >; 142 }; 143 144 mcu_mdio_pins_default: mcu-mdio1-pins-default { 145 pinctrl-single,pins = < 146 AM65X_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */ 147 AM65X_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */ 148 >; 149 }; 150}; 151 152&main_pmx0 { 153 main_uart0_pins_default: main-uart0-pins-default { 154 pinctrl-single,pins = < 155 AM65X_IOPAD(0x01e4, PIN_INPUT, 0) /* (AF11) UART0_RXD */ 156 AM65X_IOPAD(0x01e8, PIN_OUTPUT, 0) /* (AE11) UART0_TXD */ 157 AM65X_IOPAD(0x01ec, PIN_INPUT, 0) /* (AG11) UART0_CTSn */ 158 AM65X_IOPAD(0x01f0, PIN_OUTPUT, 0) /* (AD11) UART0_RTSn */ 159 >; 160 }; 161 162 main_i2c2_pins_default: main-i2c2-pins-default { 163 pinctrl-single,pins = < 164 AM65X_IOPAD(0x0074, PIN_INPUT, 5) /* (T27) GPMC0_CSn3.I2C2_SCL */ 165 AM65X_IOPAD(0x0070, PIN_INPUT, 5) /* (R25) GPMC0_CSn2.I2C2_SDA */ 166 >; 167 }; 168 169 main_spi0_pins_default: main-spi0-pins-default { 170 pinctrl-single,pins = < 171 AM65X_IOPAD(0x01c4, PIN_INPUT, 0) /* (AH13) SPI0_CLK */ 172 AM65X_IOPAD(0x01c8, PIN_INPUT, 0) /* (AE13) SPI0_D0 */ 173 AM65X_IOPAD(0x01cc, PIN_INPUT, 0) /* (AD13) SPI0_D1 */ 174 AM65X_IOPAD(0x01bc, PIN_OUTPUT, 0) /* (AG13) SPI0_CS0 */ 175 >; 176 }; 177 178 main_mmc0_pins_default: main-mmc0-pins-default { 179 pinctrl-single,pins = < 180 AM65X_IOPAD(0x01a8, PIN_INPUT_PULLDOWN, 0) /* (B25) MMC0_CLK */ 181 AM65X_IOPAD(0x01ac, PIN_INPUT_PULLUP, 0) /* (B27) MMC0_CMD */ 182 AM65X_IOPAD(0x01a4, PIN_INPUT_PULLUP, 0) /* (A26) MMC0_DAT0 */ 183 AM65X_IOPAD(0x01a0, PIN_INPUT_PULLUP, 0) /* (E25) MMC0_DAT1 */ 184 AM65X_IOPAD(0x019c, PIN_INPUT_PULLUP, 0) /* (C26) MMC0_DAT2 */ 185 AM65X_IOPAD(0x0198, PIN_INPUT_PULLUP, 0) /* (A25) MMC0_DAT3 */ 186 AM65X_IOPAD(0x0194, PIN_INPUT_PULLUP, 0) /* (E24) MMC0_DAT4 */ 187 AM65X_IOPAD(0x0190, PIN_INPUT_PULLUP, 0) /* (A24) MMC0_DAT5 */ 188 AM65X_IOPAD(0x018c, PIN_INPUT_PULLUP, 0) /* (B26) MMC0_DAT6 */ 189 AM65X_IOPAD(0x0188, PIN_INPUT_PULLUP, 0) /* (D25) MMC0_DAT7 */ 190 AM65X_IOPAD(0x01b4, PIN_INPUT_PULLUP, 0) /* (A23) MMC0_SDCD */ 191 AM65X_IOPAD(0x01b0, PIN_INPUT, 0) /* (C25) MMC0_DS */ 192 >; 193 }; 194 195 main_mmc1_pins_default: main-mmc1-pins-default { 196 pinctrl-single,pins = < 197 AM65X_IOPAD(0x02d4, PIN_INPUT_PULLDOWN, 0) /* (C27) MMC1_CLK */ 198 AM65X_IOPAD(0x02d8, PIN_INPUT_PULLUP, 0) /* (C28) MMC1_CMD */ 199 AM65X_IOPAD(0x02d0, PIN_INPUT_PULLUP, 0) /* (D28) MMC1_DAT0 */ 200 AM65X_IOPAD(0x02cc, PIN_INPUT_PULLUP, 0) /* (E27) MMC1_DAT1 */ 201 AM65X_IOPAD(0x02c8, PIN_INPUT_PULLUP, 0) /* (D26) MMC1_DAT2 */ 202 AM65X_IOPAD(0x02c4, PIN_INPUT_PULLUP, 0) /* (D27) MMC1_DAT3 */ 203 AM65X_IOPAD(0x02dc, PIN_INPUT_PULLUP, 0) /* (B24) MMC1_SDCD */ 204 AM65X_IOPAD(0x02e0, PIN_INPUT, 0) /* (C24) MMC1_SDWP */ 205 >; 206 }; 207 208 usb1_pins_default: usb1-pins-default { 209 pinctrl-single,pins = < 210 AM65X_IOPAD(0x02c0, PIN_OUTPUT, 0) /* (AC8) USB1_DRVVBUS */ 211 >; 212 }; 213}; 214 215&main_pmx1 { 216 main_i2c0_pins_default: main-i2c0-pins-default { 217 pinctrl-single,pins = < 218 AM65X_IOPAD(0x0000, PIN_INPUT, 0) /* (D20) I2C0_SCL */ 219 AM65X_IOPAD(0x0004, PIN_INPUT, 0) /* (C21) I2C0_SDA */ 220 >; 221 }; 222 223 main_i2c1_pins_default: main-i2c1-pins-default { 224 pinctrl-single,pins = < 225 AM65X_IOPAD(0x0008, PIN_INPUT, 0) /* (B21) I2C1_SCL */ 226 AM65X_IOPAD(0x000c, PIN_INPUT, 0) /* (E21) I2C1_SDA */ 227 >; 228 }; 229 230 ecap0_pins_default: ecap0-pins-default { 231 pinctrl-single,pins = < 232 AM65X_IOPAD(0x0010, PIN_INPUT, 0) /* (D21) ECAP0_IN_APWM_OUT */ 233 >; 234 }; 235}; 236 237&wkup_uart0 { 238 /* Wakeup UART is used by System firmware */ 239 status = "reserved"; 240}; 241 242&main_uart0 { 243 pinctrl-names = "default"; 244 pinctrl-0 = <&main_uart0_pins_default>; 245 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; 246}; 247 248&wkup_i2c0 { 249 pinctrl-names = "default"; 250 pinctrl-0 = <&wkup_i2c0_pins_default>; 251 clock-frequency = <400000>; 252 253 pca9554: gpio@39 { 254 compatible = "nxp,pca9554"; 255 reg = <0x39>; 256 gpio-controller; 257 #gpio-cells = <2>; 258 pinctrl-names = "default"; 259 pinctrl-0 = <&wkup_pca554_default>; 260 interrupt-parent = <&wkup_gpio0>; 261 interrupts = <25 IRQ_TYPE_EDGE_FALLING>; 262 interrupt-controller; 263 #interrupt-cells = <2>; 264 }; 265}; 266 267&main_i2c0 { 268 pinctrl-names = "default"; 269 pinctrl-0 = <&main_i2c0_pins_default>; 270 clock-frequency = <400000>; 271 272 pca9555: gpio@21 { 273 compatible = "nxp,pca9555"; 274 reg = <0x21>; 275 gpio-controller; 276 #gpio-cells = <2>; 277 }; 278}; 279 280&main_i2c1 { 281 pinctrl-names = "default"; 282 pinctrl-0 = <&main_i2c1_pins_default>; 283 clock-frequency = <400000>; 284}; 285 286&main_i2c2 { 287 pinctrl-names = "default"; 288 pinctrl-0 = <&main_i2c2_pins_default>; 289 clock-frequency = <400000>; 290}; 291 292&ecap0 { 293 pinctrl-names = "default"; 294 pinctrl-0 = <&ecap0_pins_default>; 295}; 296 297&main_spi0 { 298 pinctrl-names = "default"; 299 pinctrl-0 = <&main_spi0_pins_default>; 300 #address-cells = <1>; 301 #size-cells= <0>; 302 ti,pindir-d0-out-d1-in = <1>; 303 304 flash@0{ 305 compatible = "jedec,spi-nor"; 306 reg = <0x0>; 307 spi-tx-bus-width = <1>; 308 spi-rx-bus-width = <1>; 309 spi-max-frequency = <48000000>; 310 #address-cells = <1>; 311 #size-cells= <1>; 312 }; 313}; 314 315&sdhci0 { 316 pinctrl-names = "default"; 317 pinctrl-0 = <&main_mmc0_pins_default>; 318 bus-width = <8>; 319 non-removable; 320 ti,driver-strength-ohm = <50>; 321 disable-wp; 322}; 323 324/* 325 * Because of erratas i2025 and i2026 for silicon revision 1.0, the 326 * SD card interface might fail. Boards with sr1.0 are recommended to 327 * disable sdhci1 328 */ 329&sdhci1 { 330 pinctrl-names = "default"; 331 pinctrl-0 = <&main_mmc1_pins_default>; 332 ti,driver-strength-ohm = <50>; 333 disable-wp; 334}; 335 336&usb1 { 337 pinctrl-names = "default"; 338 pinctrl-0 = <&usb1_pins_default>; 339 dr_mode = "otg"; 340}; 341 342&dwc3_0 { 343 status = "disabled"; 344}; 345 346&usb0_phy { 347 status = "disabled"; 348}; 349 350&tscadc0 { 351 adc { 352 ti,adc-channels = <0 1 2 3 4 5 6 7>; 353 }; 354}; 355 356&tscadc1 { 357 adc { 358 ti,adc-channels = <0 1 2 3 4 5 6 7>; 359 }; 360}; 361 362&serdes0 { 363 status = "disabled"; 364}; 365 366&serdes1 { 367 status = "disabled"; 368}; 369 370&pcie0_rc { 371 status = "disabled"; 372}; 373 374&pcie0_ep { 375 status = "disabled"; 376}; 377 378&pcie1_rc { 379 status = "disabled"; 380}; 381 382&pcie1_ep { 383 status = "disabled"; 384}; 385 386&mailbox0_cluster0 { 387 interrupts = <436>; 388 389 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 390 ti,mbox-tx = <1 0 0>; 391 ti,mbox-rx = <0 0 0>; 392 }; 393}; 394 395&mailbox0_cluster1 { 396 interrupts = <432>; 397 398 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 399 ti,mbox-tx = <1 0 0>; 400 ti,mbox-rx = <0 0 0>; 401 }; 402}; 403 404&mailbox0_cluster2 { 405 status = "disabled"; 406}; 407 408&mailbox0_cluster3 { 409 status = "disabled"; 410}; 411 412&mailbox0_cluster4 { 413 status = "disabled"; 414}; 415 416&mailbox0_cluster5 { 417 status = "disabled"; 418}; 419 420&mailbox0_cluster6 { 421 status = "disabled"; 422}; 423 424&mailbox0_cluster7 { 425 status = "disabled"; 426}; 427 428&mailbox0_cluster8 { 429 status = "disabled"; 430}; 431 432&mailbox0_cluster9 { 433 status = "disabled"; 434}; 435 436&mailbox0_cluster10 { 437 status = "disabled"; 438}; 439 440&mailbox0_cluster11 { 441 status = "disabled"; 442}; 443 444&mcu_r5fss0_core0 { 445 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 446 <&mcu_r5fss0_core0_memory_region>; 447 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 448}; 449 450&mcu_r5fss0_core1 { 451 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 452 <&mcu_r5fss0_core1_memory_region>; 453 mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; 454}; 455 456&ospi0 { 457 pinctrl-names = "default"; 458 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; 459 460 flash@0{ 461 compatible = "jedec,spi-nor"; 462 reg = <0x0>; 463 spi-tx-bus-width = <8>; 464 spi-rx-bus-width = <8>; 465 spi-max-frequency = <25000000>; 466 cdns,tshsl-ns = <60>; 467 cdns,tsd2d-ns = <60>; 468 cdns,tchsh-ns = <60>; 469 cdns,tslch-ns = <60>; 470 cdns,read-delay = <0>; 471 #address-cells = <1>; 472 #size-cells = <1>; 473 }; 474}; 475 476&mcu_cpsw { 477 pinctrl-names = "default"; 478 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>; 479}; 480 481&davinci_mdio { 482 phy0: ethernet-phy@0 { 483 reg = <0>; 484 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 485 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 486 }; 487}; 488 489&cpsw_port1 { 490 phy-mode = "rgmii-rxid"; 491 phy-handle = <&phy0>; 492}; 493 494&mcasp0 { 495 status = "disabled"; 496}; 497 498&mcasp1 { 499 status = "disabled"; 500}; 501 502&mcasp2 { 503 status = "disabled"; 504}; 505 506&dss { 507 status = "disabled"; 508}; 509