1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM6 SoC Family MCU Domain peripherals 4 * 5 * Copyright (C) 2016-2020 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu { 9 mcu_conf: scm-conf@40f00000 { 10 compatible = "syscon", "simple-mfd"; 11 reg = <0x0 0x40f00000 0x0 0x20000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x0 0x40f00000 0x20000>; 15 16 phy_gmii_sel: phy@4040 { 17 compatible = "ti,am654-phy-gmii-sel"; 18 reg = <0x4040 0x4>; 19 #phy-cells = <1>; 20 }; 21 }; 22 23 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ 24 mcu_timerio_input: pinctrl@40f04200 { 25 compatible = "pinctrl-single"; 26 reg = <0x0 0x40f04200 0x0 0x10>; 27 #pinctrl-cells = <1>; 28 pinctrl-single,register-width = <32>; 29 pinctrl-single,function-mask = <0x00000101>; 30 }; 31 32 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ 33 mcu_timerio_output: pinctrl@40f04280 { 34 compatible = "pinctrl-single"; 35 reg = <0x0 0x40f04280 0x0 0x8>; 36 #pinctrl-cells = <1>; 37 pinctrl-single,register-width = <32>; 38 pinctrl-single,function-mask = <0x00000003>; 39 }; 40 41 mcu_uart0: serial@40a00000 { 42 compatible = "ti,am654-uart"; 43 reg = <0x00 0x40a00000 0x00 0x100>; 44 interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 45 clock-frequency = <96000000>; 46 current-speed = <115200>; 47 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 48 status = "disabled"; 49 }; 50 51 mcu_ram: sram@41c00000 { 52 compatible = "mmio-sram"; 53 reg = <0x00 0x41c00000 0x00 0x80000>; 54 ranges = <0x0 0x00 0x41c00000 0x80000>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 }; 58 59 mcu_i2c0: i2c@40b00000 { 60 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 61 reg = <0x0 0x40b00000 0x0 0x100>; 62 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>; 63 #address-cells = <1>; 64 #size-cells = <0>; 65 clock-names = "fck"; 66 clocks = <&k3_clks 114 1>; 67 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 68 status = "disabled"; 69 }; 70 71 mcu_spi0: spi@40300000 { 72 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 73 reg = <0x0 0x40300000 0x0 0x400>; 74 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>; 75 clocks = <&k3_clks 142 1>; 76 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 77 #address-cells = <1>; 78 #size-cells = <0>; 79 status = "disabled"; 80 }; 81 82 mcu_spi1: spi@40310000 { 83 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 84 reg = <0x0 0x40310000 0x0 0x400>; 85 interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 86 clocks = <&k3_clks 143 1>; 87 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 88 #address-cells = <1>; 89 #size-cells = <0>; 90 status = "disabled"; 91 }; 92 93 mcu_spi2: spi@40320000 { 94 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 95 reg = <0x0 0x40320000 0x0 0x400>; 96 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>; 97 clocks = <&k3_clks 144 1>; 98 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 99 #address-cells = <1>; 100 #size-cells = <0>; 101 status = "disabled"; 102 }; 103 104 tscadc0: tscadc@40200000 { 105 compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 106 reg = <0x0 0x40200000 0x0 0x1000>; 107 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 108 clocks = <&k3_clks 0 2>; 109 assigned-clocks = <&k3_clks 0 2>; 110 assigned-clock-rates = <60000000>; 111 clock-names = "fck"; 112 dmas = <&mcu_udmap 0x7100>, 113 <&mcu_udmap 0x7101 >; 114 dma-names = "fifo0", "fifo1"; 115 116 adc { 117 #io-channel-cells = <1>; 118 compatible = "ti,am654-adc", "ti,am3359-adc"; 119 }; 120 }; 121 122 tscadc1: tscadc@40210000 { 123 compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 124 reg = <0x0 0x40210000 0x0 0x1000>; 125 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 126 clocks = <&k3_clks 1 2>; 127 assigned-clocks = <&k3_clks 1 2>; 128 assigned-clock-rates = <60000000>; 129 clock-names = "fck"; 130 dmas = <&mcu_udmap 0x7102>, 131 <&mcu_udmap 0x7103>; 132 dma-names = "fifo0", "fifo1"; 133 134 adc { 135 #io-channel-cells = <1>; 136 compatible = "ti,am654-adc", "ti,am3359-adc"; 137 }; 138 }; 139 140 /* 141 * The MCU domain timer interrupts are routed only to the ESM module, 142 * and not currently available for Linux. The MCU domain timers are 143 * of limited use without interrupts, and likely reserved by the ESM. 144 */ 145 mcu_timer0: timer@40400000 { 146 compatible = "ti,am654-timer"; 147 reg = <0x00 0x40400000 0x00 0x400>; 148 clocks = <&k3_clks 35 0>; 149 clock-names = "fck"; 150 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 151 ti,timer-pwm; 152 status = "reserved"; 153 }; 154 155 mcu_timer1: timer@40410000 { 156 compatible = "ti,am654-timer"; 157 reg = <0x00 0x40410000 0x00 0x400>; 158 clocks = <&k3_clks 36 0>; 159 clock-names = "fck"; 160 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 161 ti,timer-pwm; 162 status = "reserved"; 163 }; 164 165 mcu_timer2: timer@40420000 { 166 compatible = "ti,am654-timer"; 167 reg = <0x00 0x40420000 0x00 0x400>; 168 clocks = <&k3_clks 37 0>; 169 clock-names = "fck"; 170 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 171 ti,timer-pwm; 172 status = "reserved"; 173 }; 174 175 mcu_timer3: timer@40430000 { 176 compatible = "ti,am654-timer"; 177 reg = <0x00 0x40430000 0x00 0x400>; 178 clocks = <&k3_clks 38 0>; 179 clock-names = "fck"; 180 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 181 ti,timer-pwm; 182 status = "reserved"; 183 }; 184 185 mcu_navss: bus@28380000 { 186 compatible = "simple-mfd"; 187 #address-cells = <2>; 188 #size-cells = <2>; 189 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 190 dma-coherent; 191 dma-ranges; 192 193 ti,sci-dev-id = <119>; 194 195 mcu_ringacc: ringacc@2b800000 { 196 compatible = "ti,am654-navss-ringacc"; 197 reg = <0x0 0x2b800000 0x0 0x400000>, 198 <0x0 0x2b000000 0x0 0x400000>, 199 <0x0 0x28590000 0x0 0x100>, 200 <0x0 0x2a500000 0x0 0x40000>; 201 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 202 ti,num-rings = <286>; 203 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 204 ti,sci = <&dmsc>; 205 ti,sci-dev-id = <195>; 206 msi-parent = <&inta_main_udmass>; 207 }; 208 209 mcu_udmap: dma-controller@285c0000 { 210 compatible = "ti,am654-navss-mcu-udmap"; 211 reg = <0x0 0x285c0000 0x0 0x100>, 212 <0x0 0x2a800000 0x0 0x40000>, 213 <0x0 0x2aa00000 0x0 0x40000>; 214 reg-names = "gcfg", "rchanrt", "tchanrt"; 215 msi-parent = <&inta_main_udmass>; 216 #dma-cells = <1>; 217 218 ti,sci = <&dmsc>; 219 ti,sci-dev-id = <194>; 220 ti,ringacc = <&mcu_ringacc>; 221 222 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */ 223 <0xd>; /* TX_CHAN */ 224 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */ 225 <0xa>; /* RX_CHAN */ 226 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */ 227 }; 228 }; 229 230 secure_proxy_mcu: mailbox@2a480000 { 231 compatible = "ti,am654-secure-proxy"; 232 #mbox-cells = <1>; 233 reg-names = "target_data", "rt", "scfg"; 234 reg = <0x0 0x2a480000 0x0 0x80000>, 235 <0x0 0x2a380000 0x0 0x80000>, 236 <0x0 0x2a400000 0x0 0x80000>; 237 /* 238 * Marked Disabled: 239 * Node is incomplete as it is meant for bootloaders and 240 * firmware on non-MPU processors 241 */ 242 status = "disabled"; 243 }; 244 245 m_can0: can@40528000 { 246 compatible = "bosch,m_can"; 247 reg = <0x0 0x40528000 0x0 0x400>, 248 <0x0 0x40500000 0x0 0x4400>; 249 reg-names = "m_can", "message_ram"; 250 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 251 clocks = <&k3_clks 102 5>, <&k3_clks 102 0>; 252 clock-names = "hclk", "cclk"; 253 interrupt-parent = <&gic500>; 254 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 255 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>; 256 interrupt-names = "int0", "int1"; 257 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 258 status = "disabled"; 259 }; 260 261 m_can1: can@40568000 { 262 compatible = "bosch,m_can"; 263 reg = <0x0 0x40568000 0x0 0x400>, 264 <0x0 0x40540000 0x0 0x4400>; 265 reg-names = "m_can", "message_ram"; 266 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 267 clocks = <&k3_clks 103 5>, <&k3_clks 103 0>; 268 clock-names = "hclk", "cclk"; 269 interrupt-parent = <&gic500>; 270 interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>; 272 interrupt-names = "int0", "int1"; 273 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 274 status = "disabled"; 275 }; 276 277 fss: fss@47000000 { 278 compatible = "simple-bus"; 279 #address-cells = <2>; 280 #size-cells = <2>; 281 ranges; 282 283 ospi0: spi@47040000 { 284 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 285 reg = <0x0 0x47040000 0x0 0x100>, 286 <0x5 0x00000000 0x1 0x0000000>; 287 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>; 288 cdns,fifo-depth = <256>; 289 cdns,fifo-width = <4>; 290 cdns,trigger-address = <0x0>; 291 clocks = <&k3_clks 248 0>; 292 assigned-clocks = <&k3_clks 248 0>; 293 assigned-clock-parents = <&k3_clks 248 2>; 294 assigned-clock-rates = <166666666>; 295 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; 296 #address-cells = <1>; 297 #size-cells = <0>; 298 }; 299 300 ospi1: spi@47050000 { 301 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 302 reg = <0x0 0x47050000 0x0 0x100>, 303 <0x7 0x00000000 0x1 0x00000000>; 304 interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 305 cdns,fifo-depth = <256>; 306 cdns,fifo-width = <4>; 307 cdns,trigger-address = <0x0>; 308 clocks = <&k3_clks 249 6>; 309 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 }; 313 }; 314 315 mcu_cpsw: ethernet@46000000 { 316 compatible = "ti,am654-cpsw-nuss"; 317 #address-cells = <2>; 318 #size-cells = <2>; 319 reg = <0x0 0x46000000 0x0 0x200000>; 320 reg-names = "cpsw_nuss"; 321 ranges = <0x0 0x0 0x0 0x46000000 0x0 0x200000>; 322 dma-coherent; 323 clocks = <&k3_clks 5 10>; 324 clock-names = "fck"; 325 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>; 326 327 dmas = <&mcu_udmap 0xf000>, 328 <&mcu_udmap 0xf001>, 329 <&mcu_udmap 0xf002>, 330 <&mcu_udmap 0xf003>, 331 <&mcu_udmap 0xf004>, 332 <&mcu_udmap 0xf005>, 333 <&mcu_udmap 0xf006>, 334 <&mcu_udmap 0xf007>, 335 <&mcu_udmap 0x7000>; 336 dma-names = "tx0", "tx1", "tx2", "tx3", 337 "tx4", "tx5", "tx6", "tx7", 338 "rx"; 339 340 ethernet-ports { 341 #address-cells = <1>; 342 #size-cells = <0>; 343 344 cpsw_port1: port@1 { 345 reg = <1>; 346 ti,mac-only; 347 label = "port1"; 348 ti,syscon-efuse = <&mcu_conf 0x200>; 349 phys = <&phy_gmii_sel 1>; 350 }; 351 }; 352 353 davinci_mdio: mdio@f00 { 354 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 355 reg = <0x0 0xf00 0x0 0x100>; 356 #address-cells = <1>; 357 #size-cells = <0>; 358 clocks = <&k3_clks 5 10>; 359 clock-names = "fck"; 360 bus_freq = <1000000>; 361 status = "disabled"; 362 }; 363 364 cpts@3d000 { 365 compatible = "ti,am65-cpts"; 366 reg = <0x0 0x3d000 0x0 0x400>; 367 clocks = <&mcu_cpsw_cpts_mux>; 368 clock-names = "cpts"; 369 interrupts-extended = <&gic500 GIC_SPI 570 IRQ_TYPE_LEVEL_HIGH>; 370 interrupt-names = "cpts"; 371 ti,cpts-ext-ts-inputs = <4>; 372 ti,cpts-periodic-outputs = <2>; 373 374 mcu_cpsw_cpts_mux: refclk-mux { 375 #clock-cells = <0>; 376 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, 377 <&k3_clks 118 6>, <&k3_clks 118 3>, 378 <&k3_clks 118 8>, <&k3_clks 118 14>, 379 <&k3_clks 120 3>, <&k3_clks 121 3>; 380 assigned-clocks = <&mcu_cpsw_cpts_mux>; 381 assigned-clock-parents = <&k3_clks 118 5>; 382 }; 383 }; 384 }; 385 386 mcu_r5fss0: r5fss@41000000 { 387 compatible = "ti,am654-r5fss"; 388 ti,cluster-mode = <1>; 389 #address-cells = <1>; 390 #size-cells = <1>; 391 ranges = <0x41000000 0x00 0x41000000 0x20000>, 392 <0x41400000 0x00 0x41400000 0x20000>; 393 power-domains = <&k3_pds 129 TI_SCI_PD_EXCLUSIVE>; 394 395 mcu_r5fss0_core0: r5f@41000000 { 396 compatible = "ti,am654-r5f"; 397 reg = <0x41000000 0x00008000>, 398 <0x41010000 0x00008000>; 399 reg-names = "atcm", "btcm"; 400 ti,sci = <&dmsc>; 401 ti,sci-dev-id = <159>; 402 ti,sci-proc-ids = <0x01 0xff>; 403 resets = <&k3_reset 159 1>; 404 firmware-name = "am65x-mcu-r5f0_0-fw"; 405 ti,atcm-enable = <1>; 406 ti,btcm-enable = <1>; 407 ti,loczrama = <1>; 408 }; 409 410 mcu_r5fss0_core1: r5f@41400000 { 411 compatible = "ti,am654-r5f"; 412 reg = <0x41400000 0x00008000>, 413 <0x41410000 0x00008000>; 414 reg-names = "atcm", "btcm"; 415 ti,sci = <&dmsc>; 416 ti,sci-dev-id = <245>; 417 ti,sci-proc-ids = <0x02 0xff>; 418 resets = <&k3_reset 245 1>; 419 firmware-name = "am65x-mcu-r5f0_1-fw"; 420 ti,atcm-enable = <1>; 421 ti,btcm-enable = <1>; 422 ti,loczrama = <1>; 423 }; 424 }; 425 426 mcu_rti1: watchdog@40610000 { 427 compatible = "ti,j7-rti-wdt"; 428 reg = <0x0 0x40610000 0x0 0x100>; 429 clocks = <&k3_clks 135 0>; 430 power-domains = <&k3_pds 135 TI_SCI_PD_SHARED>; 431 assigned-clocks = <&k3_clks 135 0>; 432 assigned-clock-parents = <&k3_clks 135 4>; 433 }; 434}; 435