1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM6 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy-am654-serdes.h> 8 9&cbass_main { 10 msmc_ram: sram@70000000 { 11 compatible = "mmio-sram"; 12 reg = <0x0 0x70000000 0x0 0x200000>; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 ranges = <0x0 0x0 0x70000000 0x200000>; 16 17 atf-sram@0 { 18 reg = <0x0 0x20000>; 19 }; 20 21 sysfw-sram@f0000 { 22 reg = <0xf0000 0x10000>; 23 }; 24 25 l3cache-sram@100000 { 26 reg = <0x100000 0x100000>; 27 }; 28 }; 29 30 gic500: interrupt-controller@1800000 { 31 compatible = "arm,gic-v3"; 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 #interrupt-cells = <3>; 36 interrupt-controller; 37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 38 <0x00 0x01880000 0x00 0x90000>; /* GICR */ 39 /* 40 * vcpumntirq: 41 * virtual CPU interface maintenance interrupt 42 */ 43 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 44 45 gic_its: msi-controller@1820000 { 46 compatible = "arm,gic-v3-its"; 47 reg = <0x00 0x01820000 0x00 0x10000>; 48 socionext,synquacer-pre-its = <0x1000000 0x400000>; 49 msi-controller; 50 #msi-cells = <1>; 51 }; 52 }; 53 54 serdes0: serdes@900000 { 55 compatible = "ti,phy-am654-serdes"; 56 reg = <0x0 0x900000 0x0 0x2000>; 57 reg-names = "serdes"; 58 #phy-cells = <2>; 59 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 60 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>; 61 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk"; 62 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; 63 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; 64 ti,serdes-clk = <&serdes0_clk>; 65 #clock-cells = <1>; 66 mux-controls = <&serdes_mux 0>; 67 }; 68 69 serdes1: serdes@910000 { 70 compatible = "ti,phy-am654-serdes"; 71 reg = <0x0 0x910000 0x0 0x2000>; 72 reg-names = "serdes"; 73 #phy-cells = <2>; 74 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 75 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>; 76 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk"; 77 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>; 78 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>; 79 ti,serdes-clk = <&serdes1_clk>; 80 #clock-cells = <1>; 81 mux-controls = <&serdes_mux 1>; 82 }; 83 84 main_uart0: serial@2800000 { 85 compatible = "ti,am654-uart"; 86 reg = <0x00 0x02800000 0x00 0x100>; 87 reg-shift = <2>; 88 reg-io-width = <4>; 89 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 90 clock-frequency = <48000000>; 91 current-speed = <115200>; 92 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 93 }; 94 95 main_uart1: serial@2810000 { 96 compatible = "ti,am654-uart"; 97 reg = <0x00 0x02810000 0x00 0x100>; 98 reg-shift = <2>; 99 reg-io-width = <4>; 100 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 101 clock-frequency = <48000000>; 102 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 103 }; 104 105 main_uart2: serial@2820000 { 106 compatible = "ti,am654-uart"; 107 reg = <0x00 0x02820000 0x00 0x100>; 108 reg-shift = <2>; 109 reg-io-width = <4>; 110 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 111 clock-frequency = <48000000>; 112 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 113 }; 114 115 crypto: crypto@4e00000 { 116 compatible = "ti,am654-sa2ul"; 117 reg = <0x0 0x4e00000 0x0 0x1200>; 118 power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>; 119 #address-cells = <2>; 120 #size-cells = <2>; 121 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 122 123 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 124 <&main_udmap 0x4001>; 125 dma-names = "tx", "rx1", "rx2"; 126 dma-coherent; 127 128 rng: rng@4e10000 { 129 compatible = "inside-secure,safexcel-eip76"; 130 reg = <0x0 0x4e10000 0x0 0x7d>; 131 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 132 clocks = <&k3_clks 136 1>; 133 }; 134 }; 135 136 main_pmx0: pinctrl@11c000 { 137 compatible = "pinctrl-single"; 138 reg = <0x0 0x11c000 0x0 0x2e4>; 139 #pinctrl-cells = <1>; 140 pinctrl-single,register-width = <32>; 141 pinctrl-single,function-mask = <0xffffffff>; 142 }; 143 144 main_pmx1: pinctrl@11c2e8 { 145 compatible = "pinctrl-single"; 146 reg = <0x0 0x11c2e8 0x0 0x24>; 147 #pinctrl-cells = <1>; 148 pinctrl-single,register-width = <32>; 149 pinctrl-single,function-mask = <0xffffffff>; 150 }; 151 152 main_i2c0: i2c@2000000 { 153 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 154 reg = <0x0 0x2000000 0x0 0x100>; 155 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 156 #address-cells = <1>; 157 #size-cells = <0>; 158 clock-names = "fck"; 159 clocks = <&k3_clks 110 1>; 160 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 161 }; 162 163 main_i2c1: i2c@2010000 { 164 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 165 reg = <0x0 0x2010000 0x0 0x100>; 166 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 167 #address-cells = <1>; 168 #size-cells = <0>; 169 clock-names = "fck"; 170 clocks = <&k3_clks 111 1>; 171 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 172 }; 173 174 main_i2c2: i2c@2020000 { 175 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 176 reg = <0x0 0x2020000 0x0 0x100>; 177 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 clock-names = "fck"; 181 clocks = <&k3_clks 112 1>; 182 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 183 }; 184 185 main_i2c3: i2c@2030000 { 186 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 187 reg = <0x0 0x2030000 0x0 0x100>; 188 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 189 #address-cells = <1>; 190 #size-cells = <0>; 191 clock-names = "fck"; 192 clocks = <&k3_clks 113 1>; 193 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 194 }; 195 196 ecap0: pwm@3100000 { 197 compatible = "ti,am654-ecap", "ti,am3352-ecap"; 198 #pwm-cells = <3>; 199 reg = <0x0 0x03100000 0x0 0x60>; 200 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 201 clocks = <&k3_clks 39 0>; 202 clock-names = "fck"; 203 }; 204 205 main_spi0: spi@2100000 { 206 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 207 reg = <0x0 0x2100000 0x0 0x400>; 208 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 209 clocks = <&k3_clks 137 1>; 210 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; 211 #address-cells = <1>; 212 #size-cells = <0>; 213 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 214 dma-names = "tx0", "rx0"; 215 }; 216 217 main_spi1: spi@2110000 { 218 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 219 reg = <0x0 0x2110000 0x0 0x400>; 220 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&k3_clks 138 1>; 222 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 assigned-clocks = <&k3_clks 137 1>; 226 assigned-clock-rates = <48000000>; 227 }; 228 229 main_spi2: spi@2120000 { 230 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 231 reg = <0x0 0x2120000 0x0 0x400>; 232 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 233 clocks = <&k3_clks 139 1>; 234 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>; 235 #address-cells = <1>; 236 #size-cells = <0>; 237 }; 238 239 main_spi3: spi@2130000 { 240 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 241 reg = <0x0 0x2130000 0x0 0x400>; 242 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&k3_clks 140 1>; 244 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 }; 248 249 main_spi4: spi@2140000 { 250 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 251 reg = <0x0 0x2140000 0x0 0x400>; 252 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&k3_clks 141 1>; 254 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 }; 258 259 sdhci0: mmc@4f80000 { 260 compatible = "ti,am654-sdhci-5.1"; 261 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; 262 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; 263 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>; 264 clock-names = "clk_ahb", "clk_xin"; 265 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 266 mmc-ddr-1_8v; 267 mmc-hs200-1_8v; 268 ti,otap-del-sel-legacy = <0x0>; 269 ti,otap-del-sel-mmc-hs = <0x0>; 270 ti,otap-del-sel-sd-hs = <0x0>; 271 ti,otap-del-sel-sdr12 = <0x0>; 272 ti,otap-del-sel-sdr25 = <0x0>; 273 ti,otap-del-sel-sdr50 = <0x8>; 274 ti,otap-del-sel-sdr104 = <0x7>; 275 ti,otap-del-sel-ddr50 = <0x5>; 276 ti,otap-del-sel-ddr52 = <0x5>; 277 ti,otap-del-sel-hs200 = <0x5>; 278 ti,otap-del-sel-hs400 = <0x0>; 279 ti,trm-icp = <0x8>; 280 dma-coherent; 281 }; 282 283 sdhci1: mmc@4fa0000 { 284 compatible = "ti,am654-sdhci-5.1"; 285 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>; 286 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; 287 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>; 288 clock-names = "clk_ahb", "clk_xin"; 289 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 290 ti,otap-del-sel-legacy = <0x0>; 291 ti,otap-del-sel-mmc-hs = <0x0>; 292 ti,otap-del-sel-sd-hs = <0x0>; 293 ti,otap-del-sel-sdr12 = <0x0>; 294 ti,otap-del-sel-sdr25 = <0x0>; 295 ti,otap-del-sel-sdr50 = <0x8>; 296 ti,otap-del-sel-sdr104 = <0x7>; 297 ti,otap-del-sel-ddr50 = <0x4>; 298 ti,otap-del-sel-ddr52 = <0x4>; 299 ti,otap-del-sel-hs200 = <0x7>; 300 ti,clkbuf-sel = <0x7>; 301 ti,otap-del-sel = <0x2>; 302 ti,trm-icp = <0x8>; 303 dma-coherent; 304 no-1-8-v; 305 }; 306 307 scm_conf: scm-conf@100000 { 308 compatible = "syscon", "simple-mfd"; 309 reg = <0 0x00100000 0 0x1c000>; 310 #address-cells = <1>; 311 #size-cells = <1>; 312 ranges = <0x0 0x0 0x00100000 0x1c000>; 313 314 pcie0_mode: pcie-mode@4060 { 315 compatible = "syscon"; 316 reg = <0x00004060 0x4>; 317 }; 318 319 pcie1_mode: pcie-mode@4070 { 320 compatible = "syscon"; 321 reg = <0x00004070 0x4>; 322 }; 323 324 pcie_devid: pcie-devid@210 { 325 compatible = "syscon"; 326 reg = <0x00000210 0x4>; 327 }; 328 329 serdes0_clk: clock@4080 { 330 compatible = "syscon"; 331 reg = <0x00004080 0x4>; 332 }; 333 334 serdes1_clk: clock@4090 { 335 compatible = "syscon"; 336 reg = <0x00004090 0x4>; 337 }; 338 339 serdes_mux: mux-controller { 340 compatible = "mmio-mux"; 341 #mux-control-cells = <1>; 342 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */ 343 <0x4090 0x3>; /* SERDES1 lane select */ 344 }; 345 346 dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 { 347 compatible = "syscon"; 348 reg = <0x0000041e0 0x14>; 349 }; 350 351 ehrpwm_tbclk: clock@4140 { 352 compatible = "ti,am654-ehrpwm-tbclk", "syscon"; 353 reg = <0x4140 0x18>; 354 #clock-cells = <1>; 355 }; 356 }; 357 358 dwc3_0: dwc3@4000000 { 359 compatible = "ti,am654-dwc3"; 360 reg = <0x0 0x4000000 0x0 0x4000>; 361 #address-cells = <1>; 362 #size-cells = <1>; 363 ranges = <0x0 0x0 0x4000000 0x20000>; 364 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 365 dma-coherent; 366 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; 367 clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 368 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 369 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 370 <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ 371 372 usb0: usb@10000 { 373 compatible = "snps,dwc3"; 374 reg = <0x10000 0x10000>; 375 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 378 interrupt-names = "peripheral", 379 "host", 380 "otg"; 381 maximum-speed = "high-speed"; 382 dr_mode = "otg"; 383 phys = <&usb0_phy>; 384 phy-names = "usb2-phy"; 385 snps,dis_u3_susphy_quirk; 386 }; 387 }; 388 389 usb0_phy: phy@4100000 { 390 compatible = "ti,am654-usb2", "ti,omap-usb2"; 391 reg = <0x0 0x4100000 0x0 0x54>; 392 syscon-phy-power = <&scm_conf 0x4000>; 393 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>; 394 clock-names = "wkupclk", "refclk"; 395 #phy-cells = <0>; 396 }; 397 398 dwc3_1: dwc3@4020000 { 399 compatible = "ti,am654-dwc3"; 400 reg = <0x0 0x4020000 0x0 0x4000>; 401 #address-cells = <1>; 402 #size-cells = <1>; 403 ranges = <0x0 0x0 0x4020000 0x20000>; 404 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 405 dma-coherent; 406 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 407 clocks = <&k3_clks 152 2>; 408 assigned-clocks = <&k3_clks 152 2>; 409 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 410 411 usb1: usb@10000 { 412 compatible = "snps,dwc3"; 413 reg = <0x10000 0x10000>; 414 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 417 interrupt-names = "peripheral", 418 "host", 419 "otg"; 420 maximum-speed = "high-speed"; 421 dr_mode = "otg"; 422 phys = <&usb1_phy>; 423 phy-names = "usb2-phy"; 424 }; 425 }; 426 427 usb1_phy: phy@4110000 { 428 compatible = "ti,am654-usb2", "ti,omap-usb2"; 429 reg = <0x0 0x4110000 0x0 0x54>; 430 syscon-phy-power = <&scm_conf 0x4020>; 431 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>; 432 clock-names = "wkupclk", "refclk"; 433 #phy-cells = <0>; 434 }; 435 436 intr_main_gpio: interrupt-controller@a00000 { 437 compatible = "ti,sci-intr"; 438 reg = <0x0 0x00a00000 0x0 0x400>; 439 ti,intr-trigger-type = <1>; 440 interrupt-controller; 441 interrupt-parent = <&gic500>; 442 #interrupt-cells = <1>; 443 ti,sci = <&dmsc>; 444 ti,sci-dev-id = <100>; 445 ti,interrupt-ranges = <0 392 32>; 446 }; 447 448 main_navss: bus@30800000 { 449 compatible = "simple-mfd"; 450 #address-cells = <2>; 451 #size-cells = <2>; 452 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>; 453 dma-coherent; 454 dma-ranges; 455 456 ti,sci-dev-id = <118>; 457 458 intr_main_navss: interrupt-controller@310e0000 { 459 compatible = "ti,sci-intr"; 460 reg = <0x0 0x310e0000 0x0 0x2000>; 461 ti,intr-trigger-type = <4>; 462 interrupt-controller; 463 interrupt-parent = <&gic500>; 464 #interrupt-cells = <1>; 465 ti,sci = <&dmsc>; 466 ti,sci-dev-id = <182>; 467 ti,interrupt-ranges = <0 64 64>, 468 <64 448 64>; 469 }; 470 471 inta_main_udmass: interrupt-controller@33d00000 { 472 compatible = "ti,sci-inta"; 473 reg = <0x0 0x33d00000 0x0 0x100000>; 474 interrupt-controller; 475 interrupt-parent = <&intr_main_navss>; 476 msi-controller; 477 #interrupt-cells = <0>; 478 ti,sci = <&dmsc>; 479 ti,sci-dev-id = <179>; 480 ti,interrupt-ranges = <0 0 256>; 481 }; 482 483 secure_proxy_main: mailbox@32c00000 { 484 compatible = "ti,am654-secure-proxy"; 485 #mbox-cells = <1>; 486 reg-names = "target_data", "rt", "scfg"; 487 reg = <0x00 0x32c00000 0x00 0x100000>, 488 <0x00 0x32400000 0x00 0x100000>, 489 <0x00 0x32800000 0x00 0x100000>; 490 interrupt-names = "rx_011"; 491 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 492 }; 493 494 hwspinlock: spinlock@30e00000 { 495 compatible = "ti,am654-hwspinlock"; 496 reg = <0x00 0x30e00000 0x00 0x1000>; 497 #hwlock-cells = <1>; 498 }; 499 500 mailbox0_cluster0: mailbox@31f80000 { 501 compatible = "ti,am654-mailbox"; 502 reg = <0x00 0x31f80000 0x00 0x200>; 503 #mbox-cells = <1>; 504 ti,mbox-num-users = <4>; 505 ti,mbox-num-fifos = <16>; 506 interrupt-parent = <&intr_main_navss>; 507 }; 508 509 mailbox0_cluster1: mailbox@31f81000 { 510 compatible = "ti,am654-mailbox"; 511 reg = <0x00 0x31f81000 0x00 0x200>; 512 #mbox-cells = <1>; 513 ti,mbox-num-users = <4>; 514 ti,mbox-num-fifos = <16>; 515 interrupt-parent = <&intr_main_navss>; 516 }; 517 518 mailbox0_cluster2: mailbox@31f82000 { 519 compatible = "ti,am654-mailbox"; 520 reg = <0x00 0x31f82000 0x00 0x200>; 521 #mbox-cells = <1>; 522 ti,mbox-num-users = <4>; 523 ti,mbox-num-fifos = <16>; 524 interrupt-parent = <&intr_main_navss>; 525 }; 526 527 mailbox0_cluster3: mailbox@31f83000 { 528 compatible = "ti,am654-mailbox"; 529 reg = <0x00 0x31f83000 0x00 0x200>; 530 #mbox-cells = <1>; 531 ti,mbox-num-users = <4>; 532 ti,mbox-num-fifos = <16>; 533 interrupt-parent = <&intr_main_navss>; 534 }; 535 536 mailbox0_cluster4: mailbox@31f84000 { 537 compatible = "ti,am654-mailbox"; 538 reg = <0x00 0x31f84000 0x00 0x200>; 539 #mbox-cells = <1>; 540 ti,mbox-num-users = <4>; 541 ti,mbox-num-fifos = <16>; 542 interrupt-parent = <&intr_main_navss>; 543 }; 544 545 mailbox0_cluster5: mailbox@31f85000 { 546 compatible = "ti,am654-mailbox"; 547 reg = <0x00 0x31f85000 0x00 0x200>; 548 #mbox-cells = <1>; 549 ti,mbox-num-users = <4>; 550 ti,mbox-num-fifos = <16>; 551 interrupt-parent = <&intr_main_navss>; 552 }; 553 554 mailbox0_cluster6: mailbox@31f86000 { 555 compatible = "ti,am654-mailbox"; 556 reg = <0x00 0x31f86000 0x00 0x200>; 557 #mbox-cells = <1>; 558 ti,mbox-num-users = <4>; 559 ti,mbox-num-fifos = <16>; 560 interrupt-parent = <&intr_main_navss>; 561 }; 562 563 mailbox0_cluster7: mailbox@31f87000 { 564 compatible = "ti,am654-mailbox"; 565 reg = <0x00 0x31f87000 0x00 0x200>; 566 #mbox-cells = <1>; 567 ti,mbox-num-users = <4>; 568 ti,mbox-num-fifos = <16>; 569 interrupt-parent = <&intr_main_navss>; 570 }; 571 572 mailbox0_cluster8: mailbox@31f88000 { 573 compatible = "ti,am654-mailbox"; 574 reg = <0x00 0x31f88000 0x00 0x200>; 575 #mbox-cells = <1>; 576 ti,mbox-num-users = <4>; 577 ti,mbox-num-fifos = <16>; 578 interrupt-parent = <&intr_main_navss>; 579 }; 580 581 mailbox0_cluster9: mailbox@31f89000 { 582 compatible = "ti,am654-mailbox"; 583 reg = <0x00 0x31f89000 0x00 0x200>; 584 #mbox-cells = <1>; 585 ti,mbox-num-users = <4>; 586 ti,mbox-num-fifos = <16>; 587 interrupt-parent = <&intr_main_navss>; 588 }; 589 590 mailbox0_cluster10: mailbox@31f8a000 { 591 compatible = "ti,am654-mailbox"; 592 reg = <0x00 0x31f8a000 0x00 0x200>; 593 #mbox-cells = <1>; 594 ti,mbox-num-users = <4>; 595 ti,mbox-num-fifos = <16>; 596 interrupt-parent = <&intr_main_navss>; 597 }; 598 599 mailbox0_cluster11: mailbox@31f8b000 { 600 compatible = "ti,am654-mailbox"; 601 reg = <0x00 0x31f8b000 0x00 0x200>; 602 #mbox-cells = <1>; 603 ti,mbox-num-users = <4>; 604 ti,mbox-num-fifos = <16>; 605 interrupt-parent = <&intr_main_navss>; 606 }; 607 608 ringacc: ringacc@3c000000 { 609 compatible = "ti,am654-navss-ringacc"; 610 reg = <0x0 0x3c000000 0x0 0x400000>, 611 <0x0 0x38000000 0x0 0x400000>, 612 <0x0 0x31120000 0x0 0x100>, 613 <0x0 0x33000000 0x0 0x40000>; 614 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 615 ti,num-rings = <818>; 616 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 617 ti,sci = <&dmsc>; 618 ti,sci-dev-id = <187>; 619 msi-parent = <&inta_main_udmass>; 620 }; 621 622 main_udmap: dma-controller@31150000 { 623 compatible = "ti,am654-navss-main-udmap"; 624 reg = <0x0 0x31150000 0x0 0x100>, 625 <0x0 0x34000000 0x0 0x100000>, 626 <0x0 0x35000000 0x0 0x100000>; 627 reg-names = "gcfg", "rchanrt", "tchanrt"; 628 msi-parent = <&inta_main_udmass>; 629 #dma-cells = <1>; 630 631 ti,sci = <&dmsc>; 632 ti,sci-dev-id = <188>; 633 ti,ringacc = <&ringacc>; 634 635 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */ 636 <0xd>; /* TX_CHAN */ 637 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */ 638 <0xa>; /* RX_CHAN */ 639 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */ 640 }; 641 642 cpts@310d0000 { 643 compatible = "ti,am65-cpts"; 644 reg = <0x0 0x310d0000 0x0 0x400>; 645 reg-names = "cpts"; 646 clocks = <&main_cpts_mux>; 647 clock-names = "cpts"; 648 interrupts-extended = <&intr_main_navss 391>; 649 interrupt-names = "cpts"; 650 ti,cpts-periodic-outputs = <6>; 651 ti,cpts-ext-ts-inputs = <8>; 652 653 main_cpts_mux: refclk-mux { 654 #clock-cells = <0>; 655 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, 656 <&k3_clks 118 6>, <&k3_clks 118 3>, 657 <&k3_clks 118 8>, <&k3_clks 118 14>, 658 <&k3_clks 120 3>, <&k3_clks 121 3>; 659 assigned-clocks = <&main_cpts_mux>; 660 assigned-clock-parents = <&k3_clks 118 5>; 661 }; 662 }; 663 }; 664 665 main_gpio0: gpio@600000 { 666 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 667 reg = <0x0 0x600000 0x0 0x100>; 668 gpio-controller; 669 #gpio-cells = <2>; 670 interrupt-parent = <&intr_main_gpio>; 671 interrupts = <192>, <193>, <194>, <195>, <196>, <197>; 672 interrupt-controller; 673 #interrupt-cells = <2>; 674 ti,ngpio = <96>; 675 ti,davinci-gpio-unbanked = <0>; 676 clocks = <&k3_clks 57 0>; 677 clock-names = "gpio"; 678 }; 679 680 main_gpio1: gpio@601000 { 681 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 682 reg = <0x0 0x601000 0x0 0x100>; 683 gpio-controller; 684 #gpio-cells = <2>; 685 interrupt-parent = <&intr_main_gpio>; 686 interrupts = <200>, <201>, <202>, <203>, <204>, <205>; 687 interrupt-controller; 688 #interrupt-cells = <2>; 689 ti,ngpio = <90>; 690 ti,davinci-gpio-unbanked = <0>; 691 clocks = <&k3_clks 58 0>; 692 clock-names = "gpio"; 693 }; 694 695 pcie0_rc: pcie@5500000 { 696 compatible = "ti,am654-pcie-rc"; 697 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; 698 reg-names = "app", "dbics", "config", "atu"; 699 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 700 #address-cells = <3>; 701 #size-cells = <2>; 702 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000 703 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; 704 ti,syscon-pcie-id = <&pcie_devid>; 705 ti,syscon-pcie-mode = <&pcie0_mode>; 706 bus-range = <0x0 0xff>; 707 num-viewport = <16>; 708 max-link-speed = <2>; 709 dma-coherent; 710 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 711 msi-map = <0x0 &gic_its 0x0 0x10000>; 712 device_type = "pci"; 713 }; 714 715 pcie0_ep: pcie-ep@5500000 { 716 compatible = "ti,am654-pcie-ep"; 717 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; 718 reg-names = "app", "dbics", "addr_space", "atu"; 719 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 720 ti,syscon-pcie-mode = <&pcie0_mode>; 721 num-ib-windows = <16>; 722 num-ob-windows = <16>; 723 max-link-speed = <2>; 724 dma-coherent; 725 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 726 }; 727 728 pcie1_rc: pcie@5600000 { 729 compatible = "ti,am654-pcie-rc"; 730 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; 731 reg-names = "app", "dbics", "config", "atu"; 732 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 733 #address-cells = <3>; 734 #size-cells = <2>; 735 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000 736 0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>; 737 ti,syscon-pcie-id = <&pcie_devid>; 738 ti,syscon-pcie-mode = <&pcie1_mode>; 739 bus-range = <0x0 0xff>; 740 num-viewport = <16>; 741 max-link-speed = <2>; 742 dma-coherent; 743 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 744 msi-map = <0x0 &gic_its 0x10000 0x10000>; 745 device_type = "pci"; 746 }; 747 748 pcie1_ep: pcie-ep@5600000 { 749 compatible = "ti,am654-pcie-ep"; 750 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; 751 reg-names = "app", "dbics", "addr_space", "atu"; 752 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 753 ti,syscon-pcie-mode = <&pcie1_mode>; 754 num-ib-windows = <16>; 755 num-ob-windows = <16>; 756 max-link-speed = <2>; 757 dma-coherent; 758 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 759 }; 760 761 mcasp0: mcasp@2b00000 { 762 compatible = "ti,am33xx-mcasp-audio"; 763 reg = <0x0 0x02b00000 0x0 0x2000>, 764 <0x0 0x02b08000 0x0 0x1000>; 765 reg-names = "mpu","dat"; 766 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 768 interrupt-names = "tx", "rx"; 769 770 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 771 dma-names = "tx", "rx"; 772 773 clocks = <&k3_clks 104 0>; 774 clock-names = "fck"; 775 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 776 }; 777 778 mcasp1: mcasp@2b10000 { 779 compatible = "ti,am33xx-mcasp-audio"; 780 reg = <0x0 0x02b10000 0x0 0x2000>, 781 <0x0 0x02b18000 0x0 0x1000>; 782 reg-names = "mpu","dat"; 783 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 785 interrupt-names = "tx", "rx"; 786 787 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 788 dma-names = "tx", "rx"; 789 790 clocks = <&k3_clks 105 0>; 791 clock-names = "fck"; 792 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 793 }; 794 795 mcasp2: mcasp@2b20000 { 796 compatible = "ti,am33xx-mcasp-audio"; 797 reg = <0x0 0x02b20000 0x0 0x2000>, 798 <0x0 0x02b28000 0x0 0x1000>; 799 reg-names = "mpu","dat"; 800 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 802 interrupt-names = "tx", "rx"; 803 804 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 805 dma-names = "tx", "rx"; 806 807 clocks = <&k3_clks 106 0>; 808 clock-names = "fck"; 809 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 810 }; 811 812 cal: cal@6f03000 { 813 compatible = "ti,am654-cal"; 814 reg = <0x0 0x06f03000 0x0 0x400>, 815 <0x0 0x06f03800 0x0 0x40>; 816 reg-names = "cal_top", 817 "cal_rx_core0"; 818 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 819 ti,camerrx-control = <&scm_conf 0x40c0>; 820 clock-names = "fck"; 821 clocks = <&k3_clks 2 0>; 822 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>; 823 824 ports { 825 #address-cells = <1>; 826 #size-cells = <0>; 827 828 csi2_0: port@0 { 829 reg = <0>; 830 }; 831 }; 832 }; 833 834 dss: dss@4a00000 { 835 compatible = "ti,am65x-dss"; 836 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ 837 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ 838 <0x0 0x04a06000 0x0 0x1000>, /* vid */ 839 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ 840 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ 841 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ 842 <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ 843 reg-names = "common", "vidl1", "vid", 844 "ovr1", "ovr2", "vp1", "vp2"; 845 846 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; 847 848 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 849 850 clocks = <&k3_clks 67 1>, 851 <&k3_clks 216 1>, 852 <&k3_clks 67 2>; 853 clock-names = "fck", "vp1", "vp2"; 854 855 /* 856 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via 857 * DIV1. See "Figure 12-3365. DSS Integration" 858 * in AM65x TRM for details. 859 */ 860 assigned-clocks = <&k3_clks 67 2>; 861 assigned-clock-parents = <&k3_clks 67 5>; 862 863 interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>; 864 865 dma-coherent; 866 867 dss_ports: ports { 868 #address-cells = <1>; 869 #size-cells = <0>; 870 }; 871 }; 872 873 ehrpwm0: pwm@3000000 { 874 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 875 #pwm-cells = <3>; 876 reg = <0x0 0x3000000 0x0 0x100>; 877 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 878 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>; 879 clock-names = "tbclk", "fck"; 880 }; 881 882 ehrpwm1: pwm@3010000 { 883 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 884 #pwm-cells = <3>; 885 reg = <0x0 0x3010000 0x0 0x100>; 886 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 887 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>; 888 clock-names = "tbclk", "fck"; 889 }; 890 891 ehrpwm2: pwm@3020000 { 892 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 893 #pwm-cells = <3>; 894 reg = <0x0 0x3020000 0x0 0x100>; 895 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 896 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>; 897 clock-names = "tbclk", "fck"; 898 }; 899 900 ehrpwm3: pwm@3030000 { 901 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 902 #pwm-cells = <3>; 903 reg = <0x0 0x3030000 0x0 0x100>; 904 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 905 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>; 906 clock-names = "tbclk", "fck"; 907 }; 908 909 ehrpwm4: pwm@3040000 { 910 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 911 #pwm-cells = <3>; 912 reg = <0x0 0x3040000 0x0 0x100>; 913 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; 914 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>; 915 clock-names = "tbclk", "fck"; 916 }; 917 918 ehrpwm5: pwm@3050000 { 919 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 920 #pwm-cells = <3>; 921 reg = <0x0 0x3050000 0x0 0x100>; 922 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; 923 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>; 924 clock-names = "tbclk", "fck"; 925 }; 926 927 icssg0: icssg@b000000 { 928 compatible = "ti,am654-icssg"; 929 reg = <0x00 0xb000000 0x00 0x80000>; 930 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 931 #address-cells = <1>; 932 #size-cells = <1>; 933 ranges = <0x0 0x00 0xb000000 0x80000>; 934 935 icssg0_mem: memories@0 { 936 reg = <0x0 0x2000>, 937 <0x2000 0x2000>, 938 <0x10000 0x10000>; 939 reg-names = "dram0", "dram1", 940 "shrdram2"; 941 }; 942 943 icssg0_cfg: cfg@26000 { 944 compatible = "ti,pruss-cfg", "syscon"; 945 reg = <0x26000 0x200>; 946 #address-cells = <1>; 947 #size-cells = <1>; 948 ranges = <0x0 0x26000 0x2000>; 949 950 clocks { 951 #address-cells = <1>; 952 #size-cells = <0>; 953 954 icssg0_coreclk_mux: coreclk-mux@3c { 955 reg = <0x3c>; 956 #clock-cells = <0>; 957 clocks = <&k3_clks 62 19>, /* icssg0_core_clk */ 958 <&k3_clks 62 3>; /* icssg0_iclk */ 959 assigned-clocks = <&icssg0_coreclk_mux>; 960 assigned-clock-parents = <&k3_clks 62 3>; 961 }; 962 963 icssg0_iepclk_mux: iepclk-mux@30 { 964 reg = <0x30>; 965 #clock-cells = <0>; 966 clocks = <&k3_clks 62 10>, /* icssg0_iep_clk */ 967 <&icssg0_coreclk_mux>; /* core_clk */ 968 assigned-clocks = <&icssg0_iepclk_mux>; 969 assigned-clock-parents = <&icssg0_coreclk_mux>; 970 }; 971 }; 972 }; 973 974 icssg0_mii_rt: mii-rt@32000 { 975 compatible = "ti,pruss-mii", "syscon"; 976 reg = <0x32000 0x100>; 977 }; 978 979 icssg0_mii_g_rt: mii-g-rt@33000 { 980 compatible = "ti,pruss-mii-g", "syscon"; 981 reg = <0x33000 0x1000>; 982 }; 983 984 icssg0_intc: interrupt-controller@20000 { 985 compatible = "ti,icssg-intc"; 986 reg = <0x20000 0x2000>; 987 interrupt-controller; 988 #interrupt-cells = <3>; 989 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 997 interrupt-names = "host_intr0", "host_intr1", 998 "host_intr2", "host_intr3", 999 "host_intr4", "host_intr5", 1000 "host_intr6", "host_intr7"; 1001 }; 1002 1003 pru0_0: pru@34000 { 1004 compatible = "ti,am654-pru"; 1005 reg = <0x34000 0x4000>, 1006 <0x22000 0x100>, 1007 <0x22400 0x100>; 1008 reg-names = "iram", "control", "debug"; 1009 firmware-name = "am65x-pru0_0-fw"; 1010 }; 1011 1012 rtu0_0: rtu@4000 { 1013 compatible = "ti,am654-rtu"; 1014 reg = <0x4000 0x2000>, 1015 <0x23000 0x100>, 1016 <0x23400 0x100>; 1017 reg-names = "iram", "control", "debug"; 1018 firmware-name = "am65x-rtu0_0-fw"; 1019 }; 1020 1021 tx_pru0_0: txpru@a000 { 1022 compatible = "ti,am654-tx-pru"; 1023 reg = <0xa000 0x1800>, 1024 <0x25000 0x100>, 1025 <0x25400 0x100>; 1026 reg-names = "iram", "control", "debug"; 1027 firmware-name = "am65x-txpru0_0-fw"; 1028 }; 1029 1030 pru0_1: pru@38000 { 1031 compatible = "ti,am654-pru"; 1032 reg = <0x38000 0x4000>, 1033 <0x24000 0x100>, 1034 <0x24400 0x100>; 1035 reg-names = "iram", "control", "debug"; 1036 firmware-name = "am65x-pru0_1-fw"; 1037 }; 1038 1039 rtu0_1: rtu@6000 { 1040 compatible = "ti,am654-rtu"; 1041 reg = <0x6000 0x2000>, 1042 <0x23800 0x100>, 1043 <0x23c00 0x100>; 1044 reg-names = "iram", "control", "debug"; 1045 firmware-name = "am65x-rtu0_1-fw"; 1046 }; 1047 1048 tx_pru0_1: txpru@c000 { 1049 compatible = "ti,am654-tx-pru"; 1050 reg = <0xc000 0x1800>, 1051 <0x25800 0x100>, 1052 <0x25c00 0x100>; 1053 reg-names = "iram", "control", "debug"; 1054 firmware-name = "am65x-txpru0_1-fw"; 1055 }; 1056 }; 1057 1058 icssg1: icssg@b100000 { 1059 compatible = "ti,am654-icssg"; 1060 reg = <0x00 0xb100000 0x00 0x80000>; 1061 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 1062 #address-cells = <1>; 1063 #size-cells = <1>; 1064 ranges = <0x0 0x00 0xb100000 0x80000>; 1065 1066 icssg1_mem: memories@0 { 1067 reg = <0x0 0x2000>, 1068 <0x2000 0x2000>, 1069 <0x10000 0x10000>; 1070 reg-names = "dram0", "dram1", 1071 "shrdram2"; 1072 }; 1073 1074 icssg1_cfg: cfg@26000 { 1075 compatible = "ti,pruss-cfg", "syscon"; 1076 reg = <0x26000 0x200>; 1077 #address-cells = <1>; 1078 #size-cells = <1>; 1079 ranges = <0x0 0x26000 0x2000>; 1080 1081 clocks { 1082 #address-cells = <1>; 1083 #size-cells = <0>; 1084 1085 icssg1_coreclk_mux: coreclk-mux@3c { 1086 reg = <0x3c>; 1087 #clock-cells = <0>; 1088 clocks = <&k3_clks 63 19>, /* icssg1_core_clk */ 1089 <&k3_clks 63 3>; /* icssg1_iclk */ 1090 assigned-clocks = <&icssg1_coreclk_mux>; 1091 assigned-clock-parents = <&k3_clks 63 3>; 1092 }; 1093 1094 icssg1_iepclk_mux: iepclk-mux@30 { 1095 reg = <0x30>; 1096 #clock-cells = <0>; 1097 clocks = <&k3_clks 63 10>, /* icssg1_iep_clk */ 1098 <&icssg1_coreclk_mux>; /* core_clk */ 1099 assigned-clocks = <&icssg1_iepclk_mux>; 1100 assigned-clock-parents = <&icssg1_coreclk_mux>; 1101 }; 1102 }; 1103 }; 1104 1105 icssg1_mii_rt: mii-rt@32000 { 1106 compatible = "ti,pruss-mii", "syscon"; 1107 reg = <0x32000 0x100>; 1108 }; 1109 1110 icssg1_mii_g_rt: mii-g-rt@33000 { 1111 compatible = "ti,pruss-mii-g", "syscon"; 1112 reg = <0x33000 0x1000>; 1113 }; 1114 1115 icssg1_intc: interrupt-controller@20000 { 1116 compatible = "ti,icssg-intc"; 1117 reg = <0x20000 0x2000>; 1118 interrupt-controller; 1119 #interrupt-cells = <3>; 1120 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 1128 interrupt-names = "host_intr0", "host_intr1", 1129 "host_intr2", "host_intr3", 1130 "host_intr4", "host_intr5", 1131 "host_intr6", "host_intr7"; 1132 }; 1133 1134 pru1_0: pru@34000 { 1135 compatible = "ti,am654-pru"; 1136 reg = <0x34000 0x4000>, 1137 <0x22000 0x100>, 1138 <0x22400 0x100>; 1139 reg-names = "iram", "control", "debug"; 1140 firmware-name = "am65x-pru1_0-fw"; 1141 }; 1142 1143 rtu1_0: rtu@4000 { 1144 compatible = "ti,am654-rtu"; 1145 reg = <0x4000 0x2000>, 1146 <0x23000 0x100>, 1147 <0x23400 0x100>; 1148 reg-names = "iram", "control", "debug"; 1149 firmware-name = "am65x-rtu1_0-fw"; 1150 }; 1151 1152 tx_pru1_0: txpru@a000 { 1153 compatible = "ti,am654-tx-pru"; 1154 reg = <0xa000 0x1800>, 1155 <0x25000 0x100>, 1156 <0x25400 0x100>; 1157 reg-names = "iram", "control", "debug"; 1158 firmware-name = "am65x-txpru1_0-fw"; 1159 }; 1160 1161 pru1_1: pru@38000 { 1162 compatible = "ti,am654-pru"; 1163 reg = <0x38000 0x4000>, 1164 <0x24000 0x100>, 1165 <0x24400 0x100>; 1166 reg-names = "iram", "control", "debug"; 1167 firmware-name = "am65x-pru1_1-fw"; 1168 }; 1169 1170 rtu1_1: rtu@6000 { 1171 compatible = "ti,am654-rtu"; 1172 reg = <0x6000 0x2000>, 1173 <0x23800 0x100>, 1174 <0x23c00 0x100>; 1175 reg-names = "iram", "control", "debug"; 1176 firmware-name = "am65x-rtu1_1-fw"; 1177 }; 1178 1179 tx_pru1_1: txpru@c000 { 1180 compatible = "ti,am654-tx-pru"; 1181 reg = <0xc000 0x1800>, 1182 <0x25800 0x100>, 1183 <0x25c00 0x100>; 1184 reg-names = "iram", "control", "debug"; 1185 firmware-name = "am65x-txpru1_1-fw"; 1186 }; 1187 }; 1188 1189 icssg2: icssg@b200000 { 1190 compatible = "ti,am654-icssg"; 1191 reg = <0x00 0xb200000 0x00 0x80000>; 1192 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1193 #address-cells = <1>; 1194 #size-cells = <1>; 1195 ranges = <0x0 0x00 0xb200000 0x80000>; 1196 1197 icssg2_mem: memories@0 { 1198 reg = <0x0 0x2000>, 1199 <0x2000 0x2000>, 1200 <0x10000 0x10000>; 1201 reg-names = "dram0", "dram1", 1202 "shrdram2"; 1203 }; 1204 1205 icssg2_cfg: cfg@26000 { 1206 compatible = "ti,pruss-cfg", "syscon"; 1207 reg = <0x26000 0x200>; 1208 #address-cells = <1>; 1209 #size-cells = <1>; 1210 ranges = <0x0 0x26000 0x2000>; 1211 1212 clocks { 1213 #address-cells = <1>; 1214 #size-cells = <0>; 1215 1216 icssg2_coreclk_mux: coreclk-mux@3c { 1217 reg = <0x3c>; 1218 #clock-cells = <0>; 1219 clocks = <&k3_clks 64 19>, /* icssg1_core_clk */ 1220 <&k3_clks 64 3>; /* icssg1_iclk */ 1221 assigned-clocks = <&icssg2_coreclk_mux>; 1222 assigned-clock-parents = <&k3_clks 64 3>; 1223 }; 1224 1225 icssg2_iepclk_mux: iepclk-mux@30 { 1226 reg = <0x30>; 1227 #clock-cells = <0>; 1228 clocks = <&k3_clks 64 10>, /* icssg1_iep_clk */ 1229 <&icssg2_coreclk_mux>; /* core_clk */ 1230 assigned-clocks = <&icssg2_iepclk_mux>; 1231 assigned-clock-parents = <&icssg2_coreclk_mux>; 1232 }; 1233 }; 1234 }; 1235 1236 icssg2_mii_rt: mii-rt@32000 { 1237 compatible = "ti,pruss-mii", "syscon"; 1238 reg = <0x32000 0x100>; 1239 }; 1240 1241 icssg2_mii_g_rt: mii-g-rt@33000 { 1242 compatible = "ti,pruss-mii-g", "syscon"; 1243 reg = <0x33000 0x1000>; 1244 }; 1245 1246 icssg2_intc: interrupt-controller@20000 { 1247 compatible = "ti,icssg-intc"; 1248 reg = <0x20000 0x2000>; 1249 interrupt-controller; 1250 #interrupt-cells = <3>; 1251 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 1252 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 1253 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 1254 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 1255 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 1256 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; 1259 interrupt-names = "host_intr0", "host_intr1", 1260 "host_intr2", "host_intr3", 1261 "host_intr4", "host_intr5", 1262 "host_intr6", "host_intr7"; 1263 }; 1264 1265 pru2_0: pru@34000 { 1266 compatible = "ti,am654-pru"; 1267 reg = <0x34000 0x4000>, 1268 <0x22000 0x100>, 1269 <0x22400 0x100>; 1270 reg-names = "iram", "control", "debug"; 1271 firmware-name = "am65x-pru2_0-fw"; 1272 }; 1273 1274 rtu2_0: rtu@4000 { 1275 compatible = "ti,am654-rtu"; 1276 reg = <0x4000 0x2000>, 1277 <0x23000 0x100>, 1278 <0x23400 0x100>; 1279 reg-names = "iram", "control", "debug"; 1280 firmware-name = "am65x-rtu2_0-fw"; 1281 }; 1282 1283 tx_pru2_0: txpru@a000 { 1284 compatible = "ti,am654-tx-pru"; 1285 reg = <0xa000 0x1800>, 1286 <0x25000 0x100>, 1287 <0x25400 0x100>; 1288 reg-names = "iram", "control", "debug"; 1289 firmware-name = "am65x-txpru2_0-fw"; 1290 }; 1291 1292 pru2_1: pru@38000 { 1293 compatible = "ti,am654-pru"; 1294 reg = <0x38000 0x4000>, 1295 <0x24000 0x100>, 1296 <0x24400 0x100>; 1297 reg-names = "iram", "control", "debug"; 1298 firmware-name = "am65x-pru2_1-fw"; 1299 }; 1300 1301 rtu2_1: rtu@6000 { 1302 compatible = "ti,am654-rtu"; 1303 reg = <0x6000 0x2000>, 1304 <0x23800 0x100>, 1305 <0x23c00 0x100>; 1306 reg-names = "iram", "control", "debug"; 1307 firmware-name = "am65x-rtu2_1-fw"; 1308 }; 1309 1310 tx_pru2_1: txpru@c000 { 1311 compatible = "ti,am654-tx-pru"; 1312 reg = <0xc000 0x1800>, 1313 <0x25800 0x100>, 1314 <0x25c00 0x100>; 1315 reg-names = "iram", "control", "debug"; 1316 firmware-name = "am65x-txpru2_1-fw"; 1317 }; 1318 }; 1319}; 1320