1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM6 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy-am654-serdes.h> 8 9&cbass_main { 10 msmc_ram: sram@70000000 { 11 compatible = "mmio-sram"; 12 reg = <0x0 0x70000000 0x0 0x200000>; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 ranges = <0x0 0x0 0x70000000 0x200000>; 16 17 atf-sram@0 { 18 reg = <0x0 0x20000>; 19 }; 20 21 sysfw-sram@f0000 { 22 reg = <0xf0000 0x10000>; 23 }; 24 25 l3cache-sram@100000 { 26 reg = <0x100000 0x100000>; 27 }; 28 }; 29 30 gic500: interrupt-controller@1800000 { 31 compatible = "arm,gic-v3"; 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 #interrupt-cells = <3>; 36 interrupt-controller; 37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 38 <0x00 0x01880000 0x00 0x90000>, /* GICR */ 39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 41 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 42 /* 43 * vcpumntirq: 44 * virtual CPU interface maintenance interrupt 45 */ 46 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 47 48 gic_its: msi-controller@1820000 { 49 compatible = "arm,gic-v3-its"; 50 reg = <0x00 0x01820000 0x00 0x10000>; 51 socionext,synquacer-pre-its = <0x1000000 0x400000>; 52 msi-controller; 53 #msi-cells = <1>; 54 }; 55 }; 56 57 serdes0: serdes@900000 { 58 compatible = "ti,phy-am654-serdes"; 59 reg = <0x0 0x900000 0x0 0x2000>; 60 reg-names = "serdes"; 61 #phy-cells = <2>; 62 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 63 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>; 64 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk"; 65 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; 66 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; 67 ti,serdes-clk = <&serdes0_clk>; 68 #clock-cells = <1>; 69 mux-controls = <&serdes_mux 0>; 70 }; 71 72 serdes1: serdes@910000 { 73 compatible = "ti,phy-am654-serdes"; 74 reg = <0x0 0x910000 0x0 0x2000>; 75 reg-names = "serdes"; 76 #phy-cells = <2>; 77 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 78 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>; 79 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk"; 80 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>; 81 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>; 82 ti,serdes-clk = <&serdes1_clk>; 83 #clock-cells = <1>; 84 mux-controls = <&serdes_mux 1>; 85 }; 86 87 main_uart0: serial@2800000 { 88 compatible = "ti,am654-uart"; 89 reg = <0x00 0x02800000 0x00 0x100>; 90 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 91 clock-frequency = <48000000>; 92 current-speed = <115200>; 93 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 94 }; 95 96 main_uart1: serial@2810000 { 97 compatible = "ti,am654-uart"; 98 reg = <0x00 0x02810000 0x00 0x100>; 99 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 100 clock-frequency = <48000000>; 101 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 102 }; 103 104 main_uart2: serial@2820000 { 105 compatible = "ti,am654-uart"; 106 reg = <0x00 0x02820000 0x00 0x100>; 107 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 108 clock-frequency = <48000000>; 109 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 110 }; 111 112 crypto: crypto@4e00000 { 113 compatible = "ti,am654-sa2ul"; 114 reg = <0x0 0x4e00000 0x0 0x1200>; 115 power-domains = <&k3_pds 136 TI_SCI_PD_SHARED>; 116 #address-cells = <2>; 117 #size-cells = <2>; 118 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 119 120 dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>, 121 <&main_udmap 0x4003>; 122 dma-names = "tx", "rx1", "rx2"; 123 dma-coherent; 124 125 rng: rng@4e10000 { 126 compatible = "inside-secure,safexcel-eip76"; 127 reg = <0x0 0x4e10000 0x0 0x7d>; 128 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 129 clocks = <&k3_clks 136 1>; 130 status = "disabled"; /* Used by OP-TEE */ 131 }; 132 }; 133 134 main_pmx0: pinctrl@11c000 { 135 compatible = "pinctrl-single"; 136 reg = <0x0 0x11c000 0x0 0x2e4>; 137 #pinctrl-cells = <1>; 138 pinctrl-single,register-width = <32>; 139 pinctrl-single,function-mask = <0xffffffff>; 140 }; 141 142 main_pmx1: pinctrl@11c2e8 { 143 compatible = "pinctrl-single"; 144 reg = <0x0 0x11c2e8 0x0 0x24>; 145 #pinctrl-cells = <1>; 146 pinctrl-single,register-width = <32>; 147 pinctrl-single,function-mask = <0xffffffff>; 148 }; 149 150 main_i2c0: i2c@2000000 { 151 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 152 reg = <0x0 0x2000000 0x0 0x100>; 153 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 154 #address-cells = <1>; 155 #size-cells = <0>; 156 clock-names = "fck"; 157 clocks = <&k3_clks 110 1>; 158 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 159 }; 160 161 main_i2c1: i2c@2010000 { 162 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 163 reg = <0x0 0x2010000 0x0 0x100>; 164 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 clock-names = "fck"; 168 clocks = <&k3_clks 111 1>; 169 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 170 }; 171 172 main_i2c2: i2c@2020000 { 173 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 174 reg = <0x0 0x2020000 0x0 0x100>; 175 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 176 #address-cells = <1>; 177 #size-cells = <0>; 178 clock-names = "fck"; 179 clocks = <&k3_clks 112 1>; 180 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 181 }; 182 183 main_i2c3: i2c@2030000 { 184 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 185 reg = <0x0 0x2030000 0x0 0x100>; 186 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 187 #address-cells = <1>; 188 #size-cells = <0>; 189 clock-names = "fck"; 190 clocks = <&k3_clks 113 1>; 191 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 192 }; 193 194 ecap0: pwm@3100000 { 195 compatible = "ti,am654-ecap", "ti,am3352-ecap"; 196 #pwm-cells = <3>; 197 reg = <0x0 0x03100000 0x0 0x60>; 198 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 199 clocks = <&k3_clks 39 0>; 200 clock-names = "fck"; 201 }; 202 203 main_spi0: spi@2100000 { 204 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 205 reg = <0x0 0x2100000 0x0 0x400>; 206 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 207 clocks = <&k3_clks 137 1>; 208 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; 209 #address-cells = <1>; 210 #size-cells = <0>; 211 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 212 dma-names = "tx0", "rx0"; 213 }; 214 215 main_spi1: spi@2110000 { 216 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 217 reg = <0x0 0x2110000 0x0 0x400>; 218 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&k3_clks 138 1>; 220 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>; 221 #address-cells = <1>; 222 #size-cells = <0>; 223 assigned-clocks = <&k3_clks 137 1>; 224 assigned-clock-rates = <48000000>; 225 }; 226 227 main_spi2: spi@2120000 { 228 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 229 reg = <0x0 0x2120000 0x0 0x400>; 230 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&k3_clks 139 1>; 232 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 }; 236 237 main_spi3: spi@2130000 { 238 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 239 reg = <0x0 0x2130000 0x0 0x400>; 240 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 241 clocks = <&k3_clks 140 1>; 242 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 }; 246 247 main_spi4: spi@2140000 { 248 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 249 reg = <0x0 0x2140000 0x0 0x400>; 250 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&k3_clks 141 1>; 252 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 }; 256 257 sdhci0: mmc@4f80000 { 258 compatible = "ti,am654-sdhci-5.1"; 259 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; 260 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; 261 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>; 262 clock-names = "clk_ahb", "clk_xin"; 263 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 264 mmc-ddr-1_8v; 265 mmc-hs200-1_8v; 266 ti,otap-del-sel-legacy = <0x0>; 267 ti,otap-del-sel-mmc-hs = <0x0>; 268 ti,otap-del-sel-sd-hs = <0x0>; 269 ti,otap-del-sel-sdr12 = <0x0>; 270 ti,otap-del-sel-sdr25 = <0x0>; 271 ti,otap-del-sel-sdr50 = <0x8>; 272 ti,otap-del-sel-sdr104 = <0x7>; 273 ti,otap-del-sel-ddr50 = <0x5>; 274 ti,otap-del-sel-ddr52 = <0x5>; 275 ti,otap-del-sel-hs200 = <0x5>; 276 ti,otap-del-sel-hs400 = <0x0>; 277 ti,trm-icp = <0x8>; 278 dma-coherent; 279 }; 280 281 sdhci1: mmc@4fa0000 { 282 compatible = "ti,am654-sdhci-5.1"; 283 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>; 284 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; 285 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>; 286 clock-names = "clk_ahb", "clk_xin"; 287 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 288 ti,otap-del-sel-legacy = <0x0>; 289 ti,otap-del-sel-mmc-hs = <0x0>; 290 ti,otap-del-sel-sd-hs = <0x0>; 291 ti,otap-del-sel-sdr12 = <0x0>; 292 ti,otap-del-sel-sdr25 = <0x0>; 293 ti,otap-del-sel-sdr50 = <0x8>; 294 ti,otap-del-sel-sdr104 = <0x7>; 295 ti,otap-del-sel-ddr50 = <0x4>; 296 ti,otap-del-sel-ddr52 = <0x4>; 297 ti,otap-del-sel-hs200 = <0x7>; 298 ti,clkbuf-sel = <0x7>; 299 ti,otap-del-sel = <0x2>; 300 ti,trm-icp = <0x8>; 301 dma-coherent; 302 }; 303 304 scm_conf: scm-conf@100000 { 305 compatible = "syscon", "simple-mfd"; 306 reg = <0 0x00100000 0 0x1c000>; 307 #address-cells = <1>; 308 #size-cells = <1>; 309 ranges = <0x0 0x0 0x00100000 0x1c000>; 310 311 pcie0_mode: pcie-mode@4060 { 312 compatible = "syscon"; 313 reg = <0x00004060 0x4>; 314 }; 315 316 pcie1_mode: pcie-mode@4070 { 317 compatible = "syscon"; 318 reg = <0x00004070 0x4>; 319 }; 320 321 pcie_devid: pcie-devid@210 { 322 compatible = "syscon"; 323 reg = <0x00000210 0x4>; 324 }; 325 326 serdes0_clk: clock@4080 { 327 compatible = "syscon"; 328 reg = <0x00004080 0x4>; 329 }; 330 331 serdes1_clk: clock@4090 { 332 compatible = "syscon"; 333 reg = <0x00004090 0x4>; 334 }; 335 336 serdes_mux: mux-controller { 337 compatible = "mmio-mux"; 338 #mux-control-cells = <1>; 339 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */ 340 <0x4090 0x3>; /* SERDES1 lane select */ 341 }; 342 343 dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 { 344 compatible = "syscon"; 345 reg = <0x0000041e0 0x14>; 346 }; 347 348 ehrpwm_tbclk: clock@4140 { 349 compatible = "ti,am654-ehrpwm-tbclk", "syscon"; 350 reg = <0x4140 0x18>; 351 #clock-cells = <1>; 352 }; 353 }; 354 355 dwc3_0: dwc3@4000000 { 356 compatible = "ti,am654-dwc3"; 357 reg = <0x0 0x4000000 0x0 0x4000>; 358 #address-cells = <1>; 359 #size-cells = <1>; 360 ranges = <0x0 0x0 0x4000000 0x20000>; 361 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 362 dma-coherent; 363 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; 364 clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 365 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 366 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 367 <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ 368 369 usb0: usb@10000 { 370 compatible = "snps,dwc3"; 371 reg = <0x10000 0x10000>; 372 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 375 interrupt-names = "peripheral", 376 "host", 377 "otg"; 378 maximum-speed = "high-speed"; 379 dr_mode = "otg"; 380 phys = <&usb0_phy>; 381 phy-names = "usb2-phy"; 382 snps,dis_u3_susphy_quirk; 383 }; 384 }; 385 386 usb0_phy: phy@4100000 { 387 compatible = "ti,am654-usb2", "ti,omap-usb2"; 388 reg = <0x0 0x4100000 0x0 0x54>; 389 syscon-phy-power = <&scm_conf 0x4000>; 390 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>; 391 clock-names = "wkupclk", "refclk"; 392 #phy-cells = <0>; 393 }; 394 395 dwc3_1: dwc3@4020000 { 396 compatible = "ti,am654-dwc3"; 397 reg = <0x0 0x4020000 0x0 0x4000>; 398 #address-cells = <1>; 399 #size-cells = <1>; 400 ranges = <0x0 0x0 0x4020000 0x20000>; 401 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 402 dma-coherent; 403 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 404 clocks = <&k3_clks 152 2>; 405 assigned-clocks = <&k3_clks 152 2>; 406 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 407 408 usb1: usb@10000 { 409 compatible = "snps,dwc3"; 410 reg = <0x10000 0x10000>; 411 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 413 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 414 interrupt-names = "peripheral", 415 "host", 416 "otg"; 417 maximum-speed = "high-speed"; 418 dr_mode = "otg"; 419 phys = <&usb1_phy>; 420 phy-names = "usb2-phy"; 421 }; 422 }; 423 424 usb1_phy: phy@4110000 { 425 compatible = "ti,am654-usb2", "ti,omap-usb2"; 426 reg = <0x0 0x4110000 0x0 0x54>; 427 syscon-phy-power = <&scm_conf 0x4020>; 428 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>; 429 clock-names = "wkupclk", "refclk"; 430 #phy-cells = <0>; 431 }; 432 433 intr_main_gpio: interrupt-controller@a00000 { 434 compatible = "ti,sci-intr"; 435 reg = <0x0 0x00a00000 0x0 0x400>; 436 ti,intr-trigger-type = <1>; 437 interrupt-controller; 438 interrupt-parent = <&gic500>; 439 #interrupt-cells = <1>; 440 ti,sci = <&dmsc>; 441 ti,sci-dev-id = <100>; 442 ti,interrupt-ranges = <0 392 32>; 443 }; 444 445 main_navss: bus@30800000 { 446 compatible = "simple-mfd"; 447 #address-cells = <2>; 448 #size-cells = <2>; 449 ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0xbc00000>; 450 dma-coherent; 451 dma-ranges; 452 453 ti,sci-dev-id = <118>; 454 455 intr_main_navss: interrupt-controller@310e0000 { 456 compatible = "ti,sci-intr"; 457 reg = <0x0 0x310e0000 0x0 0x2000>; 458 ti,intr-trigger-type = <4>; 459 interrupt-controller; 460 interrupt-parent = <&gic500>; 461 #interrupt-cells = <1>; 462 ti,sci = <&dmsc>; 463 ti,sci-dev-id = <182>; 464 ti,interrupt-ranges = <0 64 64>, 465 <64 448 64>; 466 }; 467 468 inta_main_udmass: interrupt-controller@33d00000 { 469 compatible = "ti,sci-inta"; 470 reg = <0x0 0x33d00000 0x0 0x100000>; 471 interrupt-controller; 472 interrupt-parent = <&intr_main_navss>; 473 msi-controller; 474 #interrupt-cells = <0>; 475 ti,sci = <&dmsc>; 476 ti,sci-dev-id = <179>; 477 ti,interrupt-ranges = <0 0 256>; 478 }; 479 480 secure_proxy_main: mailbox@32c00000 { 481 compatible = "ti,am654-secure-proxy"; 482 #mbox-cells = <1>; 483 reg-names = "target_data", "rt", "scfg"; 484 reg = <0x00 0x32c00000 0x00 0x100000>, 485 <0x00 0x32400000 0x00 0x100000>, 486 <0x00 0x32800000 0x00 0x100000>; 487 interrupt-names = "rx_011"; 488 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 489 }; 490 491 hwspinlock: spinlock@30e00000 { 492 compatible = "ti,am654-hwspinlock"; 493 reg = <0x00 0x30e00000 0x00 0x1000>; 494 #hwlock-cells = <1>; 495 }; 496 497 mailbox0_cluster0: mailbox@31f80000 { 498 compatible = "ti,am654-mailbox"; 499 reg = <0x00 0x31f80000 0x00 0x200>; 500 #mbox-cells = <1>; 501 ti,mbox-num-users = <4>; 502 ti,mbox-num-fifos = <16>; 503 interrupt-parent = <&intr_main_navss>; 504 }; 505 506 mailbox0_cluster1: mailbox@31f81000 { 507 compatible = "ti,am654-mailbox"; 508 reg = <0x00 0x31f81000 0x00 0x200>; 509 #mbox-cells = <1>; 510 ti,mbox-num-users = <4>; 511 ti,mbox-num-fifos = <16>; 512 interrupt-parent = <&intr_main_navss>; 513 }; 514 515 mailbox0_cluster2: mailbox@31f82000 { 516 compatible = "ti,am654-mailbox"; 517 reg = <0x00 0x31f82000 0x00 0x200>; 518 #mbox-cells = <1>; 519 ti,mbox-num-users = <4>; 520 ti,mbox-num-fifos = <16>; 521 interrupt-parent = <&intr_main_navss>; 522 }; 523 524 mailbox0_cluster3: mailbox@31f83000 { 525 compatible = "ti,am654-mailbox"; 526 reg = <0x00 0x31f83000 0x00 0x200>; 527 #mbox-cells = <1>; 528 ti,mbox-num-users = <4>; 529 ti,mbox-num-fifos = <16>; 530 interrupt-parent = <&intr_main_navss>; 531 }; 532 533 mailbox0_cluster4: mailbox@31f84000 { 534 compatible = "ti,am654-mailbox"; 535 reg = <0x00 0x31f84000 0x00 0x200>; 536 #mbox-cells = <1>; 537 ti,mbox-num-users = <4>; 538 ti,mbox-num-fifos = <16>; 539 interrupt-parent = <&intr_main_navss>; 540 }; 541 542 mailbox0_cluster5: mailbox@31f85000 { 543 compatible = "ti,am654-mailbox"; 544 reg = <0x00 0x31f85000 0x00 0x200>; 545 #mbox-cells = <1>; 546 ti,mbox-num-users = <4>; 547 ti,mbox-num-fifos = <16>; 548 interrupt-parent = <&intr_main_navss>; 549 }; 550 551 mailbox0_cluster6: mailbox@31f86000 { 552 compatible = "ti,am654-mailbox"; 553 reg = <0x00 0x31f86000 0x00 0x200>; 554 #mbox-cells = <1>; 555 ti,mbox-num-users = <4>; 556 ti,mbox-num-fifos = <16>; 557 interrupt-parent = <&intr_main_navss>; 558 }; 559 560 mailbox0_cluster7: mailbox@31f87000 { 561 compatible = "ti,am654-mailbox"; 562 reg = <0x00 0x31f87000 0x00 0x200>; 563 #mbox-cells = <1>; 564 ti,mbox-num-users = <4>; 565 ti,mbox-num-fifos = <16>; 566 interrupt-parent = <&intr_main_navss>; 567 }; 568 569 mailbox0_cluster8: mailbox@31f88000 { 570 compatible = "ti,am654-mailbox"; 571 reg = <0x00 0x31f88000 0x00 0x200>; 572 #mbox-cells = <1>; 573 ti,mbox-num-users = <4>; 574 ti,mbox-num-fifos = <16>; 575 interrupt-parent = <&intr_main_navss>; 576 }; 577 578 mailbox0_cluster9: mailbox@31f89000 { 579 compatible = "ti,am654-mailbox"; 580 reg = <0x00 0x31f89000 0x00 0x200>; 581 #mbox-cells = <1>; 582 ti,mbox-num-users = <4>; 583 ti,mbox-num-fifos = <16>; 584 interrupt-parent = <&intr_main_navss>; 585 }; 586 587 mailbox0_cluster10: mailbox@31f8a000 { 588 compatible = "ti,am654-mailbox"; 589 reg = <0x00 0x31f8a000 0x00 0x200>; 590 #mbox-cells = <1>; 591 ti,mbox-num-users = <4>; 592 ti,mbox-num-fifos = <16>; 593 interrupt-parent = <&intr_main_navss>; 594 }; 595 596 mailbox0_cluster11: mailbox@31f8b000 { 597 compatible = "ti,am654-mailbox"; 598 reg = <0x00 0x31f8b000 0x00 0x200>; 599 #mbox-cells = <1>; 600 ti,mbox-num-users = <4>; 601 ti,mbox-num-fifos = <16>; 602 interrupt-parent = <&intr_main_navss>; 603 }; 604 605 ringacc: ringacc@3c000000 { 606 compatible = "ti,am654-navss-ringacc"; 607 reg = <0x0 0x3c000000 0x0 0x400000>, 608 <0x0 0x38000000 0x0 0x400000>, 609 <0x0 0x31120000 0x0 0x100>, 610 <0x0 0x33000000 0x0 0x40000>; 611 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 612 ti,num-rings = <818>; 613 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 614 ti,sci = <&dmsc>; 615 ti,sci-dev-id = <187>; 616 msi-parent = <&inta_main_udmass>; 617 }; 618 619 main_udmap: dma-controller@31150000 { 620 compatible = "ti,am654-navss-main-udmap"; 621 reg = <0x0 0x31150000 0x0 0x100>, 622 <0x0 0x34000000 0x0 0x100000>, 623 <0x0 0x35000000 0x0 0x100000>; 624 reg-names = "gcfg", "rchanrt", "tchanrt"; 625 msi-parent = <&inta_main_udmass>; 626 #dma-cells = <1>; 627 628 ti,sci = <&dmsc>; 629 ti,sci-dev-id = <188>; 630 ti,ringacc = <&ringacc>; 631 632 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */ 633 <0xd>; /* TX_CHAN */ 634 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */ 635 <0xa>; /* RX_CHAN */ 636 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */ 637 }; 638 639 cpts@310d0000 { 640 compatible = "ti,am65-cpts"; 641 reg = <0x0 0x310d0000 0x0 0x400>; 642 reg-names = "cpts"; 643 clocks = <&main_cpts_mux>; 644 clock-names = "cpts"; 645 interrupts-extended = <&intr_main_navss 391>; 646 interrupt-names = "cpts"; 647 ti,cpts-periodic-outputs = <6>; 648 ti,cpts-ext-ts-inputs = <8>; 649 650 main_cpts_mux: refclk-mux { 651 #clock-cells = <0>; 652 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, 653 <&k3_clks 118 6>, <&k3_clks 118 3>, 654 <&k3_clks 118 8>, <&k3_clks 118 14>, 655 <&k3_clks 120 3>, <&k3_clks 121 3>; 656 assigned-clocks = <&main_cpts_mux>; 657 assigned-clock-parents = <&k3_clks 118 5>; 658 }; 659 }; 660 }; 661 662 main_gpio0: gpio@600000 { 663 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 664 reg = <0x0 0x600000 0x0 0x100>; 665 gpio-controller; 666 #gpio-cells = <2>; 667 interrupt-parent = <&intr_main_gpio>; 668 interrupts = <192>, <193>, <194>, <195>, <196>, <197>; 669 interrupt-controller; 670 #interrupt-cells = <2>; 671 ti,ngpio = <96>; 672 ti,davinci-gpio-unbanked = <0>; 673 clocks = <&k3_clks 57 0>; 674 clock-names = "gpio"; 675 }; 676 677 main_gpio1: gpio@601000 { 678 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 679 reg = <0x0 0x601000 0x0 0x100>; 680 gpio-controller; 681 #gpio-cells = <2>; 682 interrupt-parent = <&intr_main_gpio>; 683 interrupts = <200>, <201>, <202>, <203>, <204>, <205>; 684 interrupt-controller; 685 #interrupt-cells = <2>; 686 ti,ngpio = <90>; 687 ti,davinci-gpio-unbanked = <0>; 688 clocks = <&k3_clks 58 0>; 689 clock-names = "gpio"; 690 }; 691 692 pcie0_rc: pcie@5500000 { 693 compatible = "ti,am654-pcie-rc"; 694 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; 695 reg-names = "app", "dbics", "config", "atu"; 696 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 697 #address-cells = <3>; 698 #size-cells = <2>; 699 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000>, 700 <0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; 701 ti,syscon-pcie-id = <&pcie_devid>; 702 ti,syscon-pcie-mode = <&pcie0_mode>; 703 bus-range = <0x0 0xff>; 704 num-viewport = <16>; 705 max-link-speed = <2>; 706 dma-coherent; 707 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 708 msi-map = <0x0 &gic_its 0x0 0x10000>; 709 device_type = "pci"; 710 }; 711 712 pcie0_ep: pcie-ep@5500000 { 713 compatible = "ti,am654-pcie-ep"; 714 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; 715 reg-names = "app", "dbics", "addr_space", "atu"; 716 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 717 ti,syscon-pcie-mode = <&pcie0_mode>; 718 num-ib-windows = <16>; 719 num-ob-windows = <16>; 720 max-link-speed = <2>; 721 dma-coherent; 722 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 723 }; 724 725 pcie1_rc: pcie@5600000 { 726 compatible = "ti,am654-pcie-rc"; 727 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; 728 reg-names = "app", "dbics", "config", "atu"; 729 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 730 #address-cells = <3>; 731 #size-cells = <2>; 732 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000>, 733 <0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>; 734 ti,syscon-pcie-id = <&pcie_devid>; 735 ti,syscon-pcie-mode = <&pcie1_mode>; 736 bus-range = <0x0 0xff>; 737 num-viewport = <16>; 738 max-link-speed = <2>; 739 dma-coherent; 740 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 741 msi-map = <0x0 &gic_its 0x10000 0x10000>; 742 device_type = "pci"; 743 }; 744 745 pcie1_ep: pcie-ep@5600000 { 746 compatible = "ti,am654-pcie-ep"; 747 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; 748 reg-names = "app", "dbics", "addr_space", "atu"; 749 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 750 ti,syscon-pcie-mode = <&pcie1_mode>; 751 num-ib-windows = <16>; 752 num-ob-windows = <16>; 753 max-link-speed = <2>; 754 dma-coherent; 755 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 756 }; 757 758 mcasp0: mcasp@2b00000 { 759 compatible = "ti,am33xx-mcasp-audio"; 760 reg = <0x0 0x02b00000 0x0 0x2000>, 761 <0x0 0x02b08000 0x0 0x1000>; 762 reg-names = "mpu","dat"; 763 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 765 interrupt-names = "tx", "rx"; 766 767 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 768 dma-names = "tx", "rx"; 769 770 clocks = <&k3_clks 104 0>; 771 clock-names = "fck"; 772 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 773 }; 774 775 mcasp1: mcasp@2b10000 { 776 compatible = "ti,am33xx-mcasp-audio"; 777 reg = <0x0 0x02b10000 0x0 0x2000>, 778 <0x0 0x02b18000 0x0 0x1000>; 779 reg-names = "mpu","dat"; 780 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 782 interrupt-names = "tx", "rx"; 783 784 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 785 dma-names = "tx", "rx"; 786 787 clocks = <&k3_clks 105 0>; 788 clock-names = "fck"; 789 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 790 }; 791 792 mcasp2: mcasp@2b20000 { 793 compatible = "ti,am33xx-mcasp-audio"; 794 reg = <0x0 0x02b20000 0x0 0x2000>, 795 <0x0 0x02b28000 0x0 0x1000>; 796 reg-names = "mpu","dat"; 797 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 799 interrupt-names = "tx", "rx"; 800 801 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 802 dma-names = "tx", "rx"; 803 804 clocks = <&k3_clks 106 0>; 805 clock-names = "fck"; 806 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 807 }; 808 809 cal: cal@6f03000 { 810 compatible = "ti,am654-cal"; 811 reg = <0x0 0x06f03000 0x0 0x400>, 812 <0x0 0x06f03800 0x0 0x40>; 813 reg-names = "cal_top", 814 "cal_rx_core0"; 815 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 816 ti,camerrx-control = <&scm_conf 0x40c0>; 817 clock-names = "fck"; 818 clocks = <&k3_clks 2 0>; 819 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>; 820 821 ports { 822 #address-cells = <1>; 823 #size-cells = <0>; 824 825 csi2_0: port@0 { 826 reg = <0>; 827 }; 828 }; 829 }; 830 831 dss: dss@4a00000 { 832 compatible = "ti,am65x-dss"; 833 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ 834 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ 835 <0x0 0x04a06000 0x0 0x1000>, /* vid */ 836 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ 837 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ 838 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ 839 <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ 840 reg-names = "common", "vidl1", "vid", 841 "ovr1", "ovr2", "vp1", "vp2"; 842 843 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; 844 845 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 846 847 clocks = <&k3_clks 67 1>, 848 <&k3_clks 216 1>, 849 <&k3_clks 67 2>; 850 clock-names = "fck", "vp1", "vp2"; 851 852 /* 853 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via 854 * DIV1. See "Figure 12-3365. DSS Integration" 855 * in AM65x TRM for details. 856 */ 857 assigned-clocks = <&k3_clks 67 2>; 858 assigned-clock-parents = <&k3_clks 67 5>; 859 860 interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>; 861 862 dma-coherent; 863 864 dss_ports: ports { 865 #address-cells = <1>; 866 #size-cells = <0>; 867 }; 868 }; 869 870 ehrpwm0: pwm@3000000 { 871 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 872 #pwm-cells = <3>; 873 reg = <0x0 0x3000000 0x0 0x100>; 874 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 875 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>; 876 clock-names = "tbclk", "fck"; 877 }; 878 879 ehrpwm1: pwm@3010000 { 880 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 881 #pwm-cells = <3>; 882 reg = <0x0 0x3010000 0x0 0x100>; 883 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 884 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>; 885 clock-names = "tbclk", "fck"; 886 }; 887 888 ehrpwm2: pwm@3020000 { 889 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 890 #pwm-cells = <3>; 891 reg = <0x0 0x3020000 0x0 0x100>; 892 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 893 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>; 894 clock-names = "tbclk", "fck"; 895 }; 896 897 ehrpwm3: pwm@3030000 { 898 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 899 #pwm-cells = <3>; 900 reg = <0x0 0x3030000 0x0 0x100>; 901 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 902 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>; 903 clock-names = "tbclk", "fck"; 904 }; 905 906 ehrpwm4: pwm@3040000 { 907 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 908 #pwm-cells = <3>; 909 reg = <0x0 0x3040000 0x0 0x100>; 910 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; 911 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>; 912 clock-names = "tbclk", "fck"; 913 }; 914 915 ehrpwm5: pwm@3050000 { 916 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 917 #pwm-cells = <3>; 918 reg = <0x0 0x3050000 0x0 0x100>; 919 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; 920 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>; 921 clock-names = "tbclk", "fck"; 922 }; 923 924 icssg0: icssg@b000000 { 925 compatible = "ti,am654-icssg"; 926 reg = <0x00 0xb000000 0x00 0x80000>; 927 power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; 928 #address-cells = <1>; 929 #size-cells = <1>; 930 ranges = <0x0 0x00 0xb000000 0x80000>; 931 932 icssg0_mem: memories@0 { 933 reg = <0x0 0x2000>, 934 <0x2000 0x2000>, 935 <0x10000 0x10000>; 936 reg-names = "dram0", "dram1", 937 "shrdram2"; 938 }; 939 940 icssg0_cfg: cfg@26000 { 941 compatible = "ti,pruss-cfg", "syscon"; 942 reg = <0x26000 0x200>; 943 #address-cells = <1>; 944 #size-cells = <1>; 945 ranges = <0x0 0x26000 0x2000>; 946 947 clocks { 948 #address-cells = <1>; 949 #size-cells = <0>; 950 951 icssg0_coreclk_mux: coreclk-mux@3c { 952 reg = <0x3c>; 953 #clock-cells = <0>; 954 clocks = <&k3_clks 62 19>, /* icssg0_core_clk */ 955 <&k3_clks 62 3>; /* icssg0_iclk */ 956 assigned-clocks = <&icssg0_coreclk_mux>; 957 assigned-clock-parents = <&k3_clks 62 3>; 958 }; 959 960 icssg0_iepclk_mux: iepclk-mux@30 { 961 reg = <0x30>; 962 #clock-cells = <0>; 963 clocks = <&k3_clks 62 10>, /* icssg0_iep_clk */ 964 <&icssg0_coreclk_mux>; /* core_clk */ 965 assigned-clocks = <&icssg0_iepclk_mux>; 966 assigned-clock-parents = <&icssg0_coreclk_mux>; 967 }; 968 }; 969 }; 970 971 icssg0_mii_rt: mii-rt@32000 { 972 compatible = "ti,pruss-mii", "syscon"; 973 reg = <0x32000 0x100>; 974 }; 975 976 icssg0_mii_g_rt: mii-g-rt@33000 { 977 compatible = "ti,pruss-mii-g", "syscon"; 978 reg = <0x33000 0x1000>; 979 }; 980 981 icssg0_intc: interrupt-controller@20000 { 982 compatible = "ti,icssg-intc"; 983 reg = <0x20000 0x2000>; 984 interrupt-controller; 985 #interrupt-cells = <3>; 986 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 994 interrupt-names = "host_intr0", "host_intr1", 995 "host_intr2", "host_intr3", 996 "host_intr4", "host_intr5", 997 "host_intr6", "host_intr7"; 998 }; 999 1000 pru0_0: pru@34000 { 1001 compatible = "ti,am654-pru"; 1002 reg = <0x34000 0x4000>, 1003 <0x22000 0x100>, 1004 <0x22400 0x100>; 1005 reg-names = "iram", "control", "debug"; 1006 firmware-name = "am65x-pru0_0-fw"; 1007 }; 1008 1009 rtu0_0: rtu@4000 { 1010 compatible = "ti,am654-rtu"; 1011 reg = <0x4000 0x2000>, 1012 <0x23000 0x100>, 1013 <0x23400 0x100>; 1014 reg-names = "iram", "control", "debug"; 1015 firmware-name = "am65x-rtu0_0-fw"; 1016 }; 1017 1018 tx_pru0_0: txpru@a000 { 1019 compatible = "ti,am654-tx-pru"; 1020 reg = <0xa000 0x1800>, 1021 <0x25000 0x100>, 1022 <0x25400 0x100>; 1023 reg-names = "iram", "control", "debug"; 1024 firmware-name = "am65x-txpru0_0-fw"; 1025 }; 1026 1027 pru0_1: pru@38000 { 1028 compatible = "ti,am654-pru"; 1029 reg = <0x38000 0x4000>, 1030 <0x24000 0x100>, 1031 <0x24400 0x100>; 1032 reg-names = "iram", "control", "debug"; 1033 firmware-name = "am65x-pru0_1-fw"; 1034 }; 1035 1036 rtu0_1: rtu@6000 { 1037 compatible = "ti,am654-rtu"; 1038 reg = <0x6000 0x2000>, 1039 <0x23800 0x100>, 1040 <0x23c00 0x100>; 1041 reg-names = "iram", "control", "debug"; 1042 firmware-name = "am65x-rtu0_1-fw"; 1043 }; 1044 1045 tx_pru0_1: txpru@c000 { 1046 compatible = "ti,am654-tx-pru"; 1047 reg = <0xc000 0x1800>, 1048 <0x25800 0x100>, 1049 <0x25c00 0x100>; 1050 reg-names = "iram", "control", "debug"; 1051 firmware-name = "am65x-txpru0_1-fw"; 1052 }; 1053 1054 icssg0_mdio: mdio@32400 { 1055 compatible = "ti,davinci_mdio"; 1056 reg = <0x32400 0x100>; 1057 clocks = <&k3_clks 62 3>; 1058 clock-names = "fck"; 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 bus_freq = <1000000>; 1062 }; 1063 }; 1064 1065 icssg1: icssg@b100000 { 1066 compatible = "ti,am654-icssg"; 1067 reg = <0x00 0xb100000 0x00 0x80000>; 1068 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 1069 #address-cells = <1>; 1070 #size-cells = <1>; 1071 ranges = <0x0 0x00 0xb100000 0x80000>; 1072 1073 icssg1_mem: memories@0 { 1074 reg = <0x0 0x2000>, 1075 <0x2000 0x2000>, 1076 <0x10000 0x10000>; 1077 reg-names = "dram0", "dram1", 1078 "shrdram2"; 1079 }; 1080 1081 icssg1_cfg: cfg@26000 { 1082 compatible = "ti,pruss-cfg", "syscon"; 1083 reg = <0x26000 0x200>; 1084 #address-cells = <1>; 1085 #size-cells = <1>; 1086 ranges = <0x0 0x26000 0x2000>; 1087 1088 clocks { 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 1092 icssg1_coreclk_mux: coreclk-mux@3c { 1093 reg = <0x3c>; 1094 #clock-cells = <0>; 1095 clocks = <&k3_clks 63 19>, /* icssg1_core_clk */ 1096 <&k3_clks 63 3>; /* icssg1_iclk */ 1097 assigned-clocks = <&icssg1_coreclk_mux>; 1098 assigned-clock-parents = <&k3_clks 63 3>; 1099 }; 1100 1101 icssg1_iepclk_mux: iepclk-mux@30 { 1102 reg = <0x30>; 1103 #clock-cells = <0>; 1104 clocks = <&k3_clks 63 10>, /* icssg1_iep_clk */ 1105 <&icssg1_coreclk_mux>; /* core_clk */ 1106 assigned-clocks = <&icssg1_iepclk_mux>; 1107 assigned-clock-parents = <&icssg1_coreclk_mux>; 1108 }; 1109 }; 1110 }; 1111 1112 icssg1_mii_rt: mii-rt@32000 { 1113 compatible = "ti,pruss-mii", "syscon"; 1114 reg = <0x32000 0x100>; 1115 }; 1116 1117 icssg1_mii_g_rt: mii-g-rt@33000 { 1118 compatible = "ti,pruss-mii-g", "syscon"; 1119 reg = <0x33000 0x1000>; 1120 }; 1121 1122 icssg1_intc: interrupt-controller@20000 { 1123 compatible = "ti,icssg-intc"; 1124 reg = <0x20000 0x2000>; 1125 interrupt-controller; 1126 #interrupt-cells = <3>; 1127 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 1135 interrupt-names = "host_intr0", "host_intr1", 1136 "host_intr2", "host_intr3", 1137 "host_intr4", "host_intr5", 1138 "host_intr6", "host_intr7"; 1139 }; 1140 1141 pru1_0: pru@34000 { 1142 compatible = "ti,am654-pru"; 1143 reg = <0x34000 0x4000>, 1144 <0x22000 0x100>, 1145 <0x22400 0x100>; 1146 reg-names = "iram", "control", "debug"; 1147 firmware-name = "am65x-pru1_0-fw"; 1148 }; 1149 1150 rtu1_0: rtu@4000 { 1151 compatible = "ti,am654-rtu"; 1152 reg = <0x4000 0x2000>, 1153 <0x23000 0x100>, 1154 <0x23400 0x100>; 1155 reg-names = "iram", "control", "debug"; 1156 firmware-name = "am65x-rtu1_0-fw"; 1157 }; 1158 1159 tx_pru1_0: txpru@a000 { 1160 compatible = "ti,am654-tx-pru"; 1161 reg = <0xa000 0x1800>, 1162 <0x25000 0x100>, 1163 <0x25400 0x100>; 1164 reg-names = "iram", "control", "debug"; 1165 firmware-name = "am65x-txpru1_0-fw"; 1166 }; 1167 1168 pru1_1: pru@38000 { 1169 compatible = "ti,am654-pru"; 1170 reg = <0x38000 0x4000>, 1171 <0x24000 0x100>, 1172 <0x24400 0x100>; 1173 reg-names = "iram", "control", "debug"; 1174 firmware-name = "am65x-pru1_1-fw"; 1175 }; 1176 1177 rtu1_1: rtu@6000 { 1178 compatible = "ti,am654-rtu"; 1179 reg = <0x6000 0x2000>, 1180 <0x23800 0x100>, 1181 <0x23c00 0x100>; 1182 reg-names = "iram", "control", "debug"; 1183 firmware-name = "am65x-rtu1_1-fw"; 1184 }; 1185 1186 tx_pru1_1: txpru@c000 { 1187 compatible = "ti,am654-tx-pru"; 1188 reg = <0xc000 0x1800>, 1189 <0x25800 0x100>, 1190 <0x25c00 0x100>; 1191 reg-names = "iram", "control", "debug"; 1192 firmware-name = "am65x-txpru1_1-fw"; 1193 }; 1194 1195 icssg1_mdio: mdio@32400 { 1196 compatible = "ti,davinci_mdio"; 1197 reg = <0x32400 0x100>; 1198 clocks = <&k3_clks 63 3>; 1199 clock-names = "fck"; 1200 #address-cells = <1>; 1201 #size-cells = <0>; 1202 bus_freq = <1000000>; 1203 }; 1204 }; 1205 1206 icssg2: icssg@b200000 { 1207 compatible = "ti,am654-icssg"; 1208 reg = <0x00 0xb200000 0x00 0x80000>; 1209 power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; 1210 #address-cells = <1>; 1211 #size-cells = <1>; 1212 ranges = <0x0 0x00 0xb200000 0x80000>; 1213 1214 icssg2_mem: memories@0 { 1215 reg = <0x0 0x2000>, 1216 <0x2000 0x2000>, 1217 <0x10000 0x10000>; 1218 reg-names = "dram0", "dram1", 1219 "shrdram2"; 1220 }; 1221 1222 icssg2_cfg: cfg@26000 { 1223 compatible = "ti,pruss-cfg", "syscon"; 1224 reg = <0x26000 0x200>; 1225 #address-cells = <1>; 1226 #size-cells = <1>; 1227 ranges = <0x0 0x26000 0x2000>; 1228 1229 clocks { 1230 #address-cells = <1>; 1231 #size-cells = <0>; 1232 1233 icssg2_coreclk_mux: coreclk-mux@3c { 1234 reg = <0x3c>; 1235 #clock-cells = <0>; 1236 clocks = <&k3_clks 64 19>, /* icssg1_core_clk */ 1237 <&k3_clks 64 3>; /* icssg1_iclk */ 1238 assigned-clocks = <&icssg2_coreclk_mux>; 1239 assigned-clock-parents = <&k3_clks 64 3>; 1240 }; 1241 1242 icssg2_iepclk_mux: iepclk-mux@30 { 1243 reg = <0x30>; 1244 #clock-cells = <0>; 1245 clocks = <&k3_clks 64 10>, /* icssg1_iep_clk */ 1246 <&icssg2_coreclk_mux>; /* core_clk */ 1247 assigned-clocks = <&icssg2_iepclk_mux>; 1248 assigned-clock-parents = <&icssg2_coreclk_mux>; 1249 }; 1250 }; 1251 }; 1252 1253 icssg2_mii_rt: mii-rt@32000 { 1254 compatible = "ti,pruss-mii", "syscon"; 1255 reg = <0x32000 0x100>; 1256 }; 1257 1258 icssg2_mii_g_rt: mii-g-rt@33000 { 1259 compatible = "ti,pruss-mii-g", "syscon"; 1260 reg = <0x33000 0x1000>; 1261 }; 1262 1263 icssg2_intc: interrupt-controller@20000 { 1264 compatible = "ti,icssg-intc"; 1265 reg = <0x20000 0x2000>; 1266 interrupt-controller; 1267 #interrupt-cells = <3>; 1268 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; 1276 interrupt-names = "host_intr0", "host_intr1", 1277 "host_intr2", "host_intr3", 1278 "host_intr4", "host_intr5", 1279 "host_intr6", "host_intr7"; 1280 }; 1281 1282 pru2_0: pru@34000 { 1283 compatible = "ti,am654-pru"; 1284 reg = <0x34000 0x4000>, 1285 <0x22000 0x100>, 1286 <0x22400 0x100>; 1287 reg-names = "iram", "control", "debug"; 1288 firmware-name = "am65x-pru2_0-fw"; 1289 }; 1290 1291 rtu2_0: rtu@4000 { 1292 compatible = "ti,am654-rtu"; 1293 reg = <0x4000 0x2000>, 1294 <0x23000 0x100>, 1295 <0x23400 0x100>; 1296 reg-names = "iram", "control", "debug"; 1297 firmware-name = "am65x-rtu2_0-fw"; 1298 }; 1299 1300 tx_pru2_0: txpru@a000 { 1301 compatible = "ti,am654-tx-pru"; 1302 reg = <0xa000 0x1800>, 1303 <0x25000 0x100>, 1304 <0x25400 0x100>; 1305 reg-names = "iram", "control", "debug"; 1306 firmware-name = "am65x-txpru2_0-fw"; 1307 }; 1308 1309 pru2_1: pru@38000 { 1310 compatible = "ti,am654-pru"; 1311 reg = <0x38000 0x4000>, 1312 <0x24000 0x100>, 1313 <0x24400 0x100>; 1314 reg-names = "iram", "control", "debug"; 1315 firmware-name = "am65x-pru2_1-fw"; 1316 }; 1317 1318 rtu2_1: rtu@6000 { 1319 compatible = "ti,am654-rtu"; 1320 reg = <0x6000 0x2000>, 1321 <0x23800 0x100>, 1322 <0x23c00 0x100>; 1323 reg-names = "iram", "control", "debug"; 1324 firmware-name = "am65x-rtu2_1-fw"; 1325 }; 1326 1327 tx_pru2_1: txpru@c000 { 1328 compatible = "ti,am654-tx-pru"; 1329 reg = <0xc000 0x1800>, 1330 <0x25800 0x100>, 1331 <0x25c00 0x100>; 1332 reg-names = "iram", "control", "debug"; 1333 firmware-name = "am65x-txpru2_1-fw"; 1334 }; 1335 1336 icssg2_mdio: mdio@32400 { 1337 compatible = "ti,davinci_mdio"; 1338 reg = <0x32400 0x100>; 1339 clocks = <&k3_clks 64 3>; 1340 clock-names = "fck"; 1341 #address-cells = <1>; 1342 #size-cells = <0>; 1343 bus_freq = <1000000>; 1344 }; 1345 }; 1346}; 1347