xref: /freebsd/sys/contrib/device-tree/src/arm64/ti/k3-am642-sk.dts (revision a90b9d0159070121c221b966469c3e36d912bf82)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/phy/phy.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/net/ti-dp83867.h>
11#include <dt-bindings/leds/common.h>
12#include "k3-am642.dtsi"
13
14#include "k3-serdes.h"
15
16/ {
17	compatible = "ti,am642-sk", "ti,am642";
18	model = "Texas Instruments AM642 SK";
19
20	chosen {
21		stdout-path = &main_uart0;
22	};
23
24	aliases {
25		serial0 = &mcu_uart0;
26		serial1 = &main_uart1;
27		serial2 = &main_uart0;
28		i2c0 = &main_i2c0;
29		i2c1 = &main_i2c1;
30		mmc0 = &sdhci0;
31		mmc1 = &sdhci1;
32		ethernet0 = &cpsw_port1;
33		ethernet1 = &cpsw_port2;
34	};
35
36	memory@80000000 {
37		bootph-pre-ram;
38		device_type = "memory";
39		/* 2G RAM */
40		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
41	};
42
43	reserved-memory {
44		#address-cells = <2>;
45		#size-cells = <2>;
46		ranges;
47
48		secure_ddr: optee@9e800000 {
49			reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */
50			alignment = <0x1000>;
51			no-map;
52		};
53
54		main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
55			compatible = "shared-dma-pool";
56			reg = <0x00 0xa0000000 0x00 0x100000>;
57			no-map;
58		};
59
60		main_r5fss0_core0_memory_region: r5f-memory@a0100000 {
61			compatible = "shared-dma-pool";
62			reg = <0x00 0xa0100000 0x00 0xf00000>;
63			no-map;
64		};
65
66		main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
67			compatible = "shared-dma-pool";
68			reg = <0x00 0xa1000000 0x00 0x100000>;
69			no-map;
70		};
71
72		main_r5fss0_core1_memory_region: r5f-memory@a1100000 {
73			compatible = "shared-dma-pool";
74			reg = <0x00 0xa1100000 0x00 0xf00000>;
75			no-map;
76		};
77
78		main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 {
79			compatible = "shared-dma-pool";
80			reg = <0x00 0xa2000000 0x00 0x100000>;
81			no-map;
82		};
83
84		main_r5fss1_core0_memory_region: r5f-memory@a2100000 {
85			compatible = "shared-dma-pool";
86			reg = <0x00 0xa2100000 0x00 0xf00000>;
87			no-map;
88		};
89
90		main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 {
91			compatible = "shared-dma-pool";
92			reg = <0x00 0xa3000000 0x00 0x100000>;
93			no-map;
94		};
95
96		main_r5fss1_core1_memory_region: r5f-memory@a3100000 {
97			compatible = "shared-dma-pool";
98			reg = <0x00 0xa3100000 0x00 0xf00000>;
99			no-map;
100		};
101
102		rtos_ipc_memory_region: ipc-memories@a5000000 {
103			reg = <0x00 0xa5000000 0x00 0x00800000>;
104			alignment = <0x1000>;
105			no-map;
106		};
107	};
108
109	vusb_main: regulator-0 {
110		/* USB MAIN INPUT 5V DC */
111		bootph-all;
112		compatible = "regulator-fixed";
113		regulator-name = "vusb_main5v0";
114		regulator-min-microvolt = <5000000>;
115		regulator-max-microvolt = <5000000>;
116		regulator-always-on;
117		regulator-boot-on;
118	};
119
120	vcc_3v3_sys: regulator-1 {
121		/* output of LP8733xx */
122		bootph-all;
123		compatible = "regulator-fixed";
124		regulator-name = "vcc_3v3_sys";
125		regulator-min-microvolt = <3300000>;
126		regulator-max-microvolt = <3300000>;
127		vin-supply = <&vusb_main>;
128		regulator-always-on;
129		regulator-boot-on;
130	};
131
132	vdd_mmc1: regulator-2 {
133		/* TPS2051BD */
134		bootph-all;
135		compatible = "regulator-fixed";
136		regulator-name = "vdd_mmc1";
137		regulator-min-microvolt = <3300000>;
138		regulator-max-microvolt = <3300000>;
139		regulator-boot-on;
140		enable-active-high;
141		vin-supply = <&vcc_3v3_sys>;
142		gpio = <&exp1 3 GPIO_ACTIVE_HIGH>;
143	};
144
145	com8_ls_en: regulator-3 {
146		compatible = "regulator-fixed";
147		regulator-name = "com8_ls_en";
148		regulator-min-microvolt = <3300000>;
149		regulator-max-microvolt = <3300000>;
150		regulator-always-on;
151		regulator-boot-on;
152		pinctrl-0 = <&main_com8_ls_en_pins_default>;
153		pinctrl-names = "default";
154		gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>;
155	};
156
157	wlan_en: regulator-4 {
158		/* output of SN74AVC4T245RSVR */
159		compatible = "regulator-fixed";
160		regulator-name = "wlan_en";
161		regulator-min-microvolt = <1800000>;
162		regulator-max-microvolt = <1800000>;
163		enable-active-high;
164		pinctrl-0 = <&main_wlan_en_pins_default>;
165		pinctrl-names = "default";
166		vin-supply = <&com8_ls_en>;
167		gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>;
168	};
169
170	led-controller {
171		compatible = "gpio-leds";
172
173		led-0 {
174			color = <LED_COLOR_ID_GREEN>;
175			function = LED_FUNCTION_INDICATOR;
176			function-enumerator = <1>;
177			gpios = <&exp2 0 GPIO_ACTIVE_HIGH>;
178			default-state = "off";
179		};
180
181		led-1 {
182			color = <LED_COLOR_ID_RED>;
183			function = LED_FUNCTION_INDICATOR;
184			function-enumerator = <2>;
185			gpios = <&exp2 1 GPIO_ACTIVE_HIGH>;
186			default-state = "off";
187		};
188
189		led-2 {
190			color = <LED_COLOR_ID_GREEN>;
191			function = LED_FUNCTION_INDICATOR;
192			function-enumerator = <3>;
193			gpios = <&exp2 2 GPIO_ACTIVE_HIGH>;
194			default-state = "off";
195		};
196
197		led-3 {
198			color = <LED_COLOR_ID_AMBER>;
199			function = LED_FUNCTION_INDICATOR;
200			function-enumerator = <4>;
201			gpios = <&exp2 3 GPIO_ACTIVE_HIGH>;
202			default-state = "off";
203		};
204
205		led-4 {
206			color = <LED_COLOR_ID_GREEN>;
207			function = LED_FUNCTION_INDICATOR;
208			function-enumerator = <5>;
209			gpios = <&exp2 4 GPIO_ACTIVE_HIGH>;
210			default-state = "off";
211		};
212
213		led-5 {
214			color = <LED_COLOR_ID_RED>;
215			function = LED_FUNCTION_INDICATOR;
216			function-enumerator = <6>;
217			gpios = <&exp2 5 GPIO_ACTIVE_HIGH>;
218			default-state = "off";
219		};
220
221		led-6 {
222			color = <LED_COLOR_ID_GREEN>;
223			function = LED_FUNCTION_INDICATOR;
224			function-enumerator = <7>;
225			gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
226			default-state = "off";
227		};
228
229		led-7 {
230			color = <LED_COLOR_ID_AMBER>;
231			function = LED_FUNCTION_HEARTBEAT;
232			function-enumerator = <8>;
233			linux,default-trigger = "heartbeat";
234			gpios = <&exp2 7 GPIO_ACTIVE_HIGH>;
235		};
236	};
237};
238
239&main_pmx0 {
240	main_mmc1_pins_default: main-mmc1-default-pins {
241		bootph-all;
242		pinctrl-single,pins = <
243			AM64X_IOPAD(0x029c, PIN_INPUT_PULLUP, 0) /* (C20) MMC1_SDWP */
244			AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */
245			AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */
246			AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */
247			AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */
248			AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */
249			AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */
250			AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */
251			AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */
252		>;
253	};
254
255	main_uart0_pins_default: main-uart0-default-pins {
256		bootph-all;
257		pinctrl-single,pins = <
258			AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */
259			AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */
260			AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */
261			AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */
262		>;
263	};
264
265	main_uart1_pins_default: main-uart1-default-pins {
266		bootph-pre-ram;
267		pinctrl-single,pins = <
268			AM64X_IOPAD(0x0248, PIN_INPUT, 0) /* (D16) UART1_CTSn */
269			AM64X_IOPAD(0x024c, PIN_OUTPUT, 0) /* (E16) UART1_RTSn */
270			AM64X_IOPAD(0x0240, PIN_INPUT, 0) /* (E15) UART1_RXD */
271			AM64X_IOPAD(0x0244, PIN_OUTPUT, 0) /* (E14) UART1_TXD */
272		>;
273	};
274
275	main_usb0_pins_default: main-usb0-default-pins {
276		bootph-all;
277		pinctrl-single,pins = <
278			AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */
279		>;
280	};
281
282	main_i2c0_pins_default: main-i2c0-default-pins {
283		bootph-all;
284		pinctrl-single,pins = <
285			AM64X_IOPAD(0x0260, PIN_INPUT_PULLUP, 0) /* (A18) I2C0_SCL */
286			AM64X_IOPAD(0x0264, PIN_INPUT_PULLUP, 0) /* (B18) I2C0_SDA */
287		>;
288	};
289
290	main_i2c1_pins_default: main-i2c1-default-pins {
291		bootph-all;
292		pinctrl-single,pins = <
293			AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */
294			AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */
295		>;
296	};
297
298	mdio1_pins_default: mdio1-default-pins {
299		pinctrl-single,pins = <
300			AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */
301			AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */
302		>;
303	};
304
305	rgmii1_pins_default: rgmii1-default-pins {
306		pinctrl-single,pins = <
307			AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */
308			AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */
309			AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */
310			AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */
311			AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */
312			AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */
313			AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */
314			AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */
315			AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */
316			AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */
317			AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */
318			AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */
319		>;
320	};
321
322       rgmii2_pins_default: rgmii2-default-pins {
323		pinctrl-single,pins = <
324			AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */
325			AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */
326			AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */
327			AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */
328			AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */
329			AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */
330			AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */
331			AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */
332			AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */
333			AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */
334			AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */
335			AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */
336		>;
337	};
338
339	ospi0_pins_default: ospi0-default-pins {
340		pinctrl-single,pins = <
341			AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */
342			AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */
343			AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */
344			AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */
345			AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */
346			AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */
347			AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */
348			AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */
349			AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */
350			AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */
351			AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */
352		>;
353	};
354
355	main_ecap0_pins_default: main-ecap0-default-pins {
356		pinctrl-single,pins = <
357			AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */
358		>;
359	};
360	main_wlan_en_pins_default: main-wlan-en-default-pins {
361		pinctrl-single,pins = <
362			AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */
363		>;
364	};
365
366	main_com8_ls_en_pins_default: main-com8-ls-en-default-pins {
367		pinctrl-single,pins = <
368			AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */
369		>;
370	};
371
372	main_wlan_pins_default: main-wlan-default-pins {
373		pinctrl-single,pins = <
374			AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */
375		>;
376	};
377};
378
379&main_uart0 {
380	bootph-all;
381	status = "okay";
382	pinctrl-names = "default";
383	pinctrl-0 = <&main_uart0_pins_default>;
384	current-speed = <115200>;
385};
386
387&main_uart1 {
388	/* main_uart1 is reserved for firmware usage */
389	bootph-pre-ram;
390	status = "reserved";
391	pinctrl-names = "default";
392	pinctrl-0 = <&main_uart1_pins_default>;
393};
394
395&main_i2c0 {
396	bootph-all;
397	status = "okay";
398	pinctrl-names = "default";
399	pinctrl-0 = <&main_i2c0_pins_default>;
400	clock-frequency = <400000>;
401
402	eeprom@51 {
403		compatible = "atmel,24c512";
404		reg = <0x51>;
405	};
406};
407
408&main_i2c1 {
409	bootph-all;
410	status = "okay";
411	pinctrl-names = "default";
412	pinctrl-0 = <&main_i2c1_pins_default>;
413	clock-frequency = <400000>;
414
415	exp1: gpio@70 {
416		bootph-all;
417		compatible = "nxp,pca9538";
418		reg = <0x70>;
419		gpio-controller;
420		#gpio-cells = <2>;
421		gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST",
422				  "PRU_DETECT", "MMC1_SD_EN",
423				  "VPP_LDO_EN", "RPI_PS_3V3_En",
424				  "RPI_PS_5V0_En", "RPI_HAT_DETECT";
425	};
426
427	exp2: gpio@60 {
428		compatible = "ti,tpic2810";
429		reg = <0x60>;
430		gpio-controller;
431		#gpio-cells = <2>;
432		gpio-line-names = "LED1","LED2","LED3","LED4","LED5","LED6","LED7","LED8";
433	};
434};
435
436/* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
437&mcu_gpio0 {
438	status = "reserved";
439};
440
441&mcu_gpio_intr {
442	status = "reserved";
443};
444
445&sdhci0 {
446	status = "okay";
447	vmmc-supply = <&wlan_en>;
448	bus-width = <4>;
449	non-removable;
450	cap-power-off-card;
451	keep-power-in-suspend;
452	ti,driver-strength-ohm = <50>;
453
454	#address-cells = <1>;
455	#size-cells = <0>;
456	wlcore: wlcore@2 {
457		compatible = "ti,wl1837";
458		reg = <2>;
459		pinctrl-0 = <&main_wlan_pins_default>;
460		pinctrl-names = "default";
461		interrupt-parent = <&main_gpio0>;
462		interrupts = <46 IRQ_TYPE_EDGE_FALLING>;
463	};
464};
465
466/* SD/MMC */
467&sdhci1 {
468	bootph-all;
469	status = "okay";
470	vmmc-supply = <&vdd_mmc1>;
471	pinctrl-names = "default";
472	bus-width = <4>;
473	pinctrl-0 = <&main_mmc1_pins_default>;
474	ti,driver-strength-ohm = <50>;
475	disable-wp;
476};
477
478&serdes_ln_ctrl {
479	bootph-all;
480	idle-states = <AM64_SERDES0_LANE0_USB>;
481};
482
483&serdes_refclk {
484	bootph-all;
485};
486
487&serdes_wiz0 {
488	bootph-all;
489};
490
491&serdes0 {
492	bootph-all;
493	serdes0_usb_link: phy@0 {
494		bootph-all;
495		reg = <0>;
496		cdns,num-lanes = <1>;
497		#phy-cells = <0>;
498		cdns,phy-type = <PHY_TYPE_USB3>;
499		resets = <&serdes_wiz0 1>;
500	};
501};
502
503&usbss0 {
504	bootph-all;
505	ti,vbus-divider;
506};
507
508&usb0 {
509	bootph-all;
510	dr_mode = "host";
511	maximum-speed = "super-speed";
512	pinctrl-names = "default";
513	pinctrl-0 = <&main_usb0_pins_default>;
514	phys = <&serdes0_usb_link>;
515	phy-names = "cdns3,usb3-phy";
516};
517
518&cpsw3g {
519	pinctrl-names = "default";
520	pinctrl-0 = <&rgmii1_pins_default>, <&rgmii2_pins_default>;
521};
522
523&cpsw_port1 {
524	phy-mode = "rgmii-rxid";
525	phy-handle = <&cpsw3g_phy0>;
526};
527
528&cpsw_port2 {
529	phy-mode = "rgmii-rxid";
530	phy-handle = <&cpsw3g_phy1>;
531};
532
533&cpsw3g_mdio {
534	status = "okay";
535	pinctrl-names = "default";
536	pinctrl-0 = <&mdio1_pins_default>;
537
538	cpsw3g_phy0: ethernet-phy@0 {
539		reg = <0>;
540		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
541		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
542	};
543
544	cpsw3g_phy1: ethernet-phy@1 {
545		reg = <1>;
546		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
547		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
548	};
549};
550
551&ospi0 {
552	status = "okay";
553	pinctrl-names = "default";
554	pinctrl-0 = <&ospi0_pins_default>;
555
556	flash@0 {
557		compatible = "jedec,spi-nor";
558		reg = <0x0>;
559		spi-tx-bus-width = <8>;
560		spi-rx-bus-width = <8>;
561		spi-max-frequency = <25000000>;
562		cdns,tshsl-ns = <60>;
563		cdns,tsd2d-ns = <60>;
564		cdns,tchsh-ns = <60>;
565		cdns,tslch-ns = <60>;
566		cdns,read-delay = <4>;
567
568		partitions {
569			compatible = "fixed-partitions";
570			#address-cells = <1>;
571			#size-cells = <1>;
572
573			partition@0 {
574				label = "ospi.tiboot3";
575				reg = <0x0 0x100000>;
576			};
577
578			partition@100000 {
579				label = "ospi.tispl";
580				reg = <0x100000 0x200000>;
581			};
582
583			partition@300000 {
584				label = "ospi.u-boot";
585				reg = <0x300000 0x400000>;
586			};
587
588			partition@700000 {
589				label = "ospi.env";
590				reg = <0x700000 0x40000>;
591			};
592
593			partition@740000 {
594				label = "ospi.env.backup";
595				reg = <0x740000 0x40000>;
596			};
597
598			partition@800000 {
599				label = "ospi.rootfs";
600				reg = <0x800000 0x37c0000>;
601			};
602
603			partition@3fc0000 {
604				label = "ospi.phypattern";
605				reg = <0x3fc0000 0x40000>;
606			};
607		};
608	};
609};
610
611&mailbox0_cluster2 {
612	status = "okay";
613
614	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
615		ti,mbox-rx = <0 0 2>;
616		ti,mbox-tx = <1 0 2>;
617	};
618
619	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
620		ti,mbox-rx = <2 0 2>;
621		ti,mbox-tx = <3 0 2>;
622	};
623};
624
625&mailbox0_cluster4 {
626	status = "okay";
627
628	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
629		ti,mbox-rx = <0 0 2>;
630		ti,mbox-tx = <1 0 2>;
631	};
632
633	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
634		ti,mbox-rx = <2 0 2>;
635		ti,mbox-tx = <3 0 2>;
636	};
637};
638
639&mailbox0_cluster6 {
640	status = "okay";
641
642	mbox_m4_0: mbox-m4-0 {
643		ti,mbox-rx = <0 0 2>;
644		ti,mbox-tx = <1 0 2>;
645	};
646};
647
648&main_r5fss0_core0 {
649	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core0>;
650	memory-region = <&main_r5fss0_core0_dma_memory_region>,
651			<&main_r5fss0_core0_memory_region>;
652};
653
654&main_r5fss0_core1 {
655	mboxes = <&mailbox0_cluster2>, <&mbox_main_r5fss0_core1>;
656	memory-region = <&main_r5fss0_core1_dma_memory_region>,
657			<&main_r5fss0_core1_memory_region>;
658};
659
660&main_r5fss1_core0 {
661	mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core0>;
662	memory-region = <&main_r5fss1_core0_dma_memory_region>,
663			<&main_r5fss1_core0_memory_region>;
664};
665
666&main_r5fss1_core1 {
667	mboxes = <&mailbox0_cluster4>, <&mbox_main_r5fss1_core1>;
668	memory-region = <&main_r5fss1_core1_dma_memory_region>,
669			<&main_r5fss1_core1_memory_region>;
670};
671
672&ecap0 {
673	status = "okay";
674	/* PWM is available on Pin 1 of header J3 */
675	pinctrl-names = "default";
676	pinctrl-0 = <&main_ecap0_pins_default>;
677};
678