1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/net/ti-dp83867.h> 10#include "k3-am642.dtsi" 11 12/ { 13 compatible = "ti,am642-sk", "ti,am642"; 14 model = "Texas Instruments AM642 SK"; 15 16 chosen { 17 stdout-path = "serial2:115200n8"; 18 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; 19 }; 20 21 memory@80000000 { 22 device_type = "memory"; 23 /* 2G RAM */ 24 reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 25 26 }; 27 28 reserved-memory { 29 #address-cells = <2>; 30 #size-cells = <2>; 31 ranges; 32 33 secure_ddr: optee@9e800000 { 34 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 35 alignment = <0x1000>; 36 no-map; 37 }; 38 }; 39 40 vusb_main: fixed-regulator-vusb-main5v0 { 41 /* USB MAIN INPUT 5V DC */ 42 compatible = "regulator-fixed"; 43 regulator-name = "vusb_main5v0"; 44 regulator-min-microvolt = <5000000>; 45 regulator-max-microvolt = <5000000>; 46 regulator-always-on; 47 regulator-boot-on; 48 }; 49 50 vcc_3v3_sys: fixedregulator-vcc-3v3-sys { 51 /* output of LP8733xx */ 52 compatible = "regulator-fixed"; 53 regulator-name = "vcc_3v3_sys"; 54 regulator-min-microvolt = <3300000>; 55 regulator-max-microvolt = <3300000>; 56 vin-supply = <&vusb_main>; 57 regulator-always-on; 58 regulator-boot-on; 59 }; 60 61 vdd_mmc1: fixed-regulator-sd { 62 /* TPS2051BD */ 63 compatible = "regulator-fixed"; 64 regulator-name = "vdd_mmc1"; 65 regulator-min-microvolt = <3300000>; 66 regulator-max-microvolt = <3300000>; 67 regulator-boot-on; 68 enable-active-high; 69 vin-supply = <&vcc_3v3_sys>; 70 gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; 71 }; 72}; 73 74&main_pmx0 { 75 main_mmc1_pins_default: main-mmc1-pins-default { 76 pinctrl-single,pins = < 77 AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */ 78 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */ 79 AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */ 80 AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */ 81 AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */ 82 AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */ 83 AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */ 84 AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */ 85 >; 86 }; 87 88 main_i2c1_pins_default: main-i2c1-pins-default { 89 pinctrl-single,pins = < 90 AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ 91 AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ 92 >; 93 }; 94 95 mdio1_pins_default: mdio1-pins-default { 96 pinctrl-single,pins = < 97 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ 98 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ 99 >; 100 }; 101 102 rgmii1_pins_default: rgmii1-pins-default { 103 pinctrl-single,pins = < 104 AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */ 105 AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */ 106 AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */ 107 AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */ 108 AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */ 109 AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */ 110 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ 111 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ 112 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ 113 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ 114 AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ 115 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ 116 >; 117 }; 118 119 rgmii2_pins_default: rgmii2-pins-default { 120 pinctrl-single,pins = < 121 AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ 122 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ 123 AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ 124 AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ 125 AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ 126 AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ 127 AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ 128 AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ 129 AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ 130 AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ 131 AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ 132 AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ 133 >; 134 }; 135 136 ospi0_pins_default: ospi0-pins-default { 137 pinctrl-single,pins = < 138 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ 139 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ 140 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ 141 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ 142 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ 143 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ 144 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ 145 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ 146 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ 147 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ 148 AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ 149 >; 150 }; 151}; 152 153&mcu_uart0 { 154 status = "disabled"; 155}; 156 157&mcu_uart1 { 158 status = "disabled"; 159}; 160 161&main_uart1 { 162 /* main_uart1 is reserved for firmware usage */ 163 status = "reserved"; 164}; 165 166&main_uart2 { 167 status = "disabled"; 168}; 169 170&main_uart3 { 171 status = "disabled"; 172}; 173 174&main_uart4 { 175 status = "disabled"; 176}; 177 178&main_uart5 { 179 status = "disabled"; 180}; 181 182&main_uart6 { 183 status = "disabled"; 184}; 185 186&mcu_i2c0 { 187 status = "disabled"; 188}; 189 190&mcu_i2c1 { 191 status = "disabled"; 192}; 193 194&main_i2c1 { 195 pinctrl-names = "default"; 196 pinctrl-0 = <&main_i2c1_pins_default>; 197 clock-frequency = <400000>; 198 199 exp1: gpio@70 { 200 compatible = "nxp,pca9538"; 201 reg = <0x70>; 202 gpio-controller; 203 #gpio-cells = <2>; 204 gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", 205 "PRU_DETECT", "MMC1_SD_EN", 206 "VPP_LDO_EN", "RPI_PS_3V3_En", 207 "RPI_PS_5V0_En", "RPI_HAT_DETECT"; 208 }; 209}; 210 211&main_i2c3 { 212 status = "disabled"; 213}; 214 215&mcu_spi0 { 216 status = "disabled"; 217}; 218 219&mcu_spi1 { 220 status = "disabled"; 221}; 222 223/* mcu_gpio0 is reserved for mcu firmware usage */ 224&mcu_gpio0 { 225 status = "reserved"; 226}; 227 228&sdhci1 { 229 /* SD/MMC */ 230 vmmc-supply = <&vdd_mmc1>; 231 pinctrl-names = "default"; 232 bus-width = <4>; 233 pinctrl-0 = <&main_mmc1_pins_default>; 234 ti,driver-strength-ohm = <50>; 235 disable-wp; 236}; 237 238&cpsw3g { 239 pinctrl-names = "default"; 240 pinctrl-0 = <&mdio1_pins_default 241 &rgmii1_pins_default 242 &rgmii2_pins_default>; 243}; 244 245&cpsw_port1 { 246 phy-mode = "rgmii-rxid"; 247 phy-handle = <&cpsw3g_phy0>; 248}; 249 250&cpsw_port2 { 251 phy-mode = "rgmii-rxid"; 252 phy-handle = <&cpsw3g_phy1>; 253}; 254 255&cpsw3g_mdio { 256 cpsw3g_phy0: ethernet-phy@0 { 257 reg = <0>; 258 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 259 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 260 }; 261 262 cpsw3g_phy1: ethernet-phy@1 { 263 reg = <1>; 264 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 265 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 266 }; 267}; 268 269&tscadc0 { 270 status = "disabled"; 271}; 272 273&ospi0 { 274 pinctrl-names = "default"; 275 pinctrl-0 = <&ospi0_pins_default>; 276 277 flash@0{ 278 compatible = "jedec,spi-nor"; 279 reg = <0x0>; 280 spi-tx-bus-width = <8>; 281 spi-rx-bus-width = <8>; 282 spi-max-frequency = <25000000>; 283 cdns,tshsl-ns = <60>; 284 cdns,tsd2d-ns = <60>; 285 cdns,tchsh-ns = <60>; 286 cdns,tslch-ns = <60>; 287 cdns,read-delay = <4>; 288 #address-cells = <1>; 289 #size-cells = <1>; 290 }; 291}; 292 293&mailbox0_cluster2 { 294 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 295 ti,mbox-rx = <0 0 2>; 296 ti,mbox-tx = <1 0 2>; 297 }; 298 299 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 300 ti,mbox-rx = <2 0 2>; 301 ti,mbox-tx = <3 0 2>; 302 }; 303}; 304 305&mailbox0_cluster3 { 306 status = "disabled"; 307}; 308 309&mailbox0_cluster4 { 310 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 311 ti,mbox-rx = <0 0 2>; 312 ti,mbox-tx = <1 0 2>; 313 }; 314 315 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 316 ti,mbox-rx = <2 0 2>; 317 ti,mbox-tx = <3 0 2>; 318 }; 319}; 320 321&mailbox0_cluster5 { 322 status = "disabled"; 323}; 324 325&mailbox0_cluster6 { 326 mbox_m4_0: mbox-m4-0 { 327 ti,mbox-rx = <0 0 2>; 328 ti,mbox-tx = <1 0 2>; 329 }; 330}; 331 332&mailbox0_cluster7 { 333 status = "disabled"; 334}; 335