1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/mux/ti-serdes.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/net/ti-dp83867.h> 12#include "k3-am642.dtsi" 13 14/ { 15 compatible = "ti,am642-sk", "ti,am642"; 16 model = "Texas Instruments AM642 SK"; 17 18 chosen { 19 stdout-path = "serial2:115200n8"; 20 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; 21 }; 22 23 memory@80000000 { 24 device_type = "memory"; 25 /* 2G RAM */ 26 reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 27 28 }; 29 30 reserved-memory { 31 #address-cells = <2>; 32 #size-cells = <2>; 33 ranges; 34 35 secure_ddr: optee@9e800000 { 36 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 37 alignment = <0x1000>; 38 no-map; 39 }; 40 41 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 42 compatible = "shared-dma-pool"; 43 reg = <0x00 0xa0000000 0x00 0x100000>; 44 no-map; 45 }; 46 47 main_r5fss0_core0_memory_region: r5f-memory@a0100000 { 48 compatible = "shared-dma-pool"; 49 reg = <0x00 0xa0100000 0x00 0xf00000>; 50 no-map; 51 }; 52 53 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 54 compatible = "shared-dma-pool"; 55 reg = <0x00 0xa1000000 0x00 0x100000>; 56 no-map; 57 }; 58 59 main_r5fss0_core1_memory_region: r5f-memory@a1100000 { 60 compatible = "shared-dma-pool"; 61 reg = <0x00 0xa1100000 0x00 0xf00000>; 62 no-map; 63 }; 64 65 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { 66 compatible = "shared-dma-pool"; 67 reg = <0x00 0xa2000000 0x00 0x100000>; 68 no-map; 69 }; 70 71 main_r5fss1_core0_memory_region: r5f-memory@a2100000 { 72 compatible = "shared-dma-pool"; 73 reg = <0x00 0xa2100000 0x00 0xf00000>; 74 no-map; 75 }; 76 77 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { 78 compatible = "shared-dma-pool"; 79 reg = <0x00 0xa3000000 0x00 0x100000>; 80 no-map; 81 }; 82 83 main_r5fss1_core1_memory_region: r5f-memory@a3100000 { 84 compatible = "shared-dma-pool"; 85 reg = <0x00 0xa3100000 0x00 0xf00000>; 86 no-map; 87 }; 88 89 rtos_ipc_memory_region: ipc-memories@a5000000 { 90 reg = <0x00 0xa5000000 0x00 0x00800000>; 91 alignment = <0x1000>; 92 no-map; 93 }; 94 }; 95 96 vusb_main: fixed-regulator-vusb-main5v0 { 97 /* USB MAIN INPUT 5V DC */ 98 compatible = "regulator-fixed"; 99 regulator-name = "vusb_main5v0"; 100 regulator-min-microvolt = <5000000>; 101 regulator-max-microvolt = <5000000>; 102 regulator-always-on; 103 regulator-boot-on; 104 }; 105 106 vcc_3v3_sys: fixedregulator-vcc-3v3-sys { 107 /* output of LP8733xx */ 108 compatible = "regulator-fixed"; 109 regulator-name = "vcc_3v3_sys"; 110 regulator-min-microvolt = <3300000>; 111 regulator-max-microvolt = <3300000>; 112 vin-supply = <&vusb_main>; 113 regulator-always-on; 114 regulator-boot-on; 115 }; 116 117 vdd_mmc1: fixed-regulator-sd { 118 /* TPS2051BD */ 119 compatible = "regulator-fixed"; 120 regulator-name = "vdd_mmc1"; 121 regulator-min-microvolt = <3300000>; 122 regulator-max-microvolt = <3300000>; 123 regulator-boot-on; 124 enable-active-high; 125 vin-supply = <&vcc_3v3_sys>; 126 gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; 127 }; 128 129 com8_ls_en: regulator-1 { 130 compatible = "regulator-fixed"; 131 regulator-name = "com8_ls_en"; 132 regulator-min-microvolt = <3300000>; 133 regulator-max-microvolt = <3300000>; 134 regulator-always-on; 135 regulator-boot-on; 136 pinctrl-0 = <&main_com8_ls_en_pins_default>; 137 pinctrl-names = "default"; 138 gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>; 139 }; 140 141 wlan_en: regulator-2 { 142 /* output of SN74AVC4T245RSVR */ 143 compatible = "regulator-fixed"; 144 regulator-name = "wlan_en"; 145 regulator-min-microvolt = <1800000>; 146 regulator-max-microvolt = <1800000>; 147 enable-active-high; 148 pinctrl-0 = <&main_wlan_en_pins_default>; 149 pinctrl-names = "default"; 150 vin-supply = <&com8_ls_en>; 151 gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>; 152 }; 153}; 154 155&main_pmx0 { 156 main_mmc1_pins_default: main-mmc1-pins-default { 157 pinctrl-single,pins = < 158 AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */ 159 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */ 160 AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */ 161 AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */ 162 AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */ 163 AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */ 164 AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */ 165 AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */ 166 >; 167 }; 168 169 main_uart0_pins_default: main-uart0-pins-default { 170 pinctrl-single,pins = < 171 AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ 172 AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ 173 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ 174 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ 175 >; 176 }; 177 178 main_usb0_pins_default: main-usb0-pins-default { 179 pinctrl-single,pins = < 180 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ 181 >; 182 }; 183 184 main_i2c1_pins_default: main-i2c1-pins-default { 185 pinctrl-single,pins = < 186 AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ 187 AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ 188 >; 189 }; 190 191 mdio1_pins_default: mdio1-pins-default { 192 pinctrl-single,pins = < 193 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ 194 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ 195 >; 196 }; 197 198 rgmii1_pins_default: rgmii1-pins-default { 199 pinctrl-single,pins = < 200 AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */ 201 AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */ 202 AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */ 203 AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */ 204 AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */ 205 AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */ 206 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ 207 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ 208 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ 209 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ 210 AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ 211 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ 212 >; 213 }; 214 215 rgmii2_pins_default: rgmii2-pins-default { 216 pinctrl-single,pins = < 217 AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ 218 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ 219 AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ 220 AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ 221 AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ 222 AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ 223 AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ 224 AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ 225 AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ 226 AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ 227 AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ 228 AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ 229 >; 230 }; 231 232 ospi0_pins_default: ospi0-pins-default { 233 pinctrl-single,pins = < 234 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ 235 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ 236 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ 237 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ 238 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ 239 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ 240 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ 241 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ 242 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ 243 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ 244 AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ 245 >; 246 }; 247 248 main_ecap0_pins_default: main-ecap0-pins-default { 249 pinctrl-single,pins = < 250 AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ 251 >; 252 }; 253 main_wlan_en_pins_default: main-wlan-en-pins-default { 254 pinctrl-single,pins = < 255 AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */ 256 >; 257 }; 258 259 main_com8_ls_en_pins_default: main-com8-ls-en-pins-default { 260 pinctrl-single,pins = < 261 AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */ 262 >; 263 }; 264 265 main_wlan_pins_default: main-wlan-pins-default { 266 pinctrl-single,pins = < 267 AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */ 268 >; 269 }; 270}; 271 272&mcu_uart0 { 273 status = "disabled"; 274}; 275 276&mcu_uart1 { 277 status = "disabled"; 278}; 279 280&main_uart0 { 281 pinctrl-names = "default"; 282 pinctrl-0 = <&main_uart0_pins_default>; 283}; 284 285&main_uart1 { 286 /* main_uart1 is reserved for firmware usage */ 287 status = "reserved"; 288}; 289 290&main_uart2 { 291 status = "disabled"; 292}; 293 294&main_uart3 { 295 status = "disabled"; 296}; 297 298&main_uart4 { 299 status = "disabled"; 300}; 301 302&main_uart5 { 303 status = "disabled"; 304}; 305 306&main_uart6 { 307 status = "disabled"; 308}; 309 310&mcu_i2c0 { 311 status = "disabled"; 312}; 313 314&mcu_i2c1 { 315 status = "disabled"; 316}; 317 318&main_i2c1 { 319 pinctrl-names = "default"; 320 pinctrl-0 = <&main_i2c1_pins_default>; 321 clock-frequency = <400000>; 322 323 exp1: gpio@70 { 324 compatible = "nxp,pca9538"; 325 reg = <0x70>; 326 gpio-controller; 327 #gpio-cells = <2>; 328 gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", 329 "PRU_DETECT", "MMC1_SD_EN", 330 "VPP_LDO_EN", "RPI_PS_3V3_En", 331 "RPI_PS_5V0_En", "RPI_HAT_DETECT"; 332 }; 333}; 334 335&main_i2c3 { 336 status = "disabled"; 337}; 338 339&mcu_spi0 { 340 status = "disabled"; 341}; 342 343&mcu_spi1 { 344 status = "disabled"; 345}; 346 347/* mcu_gpio0 is reserved for mcu firmware usage */ 348&mcu_gpio0 { 349 status = "reserved"; 350}; 351 352&sdhci0 { 353 vmmc-supply = <&wlan_en>; 354 bus-width = <4>; 355 non-removable; 356 cap-power-off-card; 357 keep-power-in-suspend; 358 ti,driver-strength-ohm = <50>; 359 360 #address-cells = <1>; 361 #size-cells = <0>; 362 wlcore: wlcore@2 { 363 compatible = "ti,wl1837"; 364 reg = <2>; 365 pinctrl-0 = <&main_wlan_pins_default>; 366 pinctrl-names = "default"; 367 interrupt-parent = <&main_gpio0>; 368 interrupts = <46 IRQ_TYPE_EDGE_FALLING>; 369 }; 370}; 371 372&sdhci1 { 373 /* SD/MMC */ 374 vmmc-supply = <&vdd_mmc1>; 375 pinctrl-names = "default"; 376 bus-width = <4>; 377 pinctrl-0 = <&main_mmc1_pins_default>; 378 ti,driver-strength-ohm = <50>; 379 disable-wp; 380}; 381 382&serdes_ln_ctrl { 383 idle-states = <AM64_SERDES0_LANE0_USB>; 384}; 385 386&serdes0 { 387 serdes0_usb_link: phy@0 { 388 reg = <0>; 389 cdns,num-lanes = <1>; 390 #phy-cells = <0>; 391 cdns,phy-type = <PHY_TYPE_USB3>; 392 resets = <&serdes_wiz0 1>; 393 }; 394}; 395 396&usbss0 { 397 ti,vbus-divider; 398}; 399 400&usb0 { 401 dr_mode = "host"; 402 maximum-speed = "super-speed"; 403 pinctrl-names = "default"; 404 pinctrl-0 = <&main_usb0_pins_default>; 405 phys = <&serdes0_usb_link>; 406 phy-names = "cdns3,usb3-phy"; 407}; 408 409&cpsw3g { 410 pinctrl-names = "default"; 411 pinctrl-0 = <&mdio1_pins_default 412 &rgmii1_pins_default 413 &rgmii2_pins_default>; 414}; 415 416&cpsw_port1 { 417 phy-mode = "rgmii-rxid"; 418 phy-handle = <&cpsw3g_phy0>; 419}; 420 421&cpsw_port2 { 422 phy-mode = "rgmii-rxid"; 423 phy-handle = <&cpsw3g_phy1>; 424}; 425 426&cpsw3g_mdio { 427 cpsw3g_phy0: ethernet-phy@0 { 428 reg = <0>; 429 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 430 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 431 }; 432 433 cpsw3g_phy1: ethernet-phy@1 { 434 reg = <1>; 435 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 436 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 437 }; 438}; 439 440&tscadc0 { 441 status = "disabled"; 442}; 443 444&ospi0 { 445 pinctrl-names = "default"; 446 pinctrl-0 = <&ospi0_pins_default>; 447 448 flash@0 { 449 compatible = "jedec,spi-nor"; 450 reg = <0x0>; 451 spi-tx-bus-width = <8>; 452 spi-rx-bus-width = <8>; 453 spi-max-frequency = <25000000>; 454 cdns,tshsl-ns = <60>; 455 cdns,tsd2d-ns = <60>; 456 cdns,tchsh-ns = <60>; 457 cdns,tslch-ns = <60>; 458 cdns,read-delay = <4>; 459 }; 460}; 461 462&mailbox0_cluster2 { 463 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 464 ti,mbox-rx = <0 0 2>; 465 ti,mbox-tx = <1 0 2>; 466 }; 467 468 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 469 ti,mbox-rx = <2 0 2>; 470 ti,mbox-tx = <3 0 2>; 471 }; 472}; 473 474&mailbox0_cluster3 { 475 status = "disabled"; 476}; 477 478&mailbox0_cluster4 { 479 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 480 ti,mbox-rx = <0 0 2>; 481 ti,mbox-tx = <1 0 2>; 482 }; 483 484 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 485 ti,mbox-rx = <2 0 2>; 486 ti,mbox-tx = <3 0 2>; 487 }; 488}; 489 490&mailbox0_cluster5 { 491 status = "disabled"; 492}; 493 494&mailbox0_cluster6 { 495 mbox_m4_0: mbox-m4-0 { 496 ti,mbox-rx = <0 0 2>; 497 ti,mbox-tx = <1 0 2>; 498 }; 499}; 500 501&mailbox0_cluster7 { 502 status = "disabled"; 503}; 504 505&main_r5fss0_core0 { 506 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; 507 memory-region = <&main_r5fss0_core0_dma_memory_region>, 508 <&main_r5fss0_core0_memory_region>; 509}; 510 511&main_r5fss0_core1 { 512 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; 513 memory-region = <&main_r5fss0_core1_dma_memory_region>, 514 <&main_r5fss0_core1_memory_region>; 515}; 516 517&main_r5fss1_core0 { 518 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; 519 memory-region = <&main_r5fss1_core0_dma_memory_region>, 520 <&main_r5fss1_core0_memory_region>; 521}; 522 523&main_r5fss1_core1 { 524 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; 525 memory-region = <&main_r5fss1_core1_dma_memory_region>, 526 <&main_r5fss1_core1_memory_region>; 527}; 528 529&pcie0_rc { 530 status = "disabled"; 531}; 532 533&pcie0_ep { 534 status = "disabled"; 535}; 536 537&ecap0 { 538 /* PWM is available on Pin 1 of header J3 */ 539 pinctrl-names = "default"; 540 pinctrl-0 = <&main_ecap0_pins_default>; 541}; 542 543&ecap1 { 544 status = "disabled"; 545}; 546 547&ecap2 { 548 status = "disabled"; 549}; 550 551&epwm0 { 552 status = "disabled"; 553}; 554 555&epwm1 { 556 status = "disabled"; 557}; 558 559&epwm2 { 560 status = "disabled"; 561}; 562 563&epwm3 { 564 status = "disabled"; 565}; 566 567&epwm4 { 568 /* 569 * EPWM4_A, EPWM4_B is available on Pin 32 and 33 on J4 (RPi hat) 570 * But RPi Hat will be used for other use cases, so marking epwm4 as disabled. 571 */ 572 status = "disabled"; 573}; 574 575&epwm5 { 576 /* 577 * EPWM5_A, EPWM5_B is available on Pin 29 and 31 on J4 (RPi hat) 578 * But RPi Hat will be used for other use cases, so marking epwm5 as disabled. 579 */ 580 status = "disabled"; 581}; 582 583&epwm6 { 584 status = "disabled"; 585}; 586 587&epwm7 { 588 status = "disabled"; 589}; 590 591&epwm8 { 592 status = "disabled"; 593}; 594 595&icssg0_mdio { 596 status = "disabled"; 597}; 598 599&icssg1_mdio { 600 status = "disabled"; 601}; 602 603&main_mcan0 { 604 status = "disabled"; 605}; 606 607&main_mcan1 { 608 status = "disabled"; 609}; 610