1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/phy/phy.h> 9#include <dt-bindings/mux/ti-serdes.h> 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/net/ti-dp83867.h> 13#include "k3-am642.dtsi" 14 15/ { 16 compatible = "ti,am642-evm", "ti,am642"; 17 model = "Texas Instruments AM642 EVM"; 18 19 chosen { 20 stdout-path = "serial2:115200n8"; 21 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; 22 }; 23 24 memory@80000000 { 25 device_type = "memory"; 26 /* 2G RAM */ 27 reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 28 29 }; 30 31 reserved-memory { 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 36 secure_ddr: optee@9e800000 { 37 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 38 alignment = <0x1000>; 39 no-map; 40 }; 41 42 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 43 compatible = "shared-dma-pool"; 44 reg = <0x00 0xa0000000 0x00 0x100000>; 45 no-map; 46 }; 47 48 main_r5fss0_core0_memory_region: r5f-memory@a0100000 { 49 compatible = "shared-dma-pool"; 50 reg = <0x00 0xa0100000 0x00 0xf00000>; 51 no-map; 52 }; 53 54 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 55 compatible = "shared-dma-pool"; 56 reg = <0x00 0xa1000000 0x00 0x100000>; 57 no-map; 58 }; 59 60 main_r5fss0_core1_memory_region: r5f-memory@a1100000 { 61 compatible = "shared-dma-pool"; 62 reg = <0x00 0xa1100000 0x00 0xf00000>; 63 no-map; 64 }; 65 66 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { 67 compatible = "shared-dma-pool"; 68 reg = <0x00 0xa2000000 0x00 0x100000>; 69 no-map; 70 }; 71 72 main_r5fss1_core0_memory_region: r5f-memory@a2100000 { 73 compatible = "shared-dma-pool"; 74 reg = <0x00 0xa2100000 0x00 0xf00000>; 75 no-map; 76 }; 77 78 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { 79 compatible = "shared-dma-pool"; 80 reg = <0x00 0xa3000000 0x00 0x100000>; 81 no-map; 82 }; 83 84 main_r5fss1_core1_memory_region: r5f-memory@a3100000 { 85 compatible = "shared-dma-pool"; 86 reg = <0x00 0xa3100000 0x00 0xf00000>; 87 no-map; 88 }; 89 90 rtos_ipc_memory_region: ipc-memories@a5000000 { 91 reg = <0x00 0xa5000000 0x00 0x00800000>; 92 alignment = <0x1000>; 93 no-map; 94 }; 95 }; 96 97 evm_12v0: fixedregulator-evm12v0 { 98 /* main DC jack */ 99 compatible = "regulator-fixed"; 100 regulator-name = "evm_12v0"; 101 regulator-min-microvolt = <12000000>; 102 regulator-max-microvolt = <12000000>; 103 regulator-always-on; 104 regulator-boot-on; 105 }; 106 107 vsys_5v0: fixedregulator-vsys5v0 { 108 /* output of LM5140 */ 109 compatible = "regulator-fixed"; 110 regulator-name = "vsys_5v0"; 111 regulator-min-microvolt = <5000000>; 112 regulator-max-microvolt = <5000000>; 113 vin-supply = <&evm_12v0>; 114 regulator-always-on; 115 regulator-boot-on; 116 }; 117 118 vsys_3v3: fixedregulator-vsys3v3 { 119 /* output of LM5140 */ 120 compatible = "regulator-fixed"; 121 regulator-name = "vsys_3v3"; 122 regulator-min-microvolt = <3300000>; 123 regulator-max-microvolt = <3300000>; 124 vin-supply = <&evm_12v0>; 125 regulator-always-on; 126 regulator-boot-on; 127 }; 128 129 vdd_mmc1: fixed-regulator-sd { 130 /* TPS2051BD */ 131 compatible = "regulator-fixed"; 132 regulator-name = "vdd_mmc1"; 133 regulator-min-microvolt = <3300000>; 134 regulator-max-microvolt = <3300000>; 135 regulator-boot-on; 136 enable-active-high; 137 vin-supply = <&vsys_3v3>; 138 gpio = <&exp1 6 GPIO_ACTIVE_HIGH>; 139 }; 140 141 vddb: fixedregulator-vddb { 142 compatible = "regulator-fixed"; 143 regulator-name = "vddb_3v3_display"; 144 regulator-min-microvolt = <3300000>; 145 regulator-max-microvolt = <3300000>; 146 vin-supply = <&vsys_3v3>; 147 regulator-always-on; 148 regulator-boot-on; 149 }; 150 151 leds { 152 compatible = "gpio-leds"; 153 154 led-0 { 155 label = "am64-evm:red:heartbeat"; 156 gpios = <&exp1 16 GPIO_ACTIVE_HIGH>; 157 linux,default-trigger = "heartbeat"; 158 function = LED_FUNCTION_HEARTBEAT; 159 default-state = "off"; 160 }; 161 }; 162 163 mdio_mux: mux-controller { 164 compatible = "gpio-mux"; 165 #mux-control-cells = <0>; 166 167 mux-gpios = <&exp1 12 GPIO_ACTIVE_HIGH>; 168 }; 169 170 mdio-mux-1 { 171 compatible = "mdio-mux-multiplexer"; 172 mux-controls = <&mdio_mux>; 173 mdio-parent-bus = <&cpsw3g_mdio>; 174 #address-cells = <1>; 175 #size-cells = <0>; 176 177 mdio@1 { 178 reg = <0x1>; 179 #address-cells = <1>; 180 #size-cells = <0>; 181 182 cpsw3g_phy3: ethernet-phy@3 { 183 reg = <3>; 184 }; 185 }; 186 }; 187}; 188 189&main_pmx0 { 190 main_mmc1_pins_default: main-mmc1-pins-default { 191 pinctrl-single,pins = < 192 AM64X_IOPAD(0x0294, PIN_INPUT_PULLUP, 0) /* (J19) MMC1_CMD */ 193 AM64X_IOPAD(0x028c, PIN_INPUT_PULLDOWN, 0) /* (L20) MMC1_CLK */ 194 AM64X_IOPAD(0x0288, PIN_INPUT_PULLUP, 0) /* (K21) MMC1_DAT0 */ 195 AM64X_IOPAD(0x0284, PIN_INPUT_PULLUP, 0) /* (L21) MMC1_DAT1 */ 196 AM64X_IOPAD(0x0280, PIN_INPUT_PULLUP, 0) /* (K19) MMC1_DAT2 */ 197 AM64X_IOPAD(0x027c, PIN_INPUT_PULLUP, 0) /* (K18) MMC1_DAT3 */ 198 AM64X_IOPAD(0x0298, PIN_INPUT_PULLUP, 0) /* (D19) MMC1_SDCD */ 199 AM64X_IOPAD(0x029c, PIN_INPUT, 0) /* (C20) MMC1_SDWP */ 200 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* MMC1_CLKLB */ 201 >; 202 }; 203 204 main_uart0_pins_default: main-uart0-pins-default { 205 pinctrl-single,pins = < 206 AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ 207 AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ 208 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ 209 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ 210 >; 211 }; 212 213 main_spi0_pins_default: main-spi0-pins-default { 214 pinctrl-single,pins = < 215 AM64X_IOPAD(0x0210, PIN_INPUT, 0) /* (D13) SPI0_CLK */ 216 AM64X_IOPAD(0x0208, PIN_OUTPUT, 0) /* (D12) SPI0_CS0 */ 217 AM64X_IOPAD(0x0214, PIN_OUTPUT, 0) /* (A13) SPI0_D0 */ 218 AM64X_IOPAD(0x0218, PIN_INPUT, 0) /* (A14) SPI0_D1 */ 219 >; 220 }; 221 222 main_i2c1_pins_default: main-i2c1-pins-default { 223 pinctrl-single,pins = < 224 AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ 225 AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ 226 >; 227 }; 228 229 mdio1_pins_default: mdio1-pins-default { 230 pinctrl-single,pins = < 231 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ 232 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ 233 >; 234 }; 235 236 rgmii1_pins_default: rgmii1-pins-default { 237 pinctrl-single,pins = < 238 AM64X_IOPAD(0x01cc, PIN_INPUT, 4) /* (W5) PRG0_PRU1_GPO7.RGMII1_RD0 */ 239 AM64X_IOPAD(0x01d4, PIN_INPUT, 4) /* (Y5) PRG0_PRU1_GPO9.RGMII1_RD1 */ 240 AM64X_IOPAD(0x01d8, PIN_INPUT, 4) /* (V6) PRG0_PRU1_GPO10.RGMII1_RD2 */ 241 AM64X_IOPAD(0x01f4, PIN_INPUT, 4) /* (V5) PRG0_PRU1_GPO17.RGMII1_RD3 */ 242 AM64X_IOPAD(0x0188, PIN_INPUT, 4) /* (AA5) PRG0_PRU0_GPO10.RGMII1_RXC */ 243 AM64X_IOPAD(0x0184, PIN_INPUT, 4) /* (W6) PRG0_PRU0_GPO9.RGMII1_RX_CTL */ 244 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ 245 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ 246 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ 247 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ 248 AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ 249 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ 250 >; 251 }; 252 253 rgmii2_pins_default: rgmii2-pins-default { 254 pinctrl-single,pins = < 255 AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ 256 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ 257 AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ 258 AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ 259 AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ 260 AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ 261 AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ 262 AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ 263 AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ 264 AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ 265 AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ 266 AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ 267 >; 268 }; 269 270 main_usb0_pins_default: main-usb0-pins-default { 271 pinctrl-single,pins = < 272 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ 273 >; 274 }; 275 276 ospi0_pins_default: ospi0-pins-default { 277 pinctrl-single,pins = < 278 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ 279 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ 280 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ 281 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ 282 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ 283 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ 284 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ 285 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ 286 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ 287 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ 288 AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ 289 >; 290 }; 291 292 main_ecap0_pins_default: main-ecap0-pins-default { 293 pinctrl-single,pins = < 294 AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ 295 >; 296 }; 297}; 298 299&main_uart0 { 300 pinctrl-names = "default"; 301 pinctrl-0 = <&main_uart0_pins_default>; 302}; 303 304/* main_uart1 is reserved for firmware usage */ 305&main_uart1 { 306 status = "reserved"; 307}; 308 309&main_uart2 { 310 status = "disabled"; 311}; 312 313&main_uart3 { 314 status = "disabled"; 315}; 316 317&main_uart4 { 318 status = "disabled"; 319}; 320 321&main_uart5 { 322 status = "disabled"; 323}; 324 325&main_uart6 { 326 status = "disabled"; 327}; 328 329&mcu_uart0 { 330 status = "disabled"; 331}; 332 333&mcu_uart1 { 334 status = "disabled"; 335}; 336 337&main_i2c1 { 338 pinctrl-names = "default"; 339 pinctrl-0 = <&main_i2c1_pins_default>; 340 clock-frequency = <400000>; 341 342 exp1: gpio@22 { 343 compatible = "ti,tca6424"; 344 reg = <0x22>; 345 gpio-controller; 346 #gpio-cells = <2>; 347 gpio-line-names = "GPIO_eMMC_RSTn", "CAN_MUX_SEL", 348 "GPIO_CPSW1_RST", "GPIO_RGMII1_RST", 349 "GPIO_RGMII2_RST", "GPIO_PCIe_RST_OUT", 350 "MMC1_SD_EN", "FSI_FET_SEL", 351 "MCAN0_STB_3V3", "MCAN1_STB_3V3", 352 "CPSW_FET_SEL", "CPSW_FET2_SEL", 353 "PRG1_RGMII2_FET_SEL", "TEST_GPIO2", 354 "GPIO_OLED_RESETn", "VPP_LDO_EN", 355 "TEST_LED1", "TP92", "TP90", "TP88", 356 "TP87", "TP86", "TP89", "TP91"; 357 }; 358 359 /* osd9616p0899-10 */ 360 display@3c { 361 compatible = "solomon,ssd1306fb-i2c"; 362 reg = <0x3c>; 363 reset-gpios = <&exp1 14 GPIO_ACTIVE_LOW>; 364 vbat-supply = <&vddb>; 365 solomon,height = <16>; 366 solomon,width = <96>; 367 solomon,com-seq; 368 solomon,com-invdir; 369 solomon,page-offset = <0>; 370 solomon,prechargep1 = <2>; 371 solomon,prechargep2 = <13>; 372 }; 373}; 374 375/* mcu_gpio0 is reserved for mcu firmware usage */ 376&mcu_gpio0 { 377 status = "reserved"; 378}; 379 380&mcu_i2c0 { 381 status = "disabled"; 382}; 383 384&mcu_i2c1 { 385 status = "disabled"; 386}; 387 388&mcu_spi0 { 389 status = "disabled"; 390}; 391 392&mcu_spi1 { 393 status = "disabled"; 394}; 395 396&main_spi0 { 397 pinctrl-names = "default"; 398 pinctrl-0 = <&main_spi0_pins_default>; 399 ti,pindir-d0-out-d1-in; 400 eeprom@0 { 401 compatible = "microchip,93lc46b"; 402 reg = <0>; 403 spi-max-frequency = <1000000>; 404 spi-cs-high; 405 data-size = <16>; 406 }; 407}; 408 409&sdhci0 { 410 /* emmc */ 411 bus-width = <8>; 412 non-removable; 413 ti,driver-strength-ohm = <50>; 414 disable-wp; 415}; 416 417&sdhci1 { 418 /* SD/MMC */ 419 vmmc-supply = <&vdd_mmc1>; 420 pinctrl-names = "default"; 421 bus-width = <4>; 422 pinctrl-0 = <&main_mmc1_pins_default>; 423 ti,driver-strength-ohm = <50>; 424 disable-wp; 425}; 426 427&usbss0 { 428 ti,vbus-divider; 429 ti,usb2-only; 430}; 431 432&usb0 { 433 dr_mode = "otg"; 434 maximum-speed = "high-speed"; 435 pinctrl-names = "default"; 436 pinctrl-0 = <&main_usb0_pins_default>; 437}; 438 439&cpsw3g { 440 pinctrl-names = "default"; 441 pinctrl-0 = <&mdio1_pins_default 442 &rgmii1_pins_default 443 &rgmii2_pins_default>; 444}; 445 446&cpsw_port1 { 447 phy-mode = "rgmii-rxid"; 448 phy-handle = <&cpsw3g_phy0>; 449}; 450 451&cpsw_port2 { 452 phy-mode = "rgmii-rxid"; 453 phy-handle = <&cpsw3g_phy3>; 454}; 455 456&cpsw3g_mdio { 457 cpsw3g_phy0: ethernet-phy@0 { 458 reg = <0>; 459 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 460 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 461 }; 462}; 463 464&tscadc0 { 465 /* ADC is reserved for R5 usage */ 466 status = "reserved"; 467}; 468 469&ospi0 { 470 pinctrl-names = "default"; 471 pinctrl-0 = <&ospi0_pins_default>; 472 473 flash@0{ 474 compatible = "jedec,spi-nor"; 475 reg = <0x0>; 476 spi-tx-bus-width = <8>; 477 spi-rx-bus-width = <8>; 478 spi-max-frequency = <25000000>; 479 cdns,tshsl-ns = <60>; 480 cdns,tsd2d-ns = <60>; 481 cdns,tchsh-ns = <60>; 482 cdns,tslch-ns = <60>; 483 cdns,read-delay = <4>; 484 #address-cells = <1>; 485 #size-cells = <1>; 486 }; 487}; 488 489&mailbox0_cluster2 { 490 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 491 ti,mbox-rx = <0 0 2>; 492 ti,mbox-tx = <1 0 2>; 493 }; 494 495 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 496 ti,mbox-rx = <2 0 2>; 497 ti,mbox-tx = <3 0 2>; 498 }; 499}; 500 501&mailbox0_cluster3 { 502 status = "disabled"; 503}; 504 505&mailbox0_cluster4 { 506 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 507 ti,mbox-rx = <0 0 2>; 508 ti,mbox-tx = <1 0 2>; 509 }; 510 511 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 512 ti,mbox-rx = <2 0 2>; 513 ti,mbox-tx = <3 0 2>; 514 }; 515}; 516 517&mailbox0_cluster5 { 518 status = "disabled"; 519}; 520 521&mailbox0_cluster6 { 522 mbox_m4_0: mbox-m4-0 { 523 ti,mbox-rx = <0 0 2>; 524 ti,mbox-tx = <1 0 2>; 525 }; 526}; 527 528&mailbox0_cluster7 { 529 status = "disabled"; 530}; 531 532&main_r5fss0_core0 { 533 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; 534 memory-region = <&main_r5fss0_core0_dma_memory_region>, 535 <&main_r5fss0_core0_memory_region>; 536}; 537 538&main_r5fss0_core1 { 539 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; 540 memory-region = <&main_r5fss0_core1_dma_memory_region>, 541 <&main_r5fss0_core1_memory_region>; 542}; 543 544&main_r5fss1_core0 { 545 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; 546 memory-region = <&main_r5fss1_core0_dma_memory_region>, 547 <&main_r5fss1_core0_memory_region>; 548}; 549 550&main_r5fss1_core1 { 551 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; 552 memory-region = <&main_r5fss1_core1_dma_memory_region>, 553 <&main_r5fss1_core1_memory_region>; 554}; 555 556&serdes_ln_ctrl { 557 idle-states = <AM64_SERDES0_LANE0_PCIE0>; 558}; 559 560&serdes0 { 561 serdes0_pcie_link: phy@0 { 562 reg = <0>; 563 cdns,num-lanes = <1>; 564 #phy-cells = <0>; 565 cdns,phy-type = <PHY_TYPE_PCIE>; 566 resets = <&serdes_wiz0 1>; 567 }; 568}; 569 570&pcie0_rc { 571 reset-gpios = <&exp1 5 GPIO_ACTIVE_HIGH>; 572 phys = <&serdes0_pcie_link>; 573 phy-names = "pcie-phy"; 574 num-lanes = <1>; 575}; 576 577&pcie0_ep { 578 phys = <&serdes0_pcie_link>; 579 phy-names = "pcie-phy"; 580 num-lanes = <1>; 581 status = "disabled"; 582}; 583 584&ecap0 { 585 /* PWM is available on Pin 1 of header J12 */ 586 pinctrl-names = "default"; 587 pinctrl-0 = <&main_ecap0_pins_default>; 588}; 589 590&ecap1 { 591 status = "disabled"; 592}; 593 594&ecap2 { 595 status = "disabled"; 596}; 597 598&epwm0 { 599 status = "disabled"; 600}; 601 602&epwm1 { 603 status = "disabled"; 604}; 605 606&epwm2 { 607 status = "disabled"; 608}; 609 610&epwm3 { 611 status = "disabled"; 612}; 613 614&epwm4 { 615 status = "disabled"; 616}; 617 618&epwm5 { 619 status = "disabled"; 620}; 621 622&epwm6 { 623 status = "disabled"; 624}; 625 626&epwm7 { 627 status = "disabled"; 628}; 629 630&epwm8 { 631 status = "disabled"; 632}; 633