1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM64 SoC Family MCU Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu { 9 mcu_uart0: serial@4a00000 { 10 compatible = "ti,am64-uart", "ti,am654-uart"; 11 reg = <0x00 0x04a00000 0x00 0x100>; 12 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 13 current-speed = <115200>; 14 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 15 clocks = <&k3_clks 149 0>; 16 clock-names = "fclk"; 17 status = "disabled"; 18 }; 19 20 mcu_uart1: serial@4a10000 { 21 compatible = "ti,am64-uart", "ti,am654-uart"; 22 reg = <0x00 0x04a10000 0x00 0x100>; 23 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 24 current-speed = <115200>; 25 power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>; 26 clocks = <&k3_clks 160 0>; 27 clock-names = "fclk"; 28 status = "disabled"; 29 }; 30 31 mcu_i2c0: i2c@4900000 { 32 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 33 reg = <0x00 0x04900000 0x00 0x100>; 34 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 35 #address-cells = <1>; 36 #size-cells = <0>; 37 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 38 clocks = <&k3_clks 106 2>; 39 clock-names = "fck"; 40 status = "disabled"; 41 }; 42 43 mcu_i2c1: i2c@4910000 { 44 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 45 reg = <0x00 0x04910000 0x00 0x100>; 46 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 47 #address-cells = <1>; 48 #size-cells = <0>; 49 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>; 50 clocks = <&k3_clks 107 2>; 51 clock-names = "fck"; 52 status = "disabled"; 53 }; 54 55 mcu_spi0: spi@4b00000 { 56 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 57 reg = <0x00 0x04b00000 0x00 0x400>; 58 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 59 #address-cells = <1>; 60 #size-cells = <0>; 61 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 62 clocks = <&k3_clks 147 0>; 63 status = "disabled"; 64 }; 65 66 mcu_spi1: spi@4b10000 { 67 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 68 reg = <0x00 0x04b10000 0x00 0x400>; 69 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 70 #address-cells = <1>; 71 #size-cells = <0>; 72 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 73 clocks = <&k3_clks 148 0>; 74 status = "disabled"; 75 }; 76 77 mcu_gpio_intr: interrupt-controller@4210000 { 78 compatible = "ti,sci-intr"; 79 reg = <0x00 0x04210000 0x00 0x200>; 80 ti,intr-trigger-type = <1>; 81 interrupt-controller; 82 interrupt-parent = <&gic500>; 83 #interrupt-cells = <1>; 84 ti,sci = <&dmsc>; 85 ti,sci-dev-id = <5>; 86 ti,interrupt-ranges = <0 104 4>; 87 }; 88 89 mcu_gpio0: gpio@4201000 { 90 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 91 reg = <0x0 0x4201000 0x0 0x100>; 92 gpio-controller; 93 #gpio-cells = <2>; 94 interrupt-parent = <&mcu_gpio_intr>; 95 interrupts = <30>, <31>; 96 interrupt-controller; 97 #interrupt-cells = <2>; 98 ti,ngpio = <23>; 99 ti,davinci-gpio-unbanked = <0>; 100 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; 101 clocks = <&k3_clks 79 0>; 102 clock-names = "gpio"; 103 }; 104 105 mcu_pmx0: pinctrl@4084000 { 106 compatible = "pinctrl-single"; 107 reg = <0x00 0x4084000 0x00 0x84>; 108 #pinctrl-cells = <1>; 109 pinctrl-single,register-width = <32>; 110 pinctrl-single,function-mask = <0xffffffff>; 111 }; 112}; 113