1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM642 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8#include <dt-bindings/phy/phy-cadence.h> 9#include <dt-bindings/phy/phy-ti.h> 10 11/ { 12 serdes_refclk: clock-cmnrefclk { 13 #clock-cells = <0>; 14 compatible = "fixed-clock"; 15 clock-frequency = <0>; 16 }; 17}; 18 19&cbass_main { 20 oc_sram: sram@70000000 { 21 compatible = "mmio-sram"; 22 reg = <0x00 0x70000000 0x00 0x200000>; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 ranges = <0x0 0x00 0x70000000 0x200000>; 26 27 tfa-sram@1c0000 { 28 reg = <0x1c0000 0x20000>; 29 }; 30 31 dmsc-sram@1e0000 { 32 reg = <0x1e0000 0x1c000>; 33 }; 34 35 sproxy-sram@1fc000 { 36 reg = <0x1fc000 0x4000>; 37 }; 38 }; 39 40 main_conf: syscon@43000000 { 41 bootph-all; 42 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 43 reg = <0x0 0x43000000 0x0 0x20000>; 44 #address-cells = <1>; 45 #size-cells = <1>; 46 ranges = <0x0 0x0 0x43000000 0x20000>; 47 48 chipid@14 { 49 bootph-all; 50 compatible = "ti,am654-chipid"; 51 reg = <0x00000014 0x4>; 52 }; 53 54 serdes_ln_ctrl: mux-controller { 55 compatible = "mmio-mux"; 56 #mux-control-cells = <1>; 57 mux-reg-masks = <0x4080 0x3>; /* SERDES0 lane0 select */ 58 }; 59 60 phy_gmii_sel: phy@4044 { 61 compatible = "ti,am654-phy-gmii-sel"; 62 reg = <0x4044 0x8>; 63 #phy-cells = <1>; 64 }; 65 66 epwm_tbclk: clock-controller@4130 { 67 compatible = "ti,am64-epwm-tbclk"; 68 reg = <0x4130 0x4>; 69 #clock-cells = <1>; 70 }; 71 }; 72 73 gic500: interrupt-controller@1800000 { 74 compatible = "arm,gic-v3"; 75 #address-cells = <2>; 76 #size-cells = <2>; 77 ranges; 78 #interrupt-cells = <3>; 79 interrupt-controller; 80 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 81 <0x00 0x01840000 0x00 0xC0000>, /* GICR */ 82 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 83 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 84 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 85 /* 86 * vcpumntirq: 87 * virtual CPU interface maintenance interrupt 88 */ 89 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 90 91 gic_its: msi-controller@1820000 { 92 compatible = "arm,gic-v3-its"; 93 reg = <0x00 0x01820000 0x00 0x10000>; 94 socionext,synquacer-pre-its = <0x1000000 0x400000>; 95 msi-controller; 96 #msi-cells = <1>; 97 }; 98 }; 99 100 dmss: bus@48000000 { 101 bootph-all; 102 compatible = "simple-bus"; 103 #address-cells = <2>; 104 #size-cells = <2>; 105 dma-ranges; 106 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 107 108 ti,sci-dev-id = <25>; 109 110 secure_proxy_main: mailbox@4d000000 { 111 bootph-all; 112 compatible = "ti,am654-secure-proxy"; 113 #mbox-cells = <1>; 114 reg-names = "target_data", "rt", "scfg"; 115 reg = <0x00 0x4d000000 0x00 0x80000>, 116 <0x00 0x4a600000 0x00 0x80000>, 117 <0x00 0x4a400000 0x00 0x80000>; 118 interrupt-names = "rx_012"; 119 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 120 }; 121 122 inta_main_dmss: interrupt-controller@48000000 { 123 compatible = "ti,sci-inta"; 124 reg = <0x00 0x48000000 0x00 0x100000>; 125 #interrupt-cells = <0>; 126 interrupt-controller; 127 interrupt-parent = <&gic500>; 128 msi-controller; 129 ti,sci = <&dmsc>; 130 ti,sci-dev-id = <28>; 131 ti,interrupt-ranges = <4 68 36>; 132 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 133 }; 134 135 main_bcdma: dma-controller@485c0100 { 136 compatible = "ti,am64-dmss-bcdma"; 137 reg = <0x00 0x485c0100 0x00 0x100>, 138 <0x00 0x4c000000 0x00 0x20000>, 139 <0x00 0x4a820000 0x00 0x20000>, 140 <0x00 0x4aa40000 0x00 0x20000>, 141 <0x00 0x4bc00000 0x00 0x100000>, 142 <0x00 0x48600000 0x00 0x8000>, 143 <0x00 0x484a4000 0x00 0x2000>, 144 <0x00 0x484c2000 0x00 0x2000>, 145 <0x00 0x48420000 0x00 0x2000>; 146 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", 147 "ring", "tchan", "rchan", "bchan"; 148 msi-parent = <&inta_main_dmss>; 149 #dma-cells = <3>; 150 151 ti,sci = <&dmsc>; 152 ti,sci-dev-id = <26>; 153 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 154 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 155 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 156 }; 157 158 main_pktdma: dma-controller@485c0000 { 159 compatible = "ti,am64-dmss-pktdma"; 160 reg = <0x00 0x485c0000 0x00 0x100>, 161 <0x00 0x4a800000 0x00 0x20000>, 162 <0x00 0x4aa00000 0x00 0x40000>, 163 <0x00 0x4b800000 0x00 0x400000>, 164 <0x00 0x485e0000 0x00 0x20000>, 165 <0x00 0x484a0000 0x00 0x4000>, 166 <0x00 0x484c0000 0x00 0x2000>, 167 <0x00 0x48430000 0x00 0x4000>; 168 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", 169 "ring", "tchan", "rchan", "rflow"; 170 msi-parent = <&inta_main_dmss>; 171 #dma-cells = <2>; 172 173 ti,sci = <&dmsc>; 174 ti,sci-dev-id = <30>; 175 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 176 <0x24>, /* CPSW_TX_CHAN */ 177 <0x25>, /* SAUL_TX_0_CHAN */ 178 <0x26>, /* SAUL_TX_1_CHAN */ 179 <0x27>, /* ICSSG_0_TX_CHAN */ 180 <0x28>; /* ICSSG_1_TX_CHAN */ 181 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 182 <0x11>, /* RING_CPSW_TX_CHAN */ 183 <0x12>, /* RING_SAUL_TX_0_CHAN */ 184 <0x13>, /* RING_SAUL_TX_1_CHAN */ 185 <0x14>, /* RING_ICSSG_0_TX_CHAN */ 186 <0x15>; /* RING_ICSSG_1_TX_CHAN */ 187 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 188 <0x2b>, /* CPSW_RX_CHAN */ 189 <0x2d>, /* SAUL_RX_0_CHAN */ 190 <0x2f>, /* SAUL_RX_1_CHAN */ 191 <0x31>, /* SAUL_RX_2_CHAN */ 192 <0x33>, /* SAUL_RX_3_CHAN */ 193 <0x35>, /* ICSSG_0_RX_CHAN */ 194 <0x37>; /* ICSSG_1_RX_CHAN */ 195 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 196 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 197 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 198 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */ 199 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */ 200 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */ 201 }; 202 }; 203 204 dmsc: system-controller@44043000 { 205 bootph-all; 206 compatible = "ti,k2g-sci"; 207 ti,host-id = <12>; 208 mbox-names = "rx", "tx"; 209 mboxes = <&secure_proxy_main 12>, 210 <&secure_proxy_main 13>; 211 reg-names = "debug_messages"; 212 reg = <0x00 0x44043000 0x00 0xfe0>; 213 214 k3_pds: power-controller { 215 bootph-all; 216 compatible = "ti,sci-pm-domain"; 217 #power-domain-cells = <2>; 218 }; 219 220 k3_clks: clock-controller { 221 bootph-all; 222 compatible = "ti,k2g-sci-clk"; 223 #clock-cells = <2>; 224 }; 225 226 k3_reset: reset-controller { 227 bootph-all; 228 compatible = "ti,sci-reset"; 229 #reset-cells = <2>; 230 }; 231 }; 232 233 main_pmx0: pinctrl@f4000 { 234 bootph-all; 235 compatible = "pinctrl-single"; 236 reg = <0x00 0xf4000 0x00 0x2d0>; 237 #pinctrl-cells = <1>; 238 pinctrl-single,register-width = <32>; 239 pinctrl-single,function-mask = <0xffffffff>; 240 }; 241 242 main_timer0: timer@2400000 { 243 bootph-all; 244 compatible = "ti,am654-timer"; 245 reg = <0x00 0x2400000 0x00 0x400>; 246 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&k3_clks 36 1>; 248 clock-names = "fck"; 249 assigned-clocks = <&k3_clks 36 1>; 250 assigned-clock-parents = <&k3_clks 36 2>; 251 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 252 ti,timer-pwm; 253 }; 254 255 main_timer1: timer@2410000 { 256 compatible = "ti,am654-timer"; 257 reg = <0x00 0x2410000 0x00 0x400>; 258 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&k3_clks 37 1>; 260 clock-names = "fck"; 261 assigned-clocks = <&k3_clks 37 1>; 262 assigned-clock-parents = <&k3_clks 37 2>; 263 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 264 ti,timer-pwm; 265 }; 266 267 main_timer2: timer@2420000 { 268 compatible = "ti,am654-timer"; 269 reg = <0x00 0x2420000 0x00 0x400>; 270 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&k3_clks 38 1>; 272 clock-names = "fck"; 273 assigned-clocks = <&k3_clks 38 1>; 274 assigned-clock-parents = <&k3_clks 38 2>; 275 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 276 ti,timer-pwm; 277 }; 278 279 main_timer3: timer@2430000 { 280 compatible = "ti,am654-timer"; 281 reg = <0x00 0x2430000 0x00 0x400>; 282 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&k3_clks 39 1>; 284 clock-names = "fck"; 285 assigned-clocks = <&k3_clks 39 1>; 286 assigned-clock-parents = <&k3_clks 39 2>; 287 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 288 ti,timer-pwm; 289 }; 290 291 main_timer4: timer@2440000 { 292 compatible = "ti,am654-timer"; 293 reg = <0x00 0x2440000 0x00 0x400>; 294 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 295 clocks = <&k3_clks 40 1>; 296 clock-names = "fck"; 297 assigned-clocks = <&k3_clks 40 1>; 298 assigned-clock-parents = <&k3_clks 40 2>; 299 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 300 ti,timer-pwm; 301 }; 302 303 main_timer5: timer@2450000 { 304 compatible = "ti,am654-timer"; 305 reg = <0x00 0x2450000 0x00 0x400>; 306 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&k3_clks 41 1>; 308 clock-names = "fck"; 309 assigned-clocks = <&k3_clks 41 1>; 310 assigned-clock-parents = <&k3_clks 41 2>; 311 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 312 ti,timer-pwm; 313 }; 314 315 main_timer6: timer@2460000 { 316 compatible = "ti,am654-timer"; 317 reg = <0x00 0x2460000 0x00 0x400>; 318 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&k3_clks 42 1>; 320 clock-names = "fck"; 321 assigned-clocks = <&k3_clks 42 1>; 322 assigned-clock-parents = <&k3_clks 42 2>; 323 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 324 ti,timer-pwm; 325 }; 326 327 main_timer7: timer@2470000 { 328 compatible = "ti,am654-timer"; 329 reg = <0x00 0x2470000 0x00 0x400>; 330 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&k3_clks 43 1>; 332 clock-names = "fck"; 333 assigned-clocks = <&k3_clks 43 1>; 334 assigned-clock-parents = <&k3_clks 43 2>; 335 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 336 ti,timer-pwm; 337 }; 338 339 main_timer8: timer@2480000 { 340 compatible = "ti,am654-timer"; 341 reg = <0x00 0x2480000 0x00 0x400>; 342 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&k3_clks 44 1>; 344 clock-names = "fck"; 345 assigned-clocks = <&k3_clks 44 1>; 346 assigned-clock-parents = <&k3_clks 44 2>; 347 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; 348 ti,timer-pwm; 349 }; 350 351 main_timer9: timer@2490000 { 352 compatible = "ti,am654-timer"; 353 reg = <0x00 0x2490000 0x00 0x400>; 354 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&k3_clks 45 1>; 356 clock-names = "fck"; 357 assigned-clocks = <&k3_clks 45 1>; 358 assigned-clock-parents = <&k3_clks 45 2>; 359 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; 360 ti,timer-pwm; 361 }; 362 363 main_timer10: timer@24a0000 { 364 compatible = "ti,am654-timer"; 365 reg = <0x00 0x24a0000 0x00 0x400>; 366 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&k3_clks 46 1>; 368 clock-names = "fck"; 369 assigned-clocks = <&k3_clks 46 1>; 370 assigned-clock-parents = <&k3_clks 46 2>; 371 power-domains = <&k3_pds 46 TI_SCI_PD_EXCLUSIVE>; 372 ti,timer-pwm; 373 }; 374 375 main_timer11: timer@24b0000 { 376 compatible = "ti,am654-timer"; 377 reg = <0x00 0x24b0000 0x00 0x400>; 378 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&k3_clks 47 1>; 380 clock-names = "fck"; 381 assigned-clocks = <&k3_clks 47 1>; 382 assigned-clock-parents = <&k3_clks 47 2>; 383 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; 384 ti,timer-pwm; 385 }; 386 387 main_esm: esm@420000 { 388 bootph-pre-ram; 389 compatible = "ti,j721e-esm"; 390 reg = <0x00 0x420000 0x00 0x1000>; 391 ti,esm-pins = <160>, <161>; 392 }; 393 394 main_uart0: serial@2800000 { 395 compatible = "ti,am64-uart", "ti,am654-uart"; 396 reg = <0x00 0x02800000 0x00 0x100>; 397 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 398 clock-frequency = <48000000>; 399 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 400 clocks = <&k3_clks 146 0>; 401 clock-names = "fclk"; 402 status = "disabled"; 403 }; 404 405 main_uart1: serial@2810000 { 406 compatible = "ti,am64-uart", "ti,am654-uart"; 407 reg = <0x00 0x02810000 0x00 0x100>; 408 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 409 clock-frequency = <48000000>; 410 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 411 clocks = <&k3_clks 152 0>; 412 clock-names = "fclk"; 413 status = "disabled"; 414 }; 415 416 main_uart2: serial@2820000 { 417 compatible = "ti,am64-uart", "ti,am654-uart"; 418 reg = <0x00 0x02820000 0x00 0x100>; 419 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 420 clock-frequency = <48000000>; 421 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 422 clocks = <&k3_clks 153 0>; 423 clock-names = "fclk"; 424 status = "disabled"; 425 }; 426 427 main_uart3: serial@2830000 { 428 compatible = "ti,am64-uart", "ti,am654-uart"; 429 reg = <0x00 0x02830000 0x00 0x100>; 430 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 431 clock-frequency = <48000000>; 432 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 433 clocks = <&k3_clks 154 0>; 434 clock-names = "fclk"; 435 status = "disabled"; 436 }; 437 438 main_uart4: serial@2840000 { 439 compatible = "ti,am64-uart", "ti,am654-uart"; 440 reg = <0x00 0x02840000 0x00 0x100>; 441 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 442 clock-frequency = <48000000>; 443 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 444 clocks = <&k3_clks 155 0>; 445 clock-names = "fclk"; 446 status = "disabled"; 447 }; 448 449 main_uart5: serial@2850000 { 450 compatible = "ti,am64-uart", "ti,am654-uart"; 451 reg = <0x00 0x02850000 0x00 0x100>; 452 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 453 clock-frequency = <48000000>; 454 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 455 clocks = <&k3_clks 156 0>; 456 clock-names = "fclk"; 457 status = "disabled"; 458 }; 459 460 main_uart6: serial@2860000 { 461 compatible = "ti,am64-uart", "ti,am654-uart"; 462 reg = <0x00 0x02860000 0x00 0x100>; 463 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 464 clock-frequency = <48000000>; 465 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 466 clocks = <&k3_clks 158 0>; 467 clock-names = "fclk"; 468 status = "disabled"; 469 }; 470 471 main_i2c0: i2c@20000000 { 472 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 473 reg = <0x00 0x20000000 0x00 0x100>; 474 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 475 #address-cells = <1>; 476 #size-cells = <0>; 477 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 478 clocks = <&k3_clks 102 2>; 479 clock-names = "fck"; 480 status = "disabled"; 481 }; 482 483 main_i2c1: i2c@20010000 { 484 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 485 reg = <0x00 0x20010000 0x00 0x100>; 486 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 487 #address-cells = <1>; 488 #size-cells = <0>; 489 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 490 clocks = <&k3_clks 103 2>; 491 clock-names = "fck"; 492 status = "disabled"; 493 }; 494 495 main_i2c2: i2c@20020000 { 496 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 497 reg = <0x00 0x20020000 0x00 0x100>; 498 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 499 #address-cells = <1>; 500 #size-cells = <0>; 501 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 502 clocks = <&k3_clks 104 2>; 503 clock-names = "fck"; 504 status = "disabled"; 505 }; 506 507 main_i2c3: i2c@20030000 { 508 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 509 reg = <0x00 0x20030000 0x00 0x100>; 510 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 511 #address-cells = <1>; 512 #size-cells = <0>; 513 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 514 clocks = <&k3_clks 105 2>; 515 clock-names = "fck"; 516 status = "disabled"; 517 }; 518 519 main_spi0: spi@20100000 { 520 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 521 reg = <0x00 0x20100000 0x00 0x400>; 522 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 523 #address-cells = <1>; 524 #size-cells = <0>; 525 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 526 clocks = <&k3_clks 141 0>; 527 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>; 528 dma-names = "tx0", "rx0"; 529 status = "disabled"; 530 }; 531 532 main_spi1: spi@20110000 { 533 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 534 reg = <0x00 0x20110000 0x00 0x400>; 535 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 539 clocks = <&k3_clks 142 0>; 540 status = "disabled"; 541 }; 542 543 main_spi2: spi@20120000 { 544 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 545 reg = <0x00 0x20120000 0x00 0x400>; 546 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 550 clocks = <&k3_clks 143 0>; 551 status = "disabled"; 552 }; 553 554 main_spi3: spi@20130000 { 555 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 556 reg = <0x00 0x20130000 0x00 0x400>; 557 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 558 #address-cells = <1>; 559 #size-cells = <0>; 560 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 561 clocks = <&k3_clks 144 0>; 562 status = "disabled"; 563 }; 564 565 main_spi4: spi@20140000 { 566 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 567 reg = <0x00 0x20140000 0x00 0x400>; 568 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 569 #address-cells = <1>; 570 #size-cells = <0>; 571 power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>; 572 clocks = <&k3_clks 145 0>; 573 status = "disabled"; 574 }; 575 576 main_gpio_intr: interrupt-controller@a00000 { 577 compatible = "ti,sci-intr"; 578 reg = <0x00 0x00a00000 0x00 0x800>; 579 ti,intr-trigger-type = <1>; 580 interrupt-controller; 581 interrupt-parent = <&gic500>; 582 #interrupt-cells = <1>; 583 ti,sci = <&dmsc>; 584 ti,sci-dev-id = <3>; 585 ti,interrupt-ranges = <0 32 16>; 586 }; 587 588 main_gpio0: gpio@600000 { 589 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 590 reg = <0x0 0x00600000 0x0 0x100>; 591 gpio-controller; 592 #gpio-cells = <2>; 593 interrupt-parent = <&main_gpio_intr>; 594 interrupts = <190>, <191>, <192>, 595 <193>, <194>, <195>; 596 interrupt-controller; 597 #interrupt-cells = <2>; 598 ti,ngpio = <87>; 599 ti,davinci-gpio-unbanked = <0>; 600 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 601 clocks = <&k3_clks 77 0>; 602 clock-names = "gpio"; 603 }; 604 605 main_gpio1: gpio@601000 { 606 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 607 reg = <0x0 0x00601000 0x0 0x100>; 608 gpio-controller; 609 #gpio-cells = <2>; 610 interrupt-parent = <&main_gpio_intr>; 611 interrupts = <180>, <181>, <182>, 612 <183>, <184>, <185>; 613 interrupt-controller; 614 #interrupt-cells = <2>; 615 ti,ngpio = <88>; 616 ti,davinci-gpio-unbanked = <0>; 617 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 618 clocks = <&k3_clks 78 0>; 619 clock-names = "gpio"; 620 }; 621 622 sdhci0: mmc@fa10000 { 623 compatible = "ti,am64-sdhci-8bit"; 624 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; 625 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 626 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 627 clocks = <&k3_clks 57 0>, <&k3_clks 57 1>; 628 clock-names = "clk_ahb", "clk_xin"; 629 mmc-ddr-1_8v; 630 mmc-hs200-1_8v; 631 ti,trm-icp = <0x2>; 632 ti,otap-del-sel-legacy = <0x0>; 633 ti,otap-del-sel-mmc-hs = <0x0>; 634 ti,otap-del-sel-ddr52 = <0x6>; 635 ti,otap-del-sel-hs200 = <0x7>; 636 status = "disabled"; 637 }; 638 639 sdhci1: mmc@fa00000 { 640 compatible = "ti,am64-sdhci-4bit"; 641 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; 642 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 643 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 644 clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; 645 clock-names = "clk_ahb", "clk_xin"; 646 ti,trm-icp = <0x2>; 647 ti,otap-del-sel-legacy = <0x0>; 648 ti,otap-del-sel-sd-hs = <0xf>; 649 ti,otap-del-sel-sdr12 = <0xf>; 650 ti,otap-del-sel-sdr25 = <0xf>; 651 ti,otap-del-sel-sdr50 = <0xc>; 652 ti,otap-del-sel-sdr104 = <0x6>; 653 ti,otap-del-sel-ddr50 = <0x9>; 654 ti,clkbuf-sel = <0x7>; 655 status = "disabled"; 656 }; 657 658 cpsw3g: ethernet@8000000 { 659 compatible = "ti,am642-cpsw-nuss"; 660 #address-cells = <2>; 661 #size-cells = <2>; 662 reg = <0x0 0x8000000 0x0 0x200000>; 663 reg-names = "cpsw_nuss"; 664 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; 665 clocks = <&k3_clks 13 0>; 666 assigned-clocks = <&k3_clks 13 1>; 667 assigned-clock-parents = <&k3_clks 13 9>; 668 clock-names = "fck"; 669 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 670 671 dmas = <&main_pktdma 0xC500 15>, 672 <&main_pktdma 0xC501 15>, 673 <&main_pktdma 0xC502 15>, 674 <&main_pktdma 0xC503 15>, 675 <&main_pktdma 0xC504 15>, 676 <&main_pktdma 0xC505 15>, 677 <&main_pktdma 0xC506 15>, 678 <&main_pktdma 0xC507 15>, 679 <&main_pktdma 0x4500 15>; 680 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 681 "tx7", "rx"; 682 683 ethernet-ports { 684 #address-cells = <1>; 685 #size-cells = <0>; 686 687 cpsw_port1: port@1 { 688 reg = <1>; 689 ti,mac-only; 690 label = "port1"; 691 phys = <&phy_gmii_sel 1>; 692 mac-address = [00 00 00 00 00 00]; 693 ti,syscon-efuse = <&main_conf 0x200>; 694 }; 695 696 cpsw_port2: port@2 { 697 reg = <2>; 698 ti,mac-only; 699 label = "port2"; 700 phys = <&phy_gmii_sel 2>; 701 mac-address = [00 00 00 00 00 00]; 702 }; 703 }; 704 705 cpsw3g_mdio: mdio@f00 { 706 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 707 reg = <0x0 0xf00 0x0 0x100>; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 clocks = <&k3_clks 13 0>; 711 clock-names = "fck"; 712 bus_freq = <1000000>; 713 status = "disabled"; 714 }; 715 716 cpts@3d000 { 717 compatible = "ti,j721e-cpts"; 718 reg = <0x0 0x3d000 0x0 0x400>; 719 clocks = <&k3_clks 13 1>; 720 clock-names = "cpts"; 721 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 722 interrupt-names = "cpts"; 723 ti,cpts-ext-ts-inputs = <4>; 724 ti,cpts-periodic-outputs = <2>; 725 }; 726 }; 727 728 main_cpts0: cpts@39000000 { 729 compatible = "ti,j721e-cpts"; 730 reg = <0x0 0x39000000 0x0 0x400>; 731 reg-names = "cpts"; 732 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 733 clocks = <&k3_clks 84 0>; 734 clock-names = "cpts"; 735 assigned-clocks = <&k3_clks 84 0>; 736 assigned-clock-parents = <&k3_clks 84 8>; 737 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 738 interrupt-names = "cpts"; 739 ti,cpts-periodic-outputs = <6>; 740 ti,cpts-ext-ts-inputs = <8>; 741 }; 742 743 timesync_router: pinctrl@a40000 { 744 compatible = "pinctrl-single"; 745 reg = <0x0 0xa40000 0x0 0x800>; 746 #pinctrl-cells = <1>; 747 pinctrl-single,register-width = <32>; 748 pinctrl-single,function-mask = <0x000107ff>; 749 }; 750 751 usbss0: cdns-usb@f900000 { 752 compatible = "ti,am64-usb"; 753 reg = <0x00 0xf900000 0x00 0x100>; 754 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 755 clocks = <&k3_clks 161 9>, <&k3_clks 161 1>; 756 clock-names = "ref", "lpm"; 757 assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */ 758 assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */ 759 #address-cells = <2>; 760 #size-cells = <2>; 761 ranges; 762 usb0: usb@f400000 { 763 compatible = "cdns,usb3"; 764 reg = <0x00 0xf400000 0x00 0x10000>, 765 <0x00 0xf410000 0x00 0x10000>, 766 <0x00 0xf420000 0x00 0x10000>; 767 reg-names = "otg", 768 "xhci", 769 "dev"; 770 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 771 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 772 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */ 773 interrupt-names = "host", 774 "peripheral", 775 "otg"; 776 maximum-speed = "super-speed"; 777 dr_mode = "otg"; 778 }; 779 }; 780 781 tscadc0: tscadc@28001000 { 782 compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 783 reg = <0x00 0x28001000 0x00 0x1000>; 784 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 785 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 786 clocks = <&k3_clks 0 0>; 787 assigned-clocks = <&k3_clks 0 0>; 788 assigned-clock-parents = <&k3_clks 0 3>; 789 assigned-clock-rates = <60000000>; 790 clock-names = "fck"; 791 status = "disabled"; 792 793 adc { 794 #io-channel-cells = <1>; 795 compatible = "ti,am654-adc", "ti,am3359-adc"; 796 }; 797 }; 798 799 fss: bus@fc00000 { 800 compatible = "simple-bus"; 801 reg = <0x00 0x0fc00000 0x00 0x70000>; 802 #address-cells = <2>; 803 #size-cells = <2>; 804 ranges; 805 806 ospi0: spi@fc40000 { 807 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 808 reg = <0x00 0x0fc40000 0x00 0x100>, 809 <0x05 0x00000000 0x01 0x00000000>; 810 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 811 cdns,fifo-depth = <256>; 812 cdns,fifo-width = <4>; 813 cdns,trigger-address = <0x0>; 814 #address-cells = <0x1>; 815 #size-cells = <0x0>; 816 clocks = <&k3_clks 75 6>; 817 assigned-clocks = <&k3_clks 75 6>; 818 assigned-clock-parents = <&k3_clks 75 7>; 819 assigned-clock-rates = <166666666>; 820 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 821 status = "disabled"; 822 }; 823 }; 824 825 hwspinlock: spinlock@2a000000 { 826 compatible = "ti,am64-hwspinlock"; 827 reg = <0x00 0x2a000000 0x00 0x1000>; 828 #hwlock-cells = <1>; 829 }; 830 831 mailbox0_cluster2: mailbox@29020000 { 832 compatible = "ti,am64-mailbox"; 833 reg = <0x00 0x29020000 0x00 0x200>; 834 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 836 #mbox-cells = <1>; 837 ti,mbox-num-users = <4>; 838 ti,mbox-num-fifos = <16>; 839 status = "disabled"; 840 }; 841 842 mailbox0_cluster3: mailbox@29030000 { 843 compatible = "ti,am64-mailbox"; 844 reg = <0x00 0x29030000 0x00 0x200>; 845 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 846 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 847 #mbox-cells = <1>; 848 ti,mbox-num-users = <4>; 849 ti,mbox-num-fifos = <16>; 850 status = "disabled"; 851 }; 852 853 mailbox0_cluster4: mailbox@29040000 { 854 compatible = "ti,am64-mailbox"; 855 reg = <0x00 0x29040000 0x00 0x200>; 856 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 858 #mbox-cells = <1>; 859 ti,mbox-num-users = <4>; 860 ti,mbox-num-fifos = <16>; 861 status = "disabled"; 862 }; 863 864 mailbox0_cluster5: mailbox@29050000 { 865 compatible = "ti,am64-mailbox"; 866 reg = <0x00 0x29050000 0x00 0x200>; 867 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 869 #mbox-cells = <1>; 870 ti,mbox-num-users = <4>; 871 ti,mbox-num-fifos = <16>; 872 status = "disabled"; 873 }; 874 875 mailbox0_cluster6: mailbox@29060000 { 876 compatible = "ti,am64-mailbox"; 877 reg = <0x00 0x29060000 0x00 0x200>; 878 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 879 #mbox-cells = <1>; 880 ti,mbox-num-users = <4>; 881 ti,mbox-num-fifos = <16>; 882 status = "disabled"; 883 }; 884 885 mailbox0_cluster7: mailbox@29070000 { 886 compatible = "ti,am64-mailbox"; 887 reg = <0x00 0x29070000 0x00 0x200>; 888 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 889 #mbox-cells = <1>; 890 ti,mbox-num-users = <4>; 891 ti,mbox-num-fifos = <16>; 892 status = "disabled"; 893 }; 894 895 main_r5fss0: r5fss@78000000 { 896 compatible = "ti,am64-r5fss"; 897 ti,cluster-mode = <0>; 898 #address-cells = <1>; 899 #size-cells = <1>; 900 ranges = <0x78000000 0x00 0x78000000 0x10000>, 901 <0x78100000 0x00 0x78100000 0x10000>, 902 <0x78200000 0x00 0x78200000 0x08000>, 903 <0x78300000 0x00 0x78300000 0x08000>; 904 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 905 906 main_r5fss0_core0: r5f@78000000 { 907 compatible = "ti,am64-r5f"; 908 reg = <0x78000000 0x00010000>, 909 <0x78100000 0x00010000>; 910 reg-names = "atcm", "btcm"; 911 ti,sci = <&dmsc>; 912 ti,sci-dev-id = <121>; 913 ti,sci-proc-ids = <0x01 0xff>; 914 resets = <&k3_reset 121 1>; 915 firmware-name = "am64-main-r5f0_0-fw"; 916 ti,atcm-enable = <1>; 917 ti,btcm-enable = <1>; 918 ti,loczrama = <1>; 919 }; 920 921 main_r5fss0_core1: r5f@78200000 { 922 compatible = "ti,am64-r5f"; 923 reg = <0x78200000 0x00008000>, 924 <0x78300000 0x00008000>; 925 reg-names = "atcm", "btcm"; 926 ti,sci = <&dmsc>; 927 ti,sci-dev-id = <122>; 928 ti,sci-proc-ids = <0x02 0xff>; 929 resets = <&k3_reset 122 1>; 930 firmware-name = "am64-main-r5f0_1-fw"; 931 ti,atcm-enable = <1>; 932 ti,btcm-enable = <1>; 933 ti,loczrama = <1>; 934 }; 935 }; 936 937 main_r5fss1: r5fss@78400000 { 938 compatible = "ti,am64-r5fss"; 939 ti,cluster-mode = <0>; 940 #address-cells = <1>; 941 #size-cells = <1>; 942 ranges = <0x78400000 0x00 0x78400000 0x10000>, 943 <0x78500000 0x00 0x78500000 0x10000>, 944 <0x78600000 0x00 0x78600000 0x08000>, 945 <0x78700000 0x00 0x78700000 0x08000>; 946 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 947 948 main_r5fss1_core0: r5f@78400000 { 949 compatible = "ti,am64-r5f"; 950 reg = <0x78400000 0x00010000>, 951 <0x78500000 0x00010000>; 952 reg-names = "atcm", "btcm"; 953 ti,sci = <&dmsc>; 954 ti,sci-dev-id = <123>; 955 ti,sci-proc-ids = <0x06 0xff>; 956 resets = <&k3_reset 123 1>; 957 firmware-name = "am64-main-r5f1_0-fw"; 958 ti,atcm-enable = <1>; 959 ti,btcm-enable = <1>; 960 ti,loczrama = <1>; 961 }; 962 963 main_r5fss1_core1: r5f@78600000 { 964 compatible = "ti,am64-r5f"; 965 reg = <0x78600000 0x00008000>, 966 <0x78700000 0x00008000>; 967 reg-names = "atcm", "btcm"; 968 ti,sci = <&dmsc>; 969 ti,sci-dev-id = <124>; 970 ti,sci-proc-ids = <0x07 0xff>; 971 resets = <&k3_reset 124 1>; 972 firmware-name = "am64-main-r5f1_1-fw"; 973 ti,atcm-enable = <1>; 974 ti,btcm-enable = <1>; 975 ti,loczrama = <1>; 976 }; 977 }; 978 979 serdes_wiz0: wiz@f000000 { 980 compatible = "ti,am64-wiz-10g"; 981 #address-cells = <1>; 982 #size-cells = <1>; 983 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 984 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&serdes_refclk>; 985 clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 986 num-lanes = <1>; 987 #reset-cells = <1>; 988 #clock-cells = <1>; 989 ranges = <0x0f000000 0x0 0x0f000000 0x00010000>; 990 991 assigned-clocks = <&k3_clks 162 1>; 992 assigned-clock-parents = <&k3_clks 162 5>; 993 994 serdes0: serdes@f000000 { 995 compatible = "ti,j721e-serdes-10g"; 996 reg = <0x0f000000 0x00010000>; 997 reg-names = "torrent_phy"; 998 resets = <&serdes_wiz0 0>; 999 reset-names = "torrent_reset"; 1000 clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1001 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>; 1002 clock-names = "refclk", "phy_en_refclk"; 1003 assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>, 1004 <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>, 1005 <&serdes_wiz0 TI_WIZ_REFCLK_DIG>; 1006 assigned-clock-parents = <&k3_clks 162 1>, 1007 <&k3_clks 162 1>, 1008 <&k3_clks 162 1>; 1009 #address-cells = <1>; 1010 #size-cells = <0>; 1011 #clock-cells = <1>; 1012 }; 1013 }; 1014 1015 pcie0_rc: pcie@f102000 { 1016 compatible = "ti,am64-pcie-host", "ti,j721e-pcie-host"; 1017 reg = <0x00 0x0f102000 0x00 0x1000>, 1018 <0x00 0x0f100000 0x00 0x400>, 1019 <0x00 0x0d000000 0x00 0x00800000>, 1020 <0x00 0x68000000 0x00 0x00001000>; 1021 reg-names = "intd_cfg", "user_cfg", "reg", "cfg"; 1022 interrupt-names = "link_state"; 1023 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 1024 device_type = "pci"; 1025 ti,syscon-pcie-ctrl = <&main_conf 0x4070>; 1026 max-link-speed = <2>; 1027 num-lanes = <1>; 1028 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 1029 clocks = <&k3_clks 114 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; 1030 clock-names = "fck", "pcie_refclk"; 1031 #address-cells = <3>; 1032 #size-cells = <2>; 1033 bus-range = <0x0 0xff>; 1034 cdns,no-bar-match-nbits = <64>; 1035 vendor-id = <0x104c>; 1036 device-id = <0xb010>; 1037 msi-map = <0x0 &gic_its 0x0 0x10000>; 1038 ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>, 1039 <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>; 1040 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>; 1041 status = "disabled"; 1042 }; 1043 1044 pcie0_ep: pcie-ep@f102000 { 1045 compatible = "ti,am64-pcie-ep", "ti,j721e-pcie-ep"; 1046 reg = <0x00 0x0f102000 0x00 0x1000>, 1047 <0x00 0x0f100000 0x00 0x400>, 1048 <0x00 0x0d000000 0x00 0x00800000>, 1049 <0x00 0x68000000 0x00 0x08000000>; 1050 reg-names = "intd_cfg", "user_cfg", "reg", "mem"; 1051 interrupt-names = "link_state"; 1052 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 1053 ti,syscon-pcie-ctrl = <&main_conf 0x4070>; 1054 max-link-speed = <2>; 1055 num-lanes = <1>; 1056 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 1057 clocks = <&k3_clks 114 0>; 1058 clock-names = "fck"; 1059 max-functions = /bits/ 8 <1>; 1060 status = "disabled"; 1061 }; 1062 1063 epwm0: pwm@23000000 { 1064 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1065 #pwm-cells = <3>; 1066 reg = <0x0 0x23000000 0x0 0x100>; 1067 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 1068 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 1069 clock-names = "tbclk", "fck"; 1070 status = "disabled"; 1071 }; 1072 1073 epwm1: pwm@23010000 { 1074 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1075 #pwm-cells = <3>; 1076 reg = <0x0 0x23010000 0x0 0x100>; 1077 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 1078 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 1079 clock-names = "tbclk", "fck"; 1080 status = "disabled"; 1081 }; 1082 1083 epwm2: pwm@23020000 { 1084 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1085 #pwm-cells = <3>; 1086 reg = <0x0 0x23020000 0x0 0x100>; 1087 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 1088 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 1089 clock-names = "tbclk", "fck"; 1090 status = "disabled"; 1091 }; 1092 1093 epwm3: pwm@23030000 { 1094 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1095 #pwm-cells = <3>; 1096 reg = <0x0 0x23030000 0x0 0x100>; 1097 power-domains = <&k3_pds 89 TI_SCI_PD_EXCLUSIVE>; 1098 clocks = <&epwm_tbclk 3>, <&k3_clks 89 0>; 1099 clock-names = "tbclk", "fck"; 1100 status = "disabled"; 1101 }; 1102 1103 epwm4: pwm@23040000 { 1104 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1105 #pwm-cells = <3>; 1106 reg = <0x0 0x23040000 0x0 0x100>; 1107 power-domains = <&k3_pds 90 TI_SCI_PD_EXCLUSIVE>; 1108 clocks = <&epwm_tbclk 4>, <&k3_clks 90 0>; 1109 clock-names = "tbclk", "fck"; 1110 status = "disabled"; 1111 }; 1112 1113 epwm5: pwm@23050000 { 1114 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1115 #pwm-cells = <3>; 1116 reg = <0x0 0x23050000 0x0 0x100>; 1117 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>; 1118 clocks = <&epwm_tbclk 5>, <&k3_clks 91 0>; 1119 clock-names = "tbclk", "fck"; 1120 status = "disabled"; 1121 }; 1122 1123 epwm6: pwm@23060000 { 1124 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1125 #pwm-cells = <3>; 1126 reg = <0x0 0x23060000 0x0 0x100>; 1127 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>; 1128 clocks = <&epwm_tbclk 6>, <&k3_clks 92 0>; 1129 clock-names = "tbclk", "fck"; 1130 status = "disabled"; 1131 }; 1132 1133 epwm7: pwm@23070000 { 1134 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1135 #pwm-cells = <3>; 1136 reg = <0x0 0x23070000 0x0 0x100>; 1137 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>; 1138 clocks = <&epwm_tbclk 7>, <&k3_clks 93 0>; 1139 clock-names = "tbclk", "fck"; 1140 status = "disabled"; 1141 }; 1142 1143 epwm8: pwm@23080000 { 1144 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 1145 #pwm-cells = <3>; 1146 reg = <0x0 0x23080000 0x0 0x100>; 1147 power-domains = <&k3_pds 94 TI_SCI_PD_EXCLUSIVE>; 1148 clocks = <&epwm_tbclk 8>, <&k3_clks 94 0>; 1149 clock-names = "tbclk", "fck"; 1150 status = "disabled"; 1151 }; 1152 1153 ecap0: pwm@23100000 { 1154 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 1155 #pwm-cells = <3>; 1156 reg = <0x0 0x23100000 0x0 0x60>; 1157 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 1158 clocks = <&k3_clks 51 0>; 1159 clock-names = "fck"; 1160 status = "disabled"; 1161 }; 1162 1163 ecap1: pwm@23110000 { 1164 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 1165 #pwm-cells = <3>; 1166 reg = <0x0 0x23110000 0x0 0x60>; 1167 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 1168 clocks = <&k3_clks 52 0>; 1169 clock-names = "fck"; 1170 status = "disabled"; 1171 }; 1172 1173 ecap2: pwm@23120000 { 1174 compatible = "ti,am64-ecap", "ti,am3352-ecap"; 1175 #pwm-cells = <3>; 1176 reg = <0x0 0x23120000 0x0 0x60>; 1177 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 1178 clocks = <&k3_clks 53 0>; 1179 clock-names = "fck"; 1180 status = "disabled"; 1181 }; 1182 1183 main_rti0: watchdog@e000000 { 1184 compatible = "ti,j7-rti-wdt"; 1185 reg = <0x00 0xe000000 0x00 0x100>; 1186 clocks = <&k3_clks 125 0>; 1187 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 1188 assigned-clocks = <&k3_clks 125 0>; 1189 assigned-clock-parents = <&k3_clks 125 2>; 1190 }; 1191 1192 main_rti1: watchdog@e010000 { 1193 compatible = "ti,j7-rti-wdt"; 1194 reg = <0x00 0xe010000 0x00 0x100>; 1195 clocks = <&k3_clks 126 0>; 1196 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 1197 assigned-clocks = <&k3_clks 126 0>; 1198 assigned-clock-parents = <&k3_clks 126 2>; 1199 }; 1200 1201 icssg0: icssg@30000000 { 1202 compatible = "ti,am642-icssg"; 1203 reg = <0x00 0x30000000 0x00 0x80000>; 1204 power-domains = <&k3_pds 81 TI_SCI_PD_EXCLUSIVE>; 1205 #address-cells = <1>; 1206 #size-cells = <1>; 1207 ranges = <0x0 0x00 0x30000000 0x80000>; 1208 1209 icssg0_mem: memories@0 { 1210 reg = <0x0 0x2000>, 1211 <0x2000 0x2000>, 1212 <0x10000 0x10000>; 1213 reg-names = "dram0", "dram1", "shrdram2"; 1214 }; 1215 1216 icssg0_cfg: cfg@26000 { 1217 compatible = "ti,pruss-cfg", "syscon"; 1218 reg = <0x26000 0x200>; 1219 #address-cells = <1>; 1220 #size-cells = <1>; 1221 ranges = <0x0 0x26000 0x2000>; 1222 1223 clocks { 1224 #address-cells = <1>; 1225 #size-cells = <0>; 1226 1227 icssg0_coreclk_mux: coreclk-mux@3c { 1228 reg = <0x3c>; 1229 #clock-cells = <0>; 1230 clocks = <&k3_clks 81 0>, /* icssg0_core_clk */ 1231 <&k3_clks 81 20>; /* icssg0_iclk */ 1232 assigned-clocks = <&icssg0_coreclk_mux>; 1233 assigned-clock-parents = <&k3_clks 81 20>; 1234 }; 1235 1236 icssg0_iepclk_mux: iepclk-mux@30 { 1237 reg = <0x30>; 1238 #clock-cells = <0>; 1239 clocks = <&k3_clks 81 3>, /* icssg0_iep_clk */ 1240 <&icssg0_coreclk_mux>; /* icssg0_coreclk_mux */ 1241 assigned-clocks = <&icssg0_iepclk_mux>; 1242 assigned-clock-parents = <&icssg0_coreclk_mux>; 1243 }; 1244 }; 1245 }; 1246 1247 icssg0_mii_rt: mii-rt@32000 { 1248 compatible = "ti,pruss-mii", "syscon"; 1249 reg = <0x32000 0x100>; 1250 }; 1251 1252 icssg0_mii_g_rt: mii-g-rt@33000 { 1253 compatible = "ti,pruss-mii-g", "syscon"; 1254 reg = <0x33000 0x1000>; 1255 }; 1256 1257 icssg0_intc: interrupt-controller@20000 { 1258 compatible = "ti,icssg-intc"; 1259 reg = <0x20000 0x2000>; 1260 interrupt-controller; 1261 #interrupt-cells = <3>; 1262 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1263 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1264 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1265 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1266 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1267 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1270 interrupt-names = "host_intr0", "host_intr1", 1271 "host_intr2", "host_intr3", 1272 "host_intr4", "host_intr5", 1273 "host_intr6", "host_intr7"; 1274 }; 1275 1276 pru0_0: pru@34000 { 1277 compatible = "ti,am642-pru"; 1278 reg = <0x34000 0x3000>, 1279 <0x22000 0x100>, 1280 <0x22400 0x100>; 1281 reg-names = "iram", "control", "debug"; 1282 firmware-name = "am64x-pru0_0-fw"; 1283 }; 1284 1285 rtu0_0: rtu@4000 { 1286 compatible = "ti,am642-rtu"; 1287 reg = <0x4000 0x2000>, 1288 <0x23000 0x100>, 1289 <0x23400 0x100>; 1290 reg-names = "iram", "control", "debug"; 1291 firmware-name = "am64x-rtu0_0-fw"; 1292 }; 1293 1294 tx_pru0_0: txpru@a000 { 1295 compatible = "ti,am642-tx-pru"; 1296 reg = <0xa000 0x1800>, 1297 <0x25000 0x100>, 1298 <0x25400 0x100>; 1299 reg-names = "iram", "control", "debug"; 1300 firmware-name = "am64x-txpru0_0-fw"; 1301 }; 1302 1303 pru0_1: pru@38000 { 1304 compatible = "ti,am642-pru"; 1305 reg = <0x38000 0x3000>, 1306 <0x24000 0x100>, 1307 <0x24400 0x100>; 1308 reg-names = "iram", "control", "debug"; 1309 firmware-name = "am64x-pru0_1-fw"; 1310 }; 1311 1312 rtu0_1: rtu@6000 { 1313 compatible = "ti,am642-rtu"; 1314 reg = <0x6000 0x2000>, 1315 <0x23800 0x100>, 1316 <0x23c00 0x100>; 1317 reg-names = "iram", "control", "debug"; 1318 firmware-name = "am64x-rtu0_1-fw"; 1319 }; 1320 1321 tx_pru0_1: txpru@c000 { 1322 compatible = "ti,am642-tx-pru"; 1323 reg = <0xc000 0x1800>, 1324 <0x25800 0x100>, 1325 <0x25c00 0x100>; 1326 reg-names = "iram", "control", "debug"; 1327 firmware-name = "am64x-txpru0_1-fw"; 1328 }; 1329 1330 icssg0_mdio: mdio@32400 { 1331 compatible = "ti,davinci_mdio"; 1332 reg = <0x32400 0x100>; 1333 clocks = <&k3_clks 62 3>; 1334 clock-names = "fck"; 1335 #address-cells = <1>; 1336 #size-cells = <0>; 1337 bus_freq = <1000000>; 1338 status = "disabled"; 1339 }; 1340 }; 1341 1342 icssg1: icssg@30080000 { 1343 compatible = "ti,am642-icssg"; 1344 reg = <0x00 0x30080000 0x00 0x80000>; 1345 power-domains = <&k3_pds 82 TI_SCI_PD_EXCLUSIVE>; 1346 #address-cells = <1>; 1347 #size-cells = <1>; 1348 ranges = <0x0 0x00 0x30080000 0x80000>; 1349 1350 icssg1_mem: memories@0 { 1351 reg = <0x0 0x2000>, 1352 <0x2000 0x2000>, 1353 <0x10000 0x10000>; 1354 reg-names = "dram0", "dram1", "shrdram2"; 1355 }; 1356 1357 icssg1_cfg: cfg@26000 { 1358 compatible = "ti,pruss-cfg", "syscon"; 1359 reg = <0x26000 0x200>; 1360 #address-cells = <1>; 1361 #size-cells = <1>; 1362 ranges = <0x0 0x26000 0x2000>; 1363 1364 clocks { 1365 #address-cells = <1>; 1366 #size-cells = <0>; 1367 1368 icssg1_coreclk_mux: coreclk-mux@3c { 1369 reg = <0x3c>; 1370 #clock-cells = <0>; 1371 clocks = <&k3_clks 82 0>, /* icssg1_core_clk */ 1372 <&k3_clks 82 20>; /* icssg1_iclk */ 1373 assigned-clocks = <&icssg1_coreclk_mux>; 1374 assigned-clock-parents = <&k3_clks 82 20>; 1375 }; 1376 1377 icssg1_iepclk_mux: iepclk-mux@30 { 1378 reg = <0x30>; 1379 #clock-cells = <0>; 1380 clocks = <&k3_clks 82 3>, /* icssg1_iep_clk */ 1381 <&icssg1_coreclk_mux>; /* icssg1_coreclk_mux */ 1382 assigned-clocks = <&icssg1_iepclk_mux>; 1383 assigned-clock-parents = <&icssg1_coreclk_mux>; 1384 }; 1385 }; 1386 }; 1387 1388 icssg1_mii_rt: mii-rt@32000 { 1389 compatible = "ti,pruss-mii", "syscon"; 1390 reg = <0x32000 0x100>; 1391 }; 1392 1393 icssg1_mii_g_rt: mii-g-rt@33000 { 1394 compatible = "ti,pruss-mii-g", "syscon"; 1395 reg = <0x33000 0x1000>; 1396 }; 1397 1398 icssg1_intc: interrupt-controller@20000 { 1399 compatible = "ti,icssg-intc"; 1400 reg = <0x20000 0x2000>; 1401 interrupt-controller; 1402 #interrupt-cells = <3>; 1403 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 1410 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1411 interrupt-names = "host_intr0", "host_intr1", 1412 "host_intr2", "host_intr3", 1413 "host_intr4", "host_intr5", 1414 "host_intr6", "host_intr7"; 1415 }; 1416 1417 pru1_0: pru@34000 { 1418 compatible = "ti,am642-pru"; 1419 reg = <0x34000 0x4000>, 1420 <0x22000 0x100>, 1421 <0x22400 0x100>; 1422 reg-names = "iram", "control", "debug"; 1423 firmware-name = "am64x-pru1_0-fw"; 1424 }; 1425 1426 rtu1_0: rtu@4000 { 1427 compatible = "ti,am642-rtu"; 1428 reg = <0x4000 0x2000>, 1429 <0x23000 0x100>, 1430 <0x23400 0x100>; 1431 reg-names = "iram", "control", "debug"; 1432 firmware-name = "am64x-rtu1_0-fw"; 1433 }; 1434 1435 tx_pru1_0: txpru@a000 { 1436 compatible = "ti,am642-tx-pru"; 1437 reg = <0xa000 0x1800>, 1438 <0x25000 0x100>, 1439 <0x25400 0x100>; 1440 reg-names = "iram", "control", "debug"; 1441 firmware-name = "am64x-txpru1_0-fw"; 1442 }; 1443 1444 pru1_1: pru@38000 { 1445 compatible = "ti,am642-pru"; 1446 reg = <0x38000 0x4000>, 1447 <0x24000 0x100>, 1448 <0x24400 0x100>; 1449 reg-names = "iram", "control", "debug"; 1450 firmware-name = "am64x-pru1_1-fw"; 1451 }; 1452 1453 rtu1_1: rtu@6000 { 1454 compatible = "ti,am642-rtu"; 1455 reg = <0x6000 0x2000>, 1456 <0x23800 0x100>, 1457 <0x23c00 0x100>; 1458 reg-names = "iram", "control", "debug"; 1459 firmware-name = "am64x-rtu1_1-fw"; 1460 }; 1461 1462 tx_pru1_1: txpru@c000 { 1463 compatible = "ti,am642-tx-pru"; 1464 reg = <0xc000 0x1800>, 1465 <0x25800 0x100>, 1466 <0x25c00 0x100>; 1467 reg-names = "iram", "control", "debug"; 1468 firmware-name = "am64x-txpru1_1-fw"; 1469 }; 1470 1471 icssg1_mdio: mdio@32400 { 1472 compatible = "ti,davinci_mdio"; 1473 reg = <0x32400 0x100>; 1474 #address-cells = <1>; 1475 #size-cells = <0>; 1476 clocks = <&k3_clks 82 0>; 1477 clock-names = "fck"; 1478 bus_freq = <1000000>; 1479 status = "disabled"; 1480 }; 1481 }; 1482 1483 main_mcan0: can@20701000 { 1484 compatible = "bosch,m_can"; 1485 reg = <0x00 0x20701000 0x00 0x200>, 1486 <0x00 0x20708000 0x00 0x8000>; 1487 reg-names = "m_can", "message_ram"; 1488 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 1489 clocks = <&k3_clks 98 5>, <&k3_clks 98 0>; 1490 clock-names = "hclk", "cclk"; 1491 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1493 interrupt-names = "int0", "int1"; 1494 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1495 status = "disabled"; 1496 }; 1497 1498 main_mcan1: can@20711000 { 1499 compatible = "bosch,m_can"; 1500 reg = <0x00 0x20711000 0x00 0x200>, 1501 <0x00 0x20718000 0x00 0x8000>; 1502 reg-names = "m_can", "message_ram"; 1503 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 1504 clocks = <&k3_clks 99 5>, <&k3_clks 99 0>; 1505 clock-names = "hclk", "cclk"; 1506 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1508 interrupt-names = "int0", "int1"; 1509 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1510 status = "disabled"; 1511 }; 1512 1513 crypto: crypto@40900000 { 1514 compatible = "ti,am64-sa2ul"; 1515 reg = <0x00 0x40900000 0x00 0x1200>; 1516 power-domains = <&k3_pds 133 TI_SCI_PD_SHARED>; 1517 #address-cells = <2>; 1518 #size-cells = <2>; 1519 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 1520 dmas = <&main_pktdma 0xc001 0>, <&main_pktdma 0x4002 0>, 1521 <&main_pktdma 0x4003 0>; 1522 dma-names = "tx", "rx1", "rx2"; 1523 1524 rng: rng@40910000 { 1525 compatible = "inside-secure,safexcel-eip76"; 1526 reg = <0x00 0x40910000 0x00 0x7d>; 1527 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1528 status = "disabled"; /* Used by OP-TEE */ 1529 }; 1530 }; 1531 1532 gpmc0: memory-controller@3b000000 { 1533 compatible = "ti,am64-gpmc"; 1534 power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>; 1535 clocks = <&k3_clks 80 0>; 1536 clock-names = "fck"; 1537 reg = <0x00 0x3b000000 0x00 0x400>, 1538 <0x00 0x50000000 0x00 0x8000000>; 1539 reg-names = "cfg", "data"; 1540 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1541 gpmc,num-cs = <3>; 1542 gpmc,num-waitpins = <2>; 1543 #address-cells = <2>; 1544 #size-cells = <1>; 1545 interrupt-controller; 1546 #interrupt-cells = <2>; 1547 gpio-controller; 1548 #gpio-cells = <2>; 1549 status = "disabled"; 1550 }; 1551 1552 elm0: ecc@25010000 { 1553 compatible = "ti,am64-elm"; 1554 reg = <0x00 0x25010000 0x00 0x2000>; 1555 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1556 power-domains = <&k3_pds 54 TI_SCI_PD_EXCLUSIVE>; 1557 clocks = <&k3_clks 54 0>; 1558 clock-names = "fck"; 1559 status = "disabled"; 1560 }; 1561 1562 main_vtm0: temperature-sensor@b00000 { 1563 compatible = "ti,j7200-vtm"; 1564 reg = <0x00 0xb00000 0x00 0x400>, 1565 <0x00 0xb01000 0x00 0x400>; 1566 power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>; 1567 #thermal-sensor-cells = <1>; 1568 }; 1569}; 1570