1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM642 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 oc_sram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x200000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x00 0x70000000 0x200000>; 15 16 atf-sram@0 { 17 reg = <0x0 0x1a000>; 18 }; 19 }; 20 21 gic500: interrupt-controller@1800000 { 22 compatible = "arm,gic-v3"; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 ranges; 26 #interrupt-cells = <3>; 27 interrupt-controller; 28 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 29 <0x00 0x01840000 0x00 0xC0000>; /* GICR */ 30 /* 31 * vcpumntirq: 32 * virtual CPU interface maintenance interrupt 33 */ 34 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 35 36 gic_its: msi-controller@1820000 { 37 compatible = "arm,gic-v3-its"; 38 reg = <0x00 0x01820000 0x00 0x10000>; 39 socionext,synquacer-pre-its = <0x1000000 0x400000>; 40 msi-controller; 41 #msi-cells = <1>; 42 }; 43 }; 44 45 dmss: bus@48000000 { 46 compatible = "simple-mfd"; 47 #address-cells = <2>; 48 #size-cells = <2>; 49 dma-ranges; 50 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 51 52 ti,sci-dev-id = <25>; 53 54 secure_proxy_main: mailbox@4d000000 { 55 compatible = "ti,am654-secure-proxy"; 56 #mbox-cells = <1>; 57 reg-names = "target_data", "rt", "scfg"; 58 reg = <0x00 0x4d000000 0x00 0x80000>, 59 <0x00 0x4a600000 0x00 0x80000>, 60 <0x00 0x4a400000 0x00 0x80000>; 61 interrupt-names = "rx_012"; 62 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 63 }; 64 65 inta_main_dmss: interrupt-controller@48000000 { 66 compatible = "ti,sci-inta"; 67 reg = <0x00 0x48000000 0x00 0x100000>; 68 #interrupt-cells = <0>; 69 interrupt-controller; 70 interrupt-parent = <&gic500>; 71 msi-controller; 72 ti,sci = <&dmsc>; 73 ti,sci-dev-id = <28>; 74 ti,interrupt-ranges = <4 68 36>; 75 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 76 }; 77 78 main_bcdma: dma-controller@485c0100 { 79 compatible = "ti,am64-dmss-bcdma"; 80 reg = <0x00 0x485c0100 0x00 0x100>, 81 <0x00 0x4c000000 0x00 0x20000>, 82 <0x00 0x4a820000 0x00 0x20000>, 83 <0x00 0x4aa40000 0x00 0x20000>, 84 <0x00 0x4bc00000 0x00 0x100000>; 85 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; 86 msi-parent = <&inta_main_dmss>; 87 #dma-cells = <3>; 88 89 ti,sci = <&dmsc>; 90 ti,sci-dev-id = <26>; 91 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 92 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 93 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 94 }; 95 96 main_pktdma: dma-controller@485c0000 { 97 compatible = "ti,am64-dmss-pktdma"; 98 reg = <0x00 0x485c0000 0x00 0x100>, 99 <0x00 0x4a800000 0x00 0x20000>, 100 <0x00 0x4aa00000 0x00 0x40000>, 101 <0x00 0x4b800000 0x00 0x400000>; 102 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 103 msi-parent = <&inta_main_dmss>; 104 #dma-cells = <2>; 105 106 ti,sci = <&dmsc>; 107 ti,sci-dev-id = <30>; 108 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 109 <0x24>, /* CPSW_TX_CHAN */ 110 <0x25>, /* SAUL_TX_0_CHAN */ 111 <0x26>, /* SAUL_TX_1_CHAN */ 112 <0x27>, /* ICSSG_0_TX_CHAN */ 113 <0x28>; /* ICSSG_1_TX_CHAN */ 114 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 115 <0x11>, /* RING_CPSW_TX_CHAN */ 116 <0x12>, /* RING_SAUL_TX_0_CHAN */ 117 <0x13>, /* RING_SAUL_TX_1_CHAN */ 118 <0x14>, /* RING_ICSSG_0_TX_CHAN */ 119 <0x15>; /* RING_ICSSG_1_TX_CHAN */ 120 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 121 <0x2b>, /* CPSW_RX_CHAN */ 122 <0x2d>, /* SAUL_RX_0_CHAN */ 123 <0x2f>, /* SAUL_RX_1_CHAN */ 124 <0x31>, /* SAUL_RX_2_CHAN */ 125 <0x33>, /* SAUL_RX_3_CHAN */ 126 <0x35>, /* ICSSG_0_RX_CHAN */ 127 <0x37>; /* ICSSG_1_RX_CHAN */ 128 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 129 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 130 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 131 <0x32>, /* FLOW_SAUL_RX_2/3_CHAN */ 132 <0x36>, /* FLOW_ICSSG_0_RX_CHAN */ 133 <0x38>; /* FLOW_ICSSG_1_RX_CHAN */ 134 }; 135 }; 136 137 dmsc: system-controller@44043000 { 138 compatible = "ti,k2g-sci"; 139 ti,host-id = <12>; 140 mbox-names = "rx", "tx"; 141 mboxes= <&secure_proxy_main 12>, 142 <&secure_proxy_main 13>; 143 reg-names = "debug_messages"; 144 reg = <0x00 0x44043000 0x00 0xfe0>; 145 146 k3_pds: power-controller { 147 compatible = "ti,sci-pm-domain"; 148 #power-domain-cells = <2>; 149 }; 150 151 k3_clks: clock-controller { 152 compatible = "ti,k2g-sci-clk"; 153 #clock-cells = <2>; 154 }; 155 156 k3_reset: reset-controller { 157 compatible = "ti,sci-reset"; 158 #reset-cells = <2>; 159 }; 160 }; 161 162 main_pmx0: pinctrl@f4000 { 163 compatible = "pinctrl-single"; 164 reg = <0x00 0xf4000 0x00 0x2d0>; 165 #pinctrl-cells = <1>; 166 pinctrl-single,register-width = <32>; 167 pinctrl-single,function-mask = <0xffffffff>; 168 }; 169 170 main_conf: syscon@43000000 { 171 compatible = "syscon", "simple-mfd"; 172 reg = <0x00 0x43000000 0x00 0x20000>; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 ranges = <0x00 0x00 0x43000000 0x20000>; 176 177 chipid@14 { 178 compatible = "ti,am654-chipid"; 179 reg = <0x00000014 0x4>; 180 }; 181 182 phy_gmii_sel: phy@4044 { 183 compatible = "ti,am654-phy-gmii-sel"; 184 reg = <0x4044 0x8>; 185 #phy-cells = <1>; 186 }; 187 }; 188 189 main_uart0: serial@2800000 { 190 compatible = "ti,am64-uart", "ti,am654-uart"; 191 reg = <0x00 0x02800000 0x00 0x100>; 192 reg-shift = <2>; 193 reg-io-width = <4>; 194 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 195 clock-frequency = <48000000>; 196 current-speed = <115200>; 197 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 198 clocks = <&k3_clks 146 0>; 199 clock-names = "fclk"; 200 }; 201 202 main_uart1: serial@2810000 { 203 compatible = "ti,am64-uart", "ti,am654-uart"; 204 reg = <0x00 0x02810000 0x00 0x100>; 205 reg-shift = <2>; 206 reg-io-width = <4>; 207 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 208 clock-frequency = <48000000>; 209 current-speed = <115200>; 210 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 211 clocks = <&k3_clks 152 0>; 212 clock-names = "fclk"; 213 }; 214 215 main_uart2: serial@2820000 { 216 compatible = "ti,am64-uart", "ti,am654-uart"; 217 reg = <0x00 0x02820000 0x00 0x100>; 218 reg-shift = <2>; 219 reg-io-width = <4>; 220 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 221 clock-frequency = <48000000>; 222 current-speed = <115200>; 223 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 224 clocks = <&k3_clks 153 0>; 225 clock-names = "fclk"; 226 }; 227 228 main_uart3: serial@2830000 { 229 compatible = "ti,am64-uart", "ti,am654-uart"; 230 reg = <0x00 0x02830000 0x00 0x100>; 231 reg-shift = <2>; 232 reg-io-width = <4>; 233 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 234 clock-frequency = <48000000>; 235 current-speed = <115200>; 236 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 237 clocks = <&k3_clks 154 0>; 238 clock-names = "fclk"; 239 }; 240 241 main_uart4: serial@2840000 { 242 compatible = "ti,am64-uart", "ti,am654-uart"; 243 reg = <0x00 0x02840000 0x00 0x100>; 244 reg-shift = <2>; 245 reg-io-width = <4>; 246 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 247 clock-frequency = <48000000>; 248 current-speed = <115200>; 249 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 250 clocks = <&k3_clks 155 0>; 251 clock-names = "fclk"; 252 }; 253 254 main_uart5: serial@2850000 { 255 compatible = "ti,am64-uart", "ti,am654-uart"; 256 reg = <0x00 0x02850000 0x00 0x100>; 257 reg-shift = <2>; 258 reg-io-width = <4>; 259 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 260 clock-frequency = <48000000>; 261 current-speed = <115200>; 262 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 263 clocks = <&k3_clks 156 0>; 264 clock-names = "fclk"; 265 }; 266 267 main_uart6: serial@2860000 { 268 compatible = "ti,am64-uart", "ti,am654-uart"; 269 reg = <0x00 0x02860000 0x00 0x100>; 270 reg-shift = <2>; 271 reg-io-width = <4>; 272 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 273 clock-frequency = <48000000>; 274 current-speed = <115200>; 275 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 276 clocks = <&k3_clks 158 0>; 277 clock-names = "fclk"; 278 }; 279 280 main_i2c0: i2c@20000000 { 281 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 282 reg = <0x00 0x20000000 0x00 0x100>; 283 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 287 clocks = <&k3_clks 102 2>; 288 clock-names = "fck"; 289 }; 290 291 main_i2c1: i2c@20010000 { 292 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 293 reg = <0x00 0x20010000 0x00 0x100>; 294 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 295 #address-cells = <1>; 296 #size-cells = <0>; 297 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 298 clocks = <&k3_clks 103 2>; 299 clock-names = "fck"; 300 }; 301 302 main_i2c2: i2c@20020000 { 303 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 304 reg = <0x00 0x20020000 0x00 0x100>; 305 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 306 #address-cells = <1>; 307 #size-cells = <0>; 308 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 309 clocks = <&k3_clks 104 2>; 310 clock-names = "fck"; 311 }; 312 313 main_i2c3: i2c@20030000 { 314 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 315 reg = <0x00 0x20030000 0x00 0x100>; 316 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 320 clocks = <&k3_clks 105 2>; 321 clock-names = "fck"; 322 }; 323 324 main_spi0: spi@20100000 { 325 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 326 reg = <0x00 0x20100000 0x00 0x400>; 327 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 328 #address-cells = <1>; 329 #size-cells = <0>; 330 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 331 clocks = <&k3_clks 141 0>; 332 dmas = <&main_pktdma 0xc300 0>, <&main_pktdma 0x4300 0>; 333 dma-names = "tx0", "rx0"; 334 }; 335 336 main_spi1: spi@20110000 { 337 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 338 reg = <0x00 0x20110000 0x00 0x400>; 339 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 340 #address-cells = <1>; 341 #size-cells = <0>; 342 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 343 clocks = <&k3_clks 142 0>; 344 }; 345 346 main_spi2: spi@20120000 { 347 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 348 reg = <0x00 0x20120000 0x00 0x400>; 349 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 353 clocks = <&k3_clks 143 0>; 354 }; 355 356 main_spi3: spi@20130000 { 357 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 358 reg = <0x00 0x20130000 0x00 0x400>; 359 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 363 clocks = <&k3_clks 144 0>; 364 }; 365 366 main_spi4: spi@20140000 { 367 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 368 reg = <0x00 0x20140000 0x00 0x400>; 369 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 370 #address-cells = <1>; 371 #size-cells = <0>; 372 power-domains = <&k3_pds 145 TI_SCI_PD_EXCLUSIVE>; 373 clocks = <&k3_clks 145 0>; 374 }; 375 376 main_gpio_intr: interrupt-controller@a00000 { 377 compatible = "ti,sci-intr"; 378 reg = <0x00 0x00a00000 0x00 0x800>; 379 ti,intr-trigger-type = <1>; 380 interrupt-controller; 381 interrupt-parent = <&gic500>; 382 #interrupt-cells = <1>; 383 ti,sci = <&dmsc>; 384 ti,sci-dev-id = <3>; 385 ti,interrupt-ranges = <0 32 16>; 386 }; 387 388 main_gpio0: gpio@600000 { 389 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 390 reg = <0x0 0x00600000 0x0 0x100>; 391 gpio-controller; 392 #gpio-cells = <2>; 393 interrupt-parent = <&main_gpio_intr>; 394 interrupts = <190>, <191>, <192>, 395 <193>, <194>, <195>; 396 interrupt-controller; 397 #interrupt-cells = <2>; 398 ti,ngpio = <87>; 399 ti,davinci-gpio-unbanked = <0>; 400 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 401 clocks = <&k3_clks 77 0>; 402 clock-names = "gpio"; 403 }; 404 405 main_gpio1: gpio@601000 { 406 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 407 reg = <0x0 0x00601000 0x0 0x100>; 408 gpio-controller; 409 #gpio-cells = <2>; 410 interrupt-parent = <&main_gpio_intr>; 411 interrupts = <180>, <181>, <182>, 412 <183>, <184>, <185>; 413 interrupt-controller; 414 #interrupt-cells = <2>; 415 ti,ngpio = <88>; 416 ti,davinci-gpio-unbanked = <0>; 417 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 418 clocks = <&k3_clks 78 0>; 419 clock-names = "gpio"; 420 }; 421 422 sdhci0: mmc@fa10000 { 423 compatible = "ti,am64-sdhci-8bit"; 424 reg = <0x00 0xfa10000 0x00 0x260>, <0x00 0xfa18000 0x00 0x134>; 425 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 426 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 427 clocks = <&k3_clks 57 0>, <&k3_clks 57 1>; 428 clock-names = "clk_ahb", "clk_xin"; 429 mmc-ddr-1_8v; 430 mmc-hs200-1_8v; 431 mmc-hs400-1_8v; 432 ti,trm-icp = <0x2>; 433 ti,otap-del-sel-legacy = <0x0>; 434 ti,otap-del-sel-mmc-hs = <0x0>; 435 ti,otap-del-sel-ddr52 = <0x6>; 436 ti,otap-del-sel-hs200 = <0x7>; 437 ti,otap-del-sel-hs400 = <0x4>; 438 }; 439 440 sdhci1: mmc@fa00000 { 441 compatible = "ti,am64-sdhci-4bit"; 442 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; 443 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 444 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 445 clocks = <&k3_clks 58 3>, <&k3_clks 58 4>; 446 clock-names = "clk_ahb", "clk_xin"; 447 ti,trm-icp = <0x2>; 448 ti,otap-del-sel-legacy = <0x0>; 449 ti,otap-del-sel-sd-hs = <0xf>; 450 ti,otap-del-sel-sdr12 = <0xf>; 451 ti,otap-del-sel-sdr25 = <0xf>; 452 ti,otap-del-sel-sdr50 = <0xc>; 453 ti,otap-del-sel-sdr104 = <0x6>; 454 ti,otap-del-sel-ddr50 = <0x9>; 455 ti,clkbuf-sel = <0x7>; 456 }; 457 458 cpsw3g: ethernet@8000000 { 459 compatible = "ti,am642-cpsw-nuss"; 460 #address-cells = <2>; 461 #size-cells = <2>; 462 reg = <0x0 0x8000000 0x0 0x200000>; 463 reg-names = "cpsw_nuss"; 464 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; 465 clocks = <&k3_clks 13 0>; 466 assigned-clocks = <&k3_clks 13 1>; 467 assigned-clock-parents = <&k3_clks 13 9>; 468 clock-names = "fck"; 469 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 470 471 dmas = <&main_pktdma 0xC500 15>, 472 <&main_pktdma 0xC501 15>, 473 <&main_pktdma 0xC502 15>, 474 <&main_pktdma 0xC503 15>, 475 <&main_pktdma 0xC504 15>, 476 <&main_pktdma 0xC505 15>, 477 <&main_pktdma 0xC506 15>, 478 <&main_pktdma 0xC507 15>, 479 <&main_pktdma 0x4500 15>; 480 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 481 "tx7", "rx"; 482 483 ethernet-ports { 484 #address-cells = <1>; 485 #size-cells = <0>; 486 487 cpsw_port1: port@1 { 488 reg = <1>; 489 ti,mac-only; 490 label = "port1"; 491 phys = <&phy_gmii_sel 1>; 492 mac-address = [00 00 de ad be ef]; 493 }; 494 495 cpsw_port2: port@2 { 496 reg = <2>; 497 ti,mac-only; 498 label = "port2"; 499 phys = <&phy_gmii_sel 2>; 500 mac-address = [00 01 de ad be ef]; 501 }; 502 }; 503 504 cpsw3g_mdio: mdio@f00 { 505 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 506 reg = <0x0 0xf00 0x0 0x100>; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 clocks = <&k3_clks 13 0>; 510 clock-names = "fck"; 511 bus_freq = <1000000>; 512 }; 513 514 cpts@3d000 { 515 compatible = "ti,j721e-cpts"; 516 reg = <0x0 0x3d000 0x0 0x400>; 517 clocks = <&k3_clks 13 1>; 518 clock-names = "cpts"; 519 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 520 interrupt-names = "cpts"; 521 ti,cpts-ext-ts-inputs = <4>; 522 ti,cpts-periodic-outputs = <2>; 523 }; 524 }; 525 526 cpts@39000000 { 527 compatible = "ti,j721e-cpts"; 528 reg = <0x0 0x39000000 0x0 0x400>; 529 reg-names = "cpts"; 530 power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; 531 clocks = <&k3_clks 84 0>; 532 clock-names = "cpts"; 533 assigned-clocks = <&k3_clks 84 0>; 534 assigned-clock-parents = <&k3_clks 84 8>; 535 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 536 interrupt-names = "cpts"; 537 ti,cpts-periodic-outputs = <6>; 538 ti,cpts-ext-ts-inputs = <8>; 539 }; 540 541 usbss0: cdns-usb@f900000{ 542 compatible = "ti,am64-usb"; 543 reg = <0x00 0xf900000 0x00 0x100>; 544 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 545 clocks = <&k3_clks 161 9>, <&k3_clks 161 1>; 546 clock-names = "ref", "lpm"; 547 assigned-clocks = <&k3_clks 161 9>; /* USB2_REFCLK */ 548 assigned-clock-parents = <&k3_clks 161 10>; /* HF0SC0 */ 549 #address-cells = <2>; 550 #size-cells = <2>; 551 ranges; 552 usb0: usb@f400000{ 553 compatible = "cdns,usb3"; 554 reg = <0x00 0xf400000 0x00 0x10000>, 555 <0x00 0xf410000 0x00 0x10000>, 556 <0x00 0xf420000 0x00 0x10000>; 557 reg-names = "otg", 558 "xhci", 559 "dev"; 560 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 561 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */ 562 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */ 563 interrupt-names = "host", 564 "peripheral", 565 "otg"; 566 maximum-speed = "super-speed"; 567 dr_mode = "otg"; 568 }; 569 }; 570 571 tscadc0: tscadc@28001000 { 572 compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 573 reg = <0x00 0x28001000 0x00 0x1000>; 574 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 575 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 576 clocks = <&k3_clks 0 0>; 577 assigned-clocks = <&k3_clks 0 0>; 578 assigned-clock-parents = <&k3_clks 0 3>; 579 assigned-clock-rates = <60000000>; 580 clock-names = "adc_tsc_fck"; 581 582 adc { 583 #io-channel-cells = <1>; 584 compatible = "ti,am654-adc", "ti,am3359-adc"; 585 }; 586 }; 587 588 fss: bus@fc00000 { 589 compatible = "simple-bus"; 590 reg = <0x00 0x0fc00000 0x00 0x70000>; 591 #address-cells = <2>; 592 #size-cells = <2>; 593 ranges; 594 595 ospi0: spi@fc40000 { 596 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 597 reg = <0x00 0x0fc40000 0x00 0x100>, 598 <0x05 0x00000000 0x01 0x00000000>; 599 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 600 cdns,fifo-depth = <256>; 601 cdns,fifo-width = <4>; 602 cdns,trigger-address = <0x0>; 603 #address-cells = <0x1>; 604 #size-cells = <0x0>; 605 clocks = <&k3_clks 75 6>; 606 assigned-clocks = <&k3_clks 75 6>; 607 assigned-clock-parents = <&k3_clks 75 7>; 608 assigned-clock-rates = <166666666>; 609 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 610 }; 611 }; 612 613 hwspinlock: spinlock@2a000000 { 614 compatible = "ti,am64-hwspinlock"; 615 reg = <0x00 0x2a000000 0x00 0x1000>; 616 #hwlock-cells = <1>; 617 }; 618 619 mailbox0_cluster2: mailbox@29020000 { 620 compatible = "ti,am64-mailbox"; 621 reg = <0x00 0x29020000 0x00 0x200>; 622 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 624 #mbox-cells = <1>; 625 ti,mbox-num-users = <4>; 626 ti,mbox-num-fifos = <16>; 627 }; 628 629 mailbox0_cluster3: mailbox@29030000 { 630 compatible = "ti,am64-mailbox"; 631 reg = <0x00 0x29030000 0x00 0x200>; 632 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 633 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 634 #mbox-cells = <1>; 635 ti,mbox-num-users = <4>; 636 ti,mbox-num-fifos = <16>; 637 }; 638 639 mailbox0_cluster4: mailbox@29040000 { 640 compatible = "ti,am64-mailbox"; 641 reg = <0x00 0x29040000 0x00 0x200>; 642 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 644 #mbox-cells = <1>; 645 ti,mbox-num-users = <4>; 646 ti,mbox-num-fifos = <16>; 647 }; 648 649 mailbox0_cluster5: mailbox@29050000 { 650 compatible = "ti,am64-mailbox"; 651 reg = <0x00 0x29050000 0x00 0x200>; 652 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 654 #mbox-cells = <1>; 655 ti,mbox-num-users = <4>; 656 ti,mbox-num-fifos = <16>; 657 }; 658 659 mailbox0_cluster6: mailbox@29060000 { 660 compatible = "ti,am64-mailbox"; 661 reg = <0x00 0x29060000 0x00 0x200>; 662 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 663 #mbox-cells = <1>; 664 ti,mbox-num-users = <4>; 665 ti,mbox-num-fifos = <16>; 666 }; 667 668 mailbox0_cluster7: mailbox@29070000 { 669 compatible = "ti,am64-mailbox"; 670 reg = <0x00 0x29070000 0x00 0x200>; 671 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 672 #mbox-cells = <1>; 673 ti,mbox-num-users = <4>; 674 ti,mbox-num-fifos = <16>; 675 }; 676}; 677