1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree file for the AM62P main domain peripherals 4 * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 5 */ 6 7&cbass_main { 8 oc_sram: sram@70000000 { 9 compatible = "mmio-sram"; 10 reg = <0x00 0x70000000 0x00 0x10000>; 11 #address-cells = <1>; 12 #size-cells = <1>; 13 ranges = <0x00 0x00 0x70000000 0x10000>; 14 }; 15 16 gic500: interrupt-controller@1800000 { 17 compatible = "arm,gic-v3"; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 ranges; 21 #interrupt-cells = <3>; 22 interrupt-controller; 23 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 24 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 25 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 26 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 27 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 28 /* 29 * vcpumntirq: 30 * virtual CPU interface maintenance interrupt 31 */ 32 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 33 34 gic_its: msi-controller@1820000 { 35 compatible = "arm,gic-v3-its"; 36 reg = <0x00 0x01820000 0x00 0x10000>; 37 socionext,synquacer-pre-its = <0x1000000 0x400000>; 38 msi-controller; 39 #msi-cells = <1>; 40 }; 41 }; 42 43 main_conf: bus@100000 { 44 compatible = "simple-bus"; 45 reg = <0x00 0x00100000 0x00 0x20000>; 46 #address-cells = <1>; 47 #size-cells = <1>; 48 ranges = <0x00 0x00 0x00100000 0x20000>; 49 50 phy_gmii_sel: phy@4044 { 51 compatible = "ti,am654-phy-gmii-sel"; 52 reg = <0x4044 0x8>; 53 #phy-cells = <1>; 54 }; 55 56 epwm_tbclk: clock-controller@4130 { 57 compatible = "ti,am62-epwm-tbclk"; 58 reg = <0x4130 0x4>; 59 #clock-cells = <1>; 60 }; 61 }; 62 63 dmss: bus@48000000 { 64 compatible = "simple-bus"; 65 #address-cells = <2>; 66 #size-cells = <2>; 67 dma-ranges; 68 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 69 bootph-all; 70 71 ti,sci-dev-id = <25>; 72 73 secure_proxy_main: mailbox@4d000000 { 74 compatible = "ti,am654-secure-proxy"; 75 #mbox-cells = <1>; 76 reg-names = "target_data", "rt", "scfg"; 77 reg = <0x00 0x4d000000 0x00 0x80000>, 78 <0x00 0x4a600000 0x00 0x80000>, 79 <0x00 0x4a400000 0x00 0x80000>; 80 interrupt-names = "rx_012"; 81 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 82 bootph-all; 83 }; 84 85 inta_main_dmss: interrupt-controller@48000000 { 86 compatible = "ti,sci-inta"; 87 reg = <0x00 0x48000000 0x00 0x100000>; 88 #interrupt-cells = <0>; 89 interrupt-controller; 90 interrupt-parent = <&gic500>; 91 msi-controller; 92 ti,sci = <&dmsc>; 93 ti,sci-dev-id = <28>; 94 ti,interrupt-ranges = <5 69 35>; 95 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 96 }; 97 98 main_bcdma: dma-controller@485c0100 { 99 compatible = "ti,am64-dmss-bcdma"; 100 reg = <0x00 0x485c0100 0x00 0x100>, 101 <0x00 0x4c000000 0x00 0x20000>, 102 <0x00 0x4a820000 0x00 0x20000>, 103 <0x00 0x4aa40000 0x00 0x20000>, 104 <0x00 0x4bc00000 0x00 0x100000>, 105 <0x00 0x48600000 0x00 0x8000>, 106 <0x00 0x484a4000 0x00 0x2000>, 107 <0x00 0x484c2000 0x00 0x2000>, 108 <0x00 0x48420000 0x00 0x2000>; 109 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt", 110 "ring", "tchan", "rchan", "bchan"; 111 msi-parent = <&inta_main_dmss>; 112 #dma-cells = <3>; 113 114 ti,sci = <&dmsc>; 115 ti,sci-dev-id = <26>; 116 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 117 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 118 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 119 bootph-all; 120 }; 121 122 main_pktdma: dma-controller@485c0000 { 123 compatible = "ti,am64-dmss-pktdma"; 124 reg = <0x00 0x485c0000 0x00 0x100>, 125 <0x00 0x4a800000 0x00 0x20000>, 126 <0x00 0x4aa00000 0x00 0x40000>, 127 <0x00 0x4b800000 0x00 0x400000>, 128 <0x00 0x485e0000 0x00 0x10000>, 129 <0x00 0x484a0000 0x00 0x2000>, 130 <0x00 0x484c0000 0x00 0x2000>, 131 <0x00 0x48430000 0x00 0x1000>; 132 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt", 133 "ring", "tchan", "rchan", "rflow"; 134 msi-parent = <&inta_main_dmss>; 135 #dma-cells = <2>; 136 bootph-all; 137 138 ti,sci = <&dmsc>; 139 ti,sci-dev-id = <30>; 140 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 141 <0x24>, /* CPSW_TX_CHAN */ 142 <0x25>, /* SAUL_TX_0_CHAN */ 143 <0x26>; /* SAUL_TX_1_CHAN */ 144 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 145 <0x11>, /* RING_CPSW_TX_CHAN */ 146 <0x12>, /* RING_SAUL_TX_0_CHAN */ 147 <0x13>; /* RING_SAUL_TX_1_CHAN */ 148 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 149 <0x2b>, /* CPSW_RX_CHAN */ 150 <0x2d>, /* SAUL_RX_0_CHAN */ 151 <0x2f>, /* SAUL_RX_1_CHAN */ 152 <0x31>, /* SAUL_RX_2_CHAN */ 153 <0x33>; /* SAUL_RX_3_CHAN */ 154 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 155 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 156 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 157 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ 158 }; 159 }; 160 161 dmsc: system-controller@44043000 { 162 compatible = "ti,k2g-sci"; 163 ti,host-id = <12>; 164 mbox-names = "rx", "tx"; 165 mboxes = <&secure_proxy_main 12>, 166 <&secure_proxy_main 13>; 167 reg-names = "debug_messages"; 168 reg = <0x00 0x44043000 0x00 0xfe0>; 169 bootph-all; 170 171 k3_pds: power-controller { 172 compatible = "ti,sci-pm-domain"; 173 #power-domain-cells = <2>; 174 bootph-all; 175 }; 176 177 k3_clks: clock-controller { 178 compatible = "ti,k2g-sci-clk"; 179 #clock-cells = <2>; 180 bootph-all; 181 }; 182 183 k3_reset: reset-controller { 184 compatible = "ti,sci-reset"; 185 #reset-cells = <2>; 186 bootph-all; 187 }; 188 }; 189 190 crypto: crypto@40900000 { 191 compatible = "ti,am62-sa3ul"; 192 reg = <0x00 0x40900000 0x00 0x1200>; 193 #address-cells = <2>; 194 #size-cells = <2>; 195 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 196 197 dmas = <&main_pktdma 0xf501 0>, <&main_pktdma 0x7506 0>, 198 <&main_pktdma 0x7507 0>; 199 dma-names = "tx", "rx1", "rx2"; 200 }; 201 202 secure_proxy_sa3: mailbox@43600000 { 203 compatible = "ti,am654-secure-proxy"; 204 #mbox-cells = <1>; 205 reg-names = "target_data", "rt", "scfg"; 206 reg = <0x00 0x43600000 0x00 0x10000>, 207 <0x00 0x44880000 0x00 0x20000>, 208 <0x00 0x44860000 0x00 0x20000>; 209 /* 210 * Marked Disabled: 211 * Node is incomplete as it is meant for bootloaders and 212 * firmware on non-MPU processors 213 */ 214 status = "disabled"; 215 bootph-all; 216 }; 217 218 main_pmx0: pinctrl@f4000 { 219 compatible = "pinctrl-single"; 220 reg = <0x00 0xf4000 0x00 0x2ac>; 221 #pinctrl-cells = <1>; 222 pinctrl-single,register-width = <32>; 223 pinctrl-single,function-mask = <0xffffffff>; 224 bootph-all; 225 }; 226 227 main_esm: esm@420000 { 228 compatible = "ti,j721e-esm"; 229 reg = <0x00 0x420000 0x00 0x1000>; 230 ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>; 231 bootph-pre-ram; 232 }; 233 234 main_timer0: timer@2400000 { 235 compatible = "ti,am654-timer"; 236 reg = <0x00 0x2400000 0x00 0x400>; 237 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&k3_clks 36 2>; 239 clock-names = "fck"; 240 assigned-clocks = <&k3_clks 36 2>; 241 assigned-clock-parents = <&k3_clks 36 3>; 242 power-domains = <&k3_pds 36 TI_SCI_PD_EXCLUSIVE>; 243 ti,timer-pwm; 244 bootph-all; 245 }; 246 247 main_timer1: timer@2410000 { 248 compatible = "ti,am654-timer"; 249 reg = <0x00 0x2410000 0x00 0x400>; 250 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&k3_clks 37 2>; 252 clock-names = "fck"; 253 assigned-clocks = <&k3_clks 37 2>; 254 assigned-clock-parents = <&k3_clks 37 3>; 255 power-domains = <&k3_pds 37 TI_SCI_PD_EXCLUSIVE>; 256 ti,timer-pwm; 257 }; 258 259 main_timer2: timer@2420000 { 260 compatible = "ti,am654-timer"; 261 reg = <0x00 0x2420000 0x00 0x400>; 262 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&k3_clks 38 2>; 264 clock-names = "fck"; 265 assigned-clocks = <&k3_clks 38 2>; 266 assigned-clock-parents = <&k3_clks 38 3>; 267 power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; 268 ti,timer-pwm; 269 }; 270 271 main_timer3: timer@2430000 { 272 compatible = "ti,am654-timer"; 273 reg = <0x00 0x2430000 0x00 0x400>; 274 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&k3_clks 39 2>; 276 clock-names = "fck"; 277 assigned-clocks = <&k3_clks 39 2>; 278 assigned-clock-parents = <&k3_clks 39 3>; 279 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 280 ti,timer-pwm; 281 }; 282 283 main_timer4: timer@2440000 { 284 compatible = "ti,am654-timer"; 285 reg = <0x00 0x2440000 0x00 0x400>; 286 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 287 clocks = <&k3_clks 40 2>; 288 clock-names = "fck"; 289 assigned-clocks = <&k3_clks 40 2>; 290 assigned-clock-parents = <&k3_clks 40 3>; 291 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 292 ti,timer-pwm; 293 }; 294 295 main_timer5: timer@2450000 { 296 compatible = "ti,am654-timer"; 297 reg = <0x00 0x2450000 0x00 0x400>; 298 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&k3_clks 41 2>; 300 clock-names = "fck"; 301 assigned-clocks = <&k3_clks 41 2>; 302 assigned-clock-parents = <&k3_clks 41 3>; 303 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 304 ti,timer-pwm; 305 }; 306 307 main_timer6: timer@2460000 { 308 compatible = "ti,am654-timer"; 309 reg = <0x00 0x2460000 0x00 0x400>; 310 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&k3_clks 42 2>; 312 clock-names = "fck"; 313 assigned-clocks = <&k3_clks 42 2>; 314 assigned-clock-parents = <&k3_clks 42 3>; 315 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 316 ti,timer-pwm; 317 }; 318 319 main_timer7: timer@2470000 { 320 compatible = "ti,am654-timer"; 321 reg = <0x00 0x2470000 0x00 0x400>; 322 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&k3_clks 43 2>; 324 clock-names = "fck"; 325 assigned-clocks = <&k3_clks 43 2>; 326 assigned-clock-parents = <&k3_clks 43 3>; 327 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 328 ti,timer-pwm; 329 }; 330 331 main_uart0: serial@2800000 { 332 compatible = "ti,am64-uart", "ti,am654-uart"; 333 reg = <0x00 0x02800000 0x00 0x100>; 334 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 335 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 336 clocks = <&k3_clks 146 0>; 337 clock-names = "fclk"; 338 status = "disabled"; 339 }; 340 341 main_uart1: serial@2810000 { 342 compatible = "ti,am64-uart", "ti,am654-uart"; 343 reg = <0x00 0x02810000 0x00 0x100>; 344 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 345 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 346 clocks = <&k3_clks 152 0>; 347 clock-names = "fclk"; 348 status = "disabled"; 349 }; 350 351 main_uart2: serial@2820000 { 352 compatible = "ti,am64-uart", "ti,am654-uart"; 353 reg = <0x00 0x02820000 0x00 0x100>; 354 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 355 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 356 clocks = <&k3_clks 153 0>; 357 clock-names = "fclk"; 358 status = "disabled"; 359 }; 360 361 main_uart3: serial@2830000 { 362 compatible = "ti,am64-uart", "ti,am654-uart"; 363 reg = <0x00 0x02830000 0x00 0x100>; 364 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 365 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 366 clocks = <&k3_clks 154 0>; 367 clock-names = "fclk"; 368 status = "disabled"; 369 }; 370 371 main_uart4: serial@2840000 { 372 compatible = "ti,am64-uart", "ti,am654-uart"; 373 reg = <0x00 0x02840000 0x00 0x100>; 374 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 375 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 376 clocks = <&k3_clks 155 0>; 377 clock-names = "fclk"; 378 status = "disabled"; 379 }; 380 381 main_uart5: serial@2850000 { 382 compatible = "ti,am64-uart", "ti,am654-uart"; 383 reg = <0x00 0x02850000 0x00 0x100>; 384 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 385 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 386 clocks = <&k3_clks 156 0>; 387 clock-names = "fclk"; 388 status = "disabled"; 389 }; 390 391 main_uart6: serial@2860000 { 392 compatible = "ti,am64-uart", "ti,am654-uart"; 393 reg = <0x00 0x02860000 0x00 0x100>; 394 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 395 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 396 clocks = <&k3_clks 158 0>; 397 clock-names = "fclk"; 398 status = "disabled"; 399 }; 400 401 main_i2c0: i2c@20000000 { 402 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 403 reg = <0x00 0x20000000 0x00 0x100>; 404 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 408 clocks = <&k3_clks 102 2>; 409 clock-names = "fck"; 410 status = "disabled"; 411 }; 412 413 main_i2c1: i2c@20010000 { 414 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 415 reg = <0x00 0x20010000 0x00 0x100>; 416 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 420 clocks = <&k3_clks 103 2>; 421 clock-names = "fck"; 422 status = "disabled"; 423 }; 424 425 main_i2c2: i2c@20020000 { 426 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 427 reg = <0x00 0x20020000 0x00 0x100>; 428 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 432 clocks = <&k3_clks 104 2>; 433 clock-names = "fck"; 434 status = "disabled"; 435 }; 436 437 main_i2c3: i2c@20030000 { 438 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 439 reg = <0x00 0x20030000 0x00 0x100>; 440 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 441 #address-cells = <1>; 442 #size-cells = <0>; 443 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 444 clocks = <&k3_clks 105 2>; 445 clock-names = "fck"; 446 status = "disabled"; 447 }; 448 449 main_spi0: spi@20100000 { 450 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 451 reg = <0x00 0x20100000 0x00 0x400>; 452 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 456 clocks = <&k3_clks 141 0>; 457 status = "disabled"; 458 }; 459 460 main_spi1: spi@20110000 { 461 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 462 reg = <0x00 0x20110000 0x00 0x400>; 463 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 467 clocks = <&k3_clks 142 0>; 468 status = "disabled"; 469 }; 470 471 main_spi2: spi@20120000 { 472 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 473 reg = <0x00 0x20120000 0x00 0x400>; 474 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 475 #address-cells = <1>; 476 #size-cells = <0>; 477 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 478 clocks = <&k3_clks 143 0>; 479 status = "disabled"; 480 }; 481 482 main_gpio_intr: interrupt-controller@a00000 { 483 compatible = "ti,sci-intr"; 484 reg = <0x00 0x00a00000 0x00 0x800>; 485 ti,intr-trigger-type = <1>; 486 interrupt-controller; 487 interrupt-parent = <&gic500>; 488 #interrupt-cells = <1>; 489 ti,sci = <&dmsc>; 490 ti,sci-dev-id = <3>; 491 ti,interrupt-ranges = <0 32 16>; 492 }; 493 494 main_gpio0: gpio@600000 { 495 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 496 reg = <0x00 0x00600000 0x00 0x100>; 497 gpio-controller; 498 #gpio-cells = <2>; 499 interrupt-parent = <&main_gpio_intr>; 500 interrupts = <190>, <191>, <192>, 501 <193>, <194>, <195>; 502 interrupt-controller; 503 #interrupt-cells = <2>; 504 ti,ngpio = <92>; 505 ti,davinci-gpio-unbanked = <0>; 506 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 507 clocks = <&k3_clks 77 0>; 508 clock-names = "gpio"; 509 }; 510 511 main_gpio1: gpio@601000 { 512 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 513 reg = <0x00 0x00601000 0x00 0x100>; 514 gpio-controller; 515 #gpio-cells = <2>; 516 interrupt-parent = <&main_gpio_intr>; 517 interrupts = <180>, <181>, <182>, 518 <183>, <184>, <185>; 519 interrupt-controller; 520 #interrupt-cells = <2>; 521 ti,ngpio = <52>; 522 ti,davinci-gpio-unbanked = <0>; 523 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 524 clocks = <&k3_clks 78 0>; 525 clock-names = "gpio"; 526 }; 527 528 sdhci0: mmc@fa10000 { 529 compatible = "ti,am64-sdhci-8bit"; 530 reg = <0x00 0x0fa10000 0x00 0x1000>, <0x00 0x0fa18000 0x00 0x400>; 531 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 532 power-domains = <&k3_pds 57 TI_SCI_PD_EXCLUSIVE>; 533 clocks = <&k3_clks 57 1>, <&k3_clks 57 2>; 534 clock-names = "clk_ahb", "clk_xin"; 535 assigned-clocks = <&k3_clks 57 2>; 536 assigned-clock-parents = <&k3_clks 57 4>; 537 ti,otap-del-sel-legacy = <0x0>; 538 status = "disabled"; 539 }; 540 541 sdhci1: mmc@fa00000 { 542 compatible = "ti,am62-sdhci"; 543 reg = <0x00 0x0fa00000 0x00 0x1000>, <0x00 0x0fa08000 0x00 0x400>; 544 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 545 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 546 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; 547 clock-names = "clk_ahb", "clk_xin"; 548 ti,otap-del-sel-legacy = <0x8>; 549 status = "disabled"; 550 }; 551 552 sdhci2: mmc@fa20000 { 553 compatible = "ti,am62-sdhci"; 554 reg = <0x00 0x0fa20000 0x00 0x1000>, <0x00 0x0fa28000 0x00 0x400>; 555 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 556 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>; 557 clocks = <&k3_clks 184 5>, <&k3_clks 184 6>; 558 clock-names = "clk_ahb", "clk_xin"; 559 ti,otap-del-sel-legacy = <0x8>; 560 status = "disabled"; 561 }; 562 563 fss: bus@fc00000 { 564 compatible = "simple-bus"; 565 reg = <0x00 0x0fc00000 0x00 0x70000>; 566 #address-cells = <2>; 567 #size-cells = <2>; 568 ranges; 569 570 ospi0: spi@fc40000 { 571 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 572 reg = <0x00 0x0fc40000 0x00 0x100>, 573 <0x05 0x00000000 0x01 0x00000000>; 574 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 575 cdns,fifo-depth = <256>; 576 cdns,fifo-width = <4>; 577 cdns,trigger-address = <0x0>; 578 clocks = <&k3_clks 75 7>; 579 assigned-clocks = <&k3_clks 75 7>; 580 assigned-clock-parents = <&k3_clks 75 8>; 581 assigned-clock-rates = <166666666>; 582 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 583 #address-cells = <1>; 584 #size-cells = <0>; 585 status = "disabled"; 586 }; 587 }; 588 589 cpsw3g: ethernet@8000000 { 590 compatible = "ti,am642-cpsw-nuss"; 591 #address-cells = <2>; 592 #size-cells = <2>; 593 reg = <0x00 0x08000000 0x00 0x200000>; 594 reg-names = "cpsw_nuss"; 595 ranges = <0x00 0x00 0x00 0x08000000 0x00 0x200000>; 596 clocks = <&k3_clks 13 0>; 597 assigned-clocks = <&k3_clks 13 3>; 598 assigned-clock-parents = <&k3_clks 13 11>; 599 clock-names = "fck"; 600 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 601 602 dmas = <&main_pktdma 0xc600 15>, 603 <&main_pktdma 0xc601 15>, 604 <&main_pktdma 0xc602 15>, 605 <&main_pktdma 0xc603 15>, 606 <&main_pktdma 0xc604 15>, 607 <&main_pktdma 0xc605 15>, 608 <&main_pktdma 0xc606 15>, 609 <&main_pktdma 0xc607 15>, 610 <&main_pktdma 0x4600 15>; 611 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 612 "tx7", "rx"; 613 614 ethernet-ports { 615 #address-cells = <1>; 616 #size-cells = <0>; 617 618 cpsw_port1: port@1 { 619 reg = <1>; 620 ti,mac-only; 621 label = "port1"; 622 phys = <&phy_gmii_sel 1>; 623 mac-address = [00 00 00 00 00 00]; 624 }; 625 626 cpsw_port2: port@2 { 627 reg = <2>; 628 ti,mac-only; 629 label = "port2"; 630 phys = <&phy_gmii_sel 2>; 631 mac-address = [00 00 00 00 00 00]; 632 }; 633 }; 634 635 cpsw3g_mdio: mdio@f00 { 636 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 637 reg = <0x00 0xf00 0x00 0x100>; 638 #address-cells = <1>; 639 #size-cells = <0>; 640 clocks = <&k3_clks 13 0>; 641 clock-names = "fck"; 642 bus_freq = <1000000>; 643 status = "disabled"; 644 }; 645 646 cpts@3d000 { 647 compatible = "ti,j721e-cpts"; 648 reg = <0x00 0x3d000 0x00 0x400>; 649 clocks = <&k3_clks 13 3>; 650 clock-names = "cpts"; 651 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 652 interrupt-names = "cpts"; 653 ti,cpts-ext-ts-inputs = <4>; 654 ti,cpts-periodic-outputs = <2>; 655 }; 656 }; 657 658 hwspinlock: spinlock@2a000000 { 659 compatible = "ti,am64-hwspinlock"; 660 reg = <0x00 0x2a000000 0x00 0x1000>; 661 #hwlock-cells = <1>; 662 }; 663 664 mailbox0_cluster0: mailbox@29000000 { 665 compatible = "ti,am64-mailbox"; 666 reg = <0x00 0x29000000 0x00 0x200>; 667 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 668 #mbox-cells = <1>; 669 ti,mbox-num-users = <4>; 670 ti,mbox-num-fifos = <16>; 671 }; 672 673 mailbox0_cluster1: mailbox@29010000 { 674 compatible = "ti,am64-mailbox"; 675 reg = <0x00 0x29010000 0x00 0x200>; 676 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 677 #mbox-cells = <1>; 678 ti,mbox-num-users = <4>; 679 ti,mbox-num-fifos = <16>; 680 }; 681 682 mailbox0_cluster2: mailbox@29020000 { 683 compatible = "ti,am64-mailbox"; 684 reg = <0x00 0x29020000 0x00 0x200>; 685 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 686 #mbox-cells = <1>; 687 ti,mbox-num-users = <4>; 688 ti,mbox-num-fifos = <16>; 689 }; 690 691 mailbox0_cluster3: mailbox@29030000 { 692 compatible = "ti,am64-mailbox"; 693 reg = <0x00 0x29030000 0x00 0x200>; 694 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 695 #mbox-cells = <1>; 696 ti,mbox-num-users = <4>; 697 ti,mbox-num-fifos = <16>; 698 }; 699 700 ecap0: pwm@23100000 { 701 compatible = "ti,am3352-ecap"; 702 #pwm-cells = <3>; 703 reg = <0x00 0x23100000 0x00 0x100>; 704 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 705 clocks = <&k3_clks 51 0>; 706 clock-names = "fck"; 707 status = "disabled"; 708 }; 709 710 ecap1: pwm@23110000 { 711 compatible = "ti,am3352-ecap"; 712 #pwm-cells = <3>; 713 reg = <0x00 0x23110000 0x00 0x100>; 714 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 715 clocks = <&k3_clks 52 0>; 716 clock-names = "fck"; 717 status = "disabled"; 718 }; 719 720 ecap2: pwm@23120000 { 721 compatible = "ti,am3352-ecap"; 722 #pwm-cells = <3>; 723 reg = <0x00 0x23120000 0x00 0x100>; 724 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 725 clocks = <&k3_clks 53 0>; 726 clock-names = "fck"; 727 status = "disabled"; 728 }; 729 730 main_mcan0: can@20701000 { 731 compatible = "bosch,m_can"; 732 reg = <0x00 0x20701000 0x00 0x200>, 733 <0x00 0x20708000 0x00 0x8000>; 734 reg-names = "m_can", "message_ram"; 735 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 736 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; 737 clock-names = "hclk", "cclk"; 738 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 740 interrupt-names = "int0", "int1"; 741 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 742 status = "disabled"; 743 }; 744 745 main_mcan1: can@20711000 { 746 compatible = "bosch,m_can"; 747 reg = <0x00 0x20711000 0x00 0x200>, 748 <0x00 0x20718000 0x00 0x8000>; 749 reg-names = "m_can", "message_ram"; 750 power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>; 751 clocks = <&k3_clks 99 6>, <&k3_clks 99 1>; 752 clock-names = "hclk", "cclk"; 753 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; 755 interrupt-names = "int0", "int1"; 756 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 757 status = "disabled"; 758 }; 759 760 main_rti0: watchdog@e000000 { 761 compatible = "ti,j7-rti-wdt"; 762 reg = <0x00 0x0e000000 0x00 0x100>; 763 clocks = <&k3_clks 125 0>; 764 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 765 assigned-clocks = <&k3_clks 125 0>; 766 assigned-clock-parents = <&k3_clks 125 2>; 767 }; 768 769 main_rti1: watchdog@e010000 { 770 compatible = "ti,j7-rti-wdt"; 771 reg = <0x00 0x0e010000 0x00 0x100>; 772 clocks = <&k3_clks 126 0>; 773 power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 774 assigned-clocks = <&k3_clks 126 0>; 775 assigned-clock-parents = <&k3_clks 126 2>; 776 }; 777 778 main_rti2: watchdog@e020000 { 779 compatible = "ti,j7-rti-wdt"; 780 reg = <0x00 0x0e020000 0x00 0x100>; 781 clocks = <&k3_clks 127 0>; 782 power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; 783 assigned-clocks = <&k3_clks 127 0>; 784 assigned-clock-parents = <&k3_clks 127 2>; 785 }; 786 787 main_rti3: watchdog@e030000 { 788 compatible = "ti,j7-rti-wdt"; 789 reg = <0x00 0x0e030000 0x00 0x100>; 790 clocks = <&k3_clks 128 0>; 791 power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; 792 assigned-clocks = <&k3_clks 128 0>; 793 assigned-clock-parents = <&k3_clks 128 2>; 794 }; 795 796 main_rti15: watchdog@e0f0000 { 797 compatible = "ti,j7-rti-wdt"; 798 reg = <0x00 0x0e0f0000 0x00 0x100>; 799 clocks = <&k3_clks 130 0>; 800 power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>; 801 assigned-clocks = <&k3_clks 130 0>; 802 assigned-clock-parents = <&k3_clks 130 2>; 803 }; 804 805 epwm0: pwm@23000000 { 806 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 807 #pwm-cells = <3>; 808 reg = <0x00 0x23000000 0x00 0x100>; 809 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 810 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 811 clock-names = "tbclk", "fck"; 812 status = "disabled"; 813 }; 814 815 epwm1: pwm@23010000 { 816 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 817 #pwm-cells = <3>; 818 reg = <0x00 0x23010000 0x00 0x100>; 819 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 820 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 821 clock-names = "tbclk", "fck"; 822 status = "disabled"; 823 }; 824 825 epwm2: pwm@23020000 { 826 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 827 #pwm-cells = <3>; 828 reg = <0x00 0x23020000 0x00 0x100>; 829 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 830 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 831 clock-names = "tbclk", "fck"; 832 status = "disabled"; 833 }; 834 835 mcasp0: audio-controller@2b00000 { 836 compatible = "ti,am33xx-mcasp-audio"; 837 reg = <0x00 0x02b00000 0x00 0x2000>, 838 <0x00 0x02b08000 0x00 0x400>; 839 reg-names = "mpu", "dat"; 840 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 842 interrupt-names = "tx", "rx"; 843 844 dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; 845 dma-names = "tx", "rx"; 846 847 clocks = <&k3_clks 190 0>; 848 clock-names = "fck"; 849 assigned-clocks = <&k3_clks 190 0>; 850 assigned-clock-parents = <&k3_clks 190 2>; 851 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 852 status = "disabled"; 853 }; 854 855 mcasp1: audio-controller@2b10000 { 856 compatible = "ti,am33xx-mcasp-audio"; 857 reg = <0x00 0x02b10000 0x00 0x2000>, 858 <0x00 0x02b18000 0x00 0x400>; 859 reg-names = "mpu", "dat"; 860 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 862 interrupt-names = "tx", "rx"; 863 864 dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; 865 dma-names = "tx", "rx"; 866 867 clocks = <&k3_clks 191 0>; 868 clock-names = "fck"; 869 assigned-clocks = <&k3_clks 191 0>; 870 assigned-clock-parents = <&k3_clks 191 2>; 871 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 872 status = "disabled"; 873 }; 874 875 mcasp2: audio-controller@2b20000 { 876 compatible = "ti,am33xx-mcasp-audio"; 877 reg = <0x00 0x02b20000 0x00 0x2000>, 878 <0x00 0x02b28000 0x00 0x400>; 879 reg-names = "mpu", "dat"; 880 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 882 interrupt-names = "tx", "rx"; 883 884 dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; 885 dma-names = "tx", "rx"; 886 887 clocks = <&k3_clks 192 0>; 888 clock-names = "fck"; 889 assigned-clocks = <&k3_clks 192 0>; 890 assigned-clock-parents = <&k3_clks 192 2>; 891 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 892 status = "disabled"; 893 }; 894}; 895