1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM625 SoC Family MCU Domain peripherals 4 * 5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu { 9 mcu_pmx0: pinctrl@4084000 { 10 compatible = "pinctrl-single"; 11 reg = <0x00 0x04084000 0x00 0x88>; 12 #pinctrl-cells = <1>; 13 pinctrl-single,register-width = <32>; 14 pinctrl-single,function-mask = <0xffffffff>; 15 status = "disabled"; 16 }; 17 18 mcu_uart0: serial@4a00000 { 19 compatible = "ti,am64-uart", "ti,am654-uart"; 20 reg = <0x00 0x04a00000 0x00 0x100>; 21 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 22 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 23 clocks = <&k3_clks 149 0>; 24 clock-names = "fclk"; 25 status = "disabled"; 26 }; 27 28 mcu_i2c0: i2c@4900000 { 29 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 30 reg = <0x00 0x04900000 0x00 0x100>; 31 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 32 #address-cells = <1>; 33 #size-cells = <0>; 34 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 35 clocks = <&k3_clks 106 2>; 36 clock-names = "fck"; 37 status = "disabled"; 38 }; 39 40 mcu_spi0: spi@4b00000 { 41 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 42 reg = <0x00 0x04b00000 0x00 0x400>; 43 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 44 #address-cells = <1>; 45 #size-cells = <0>; 46 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 47 clocks = <&k3_clks 147 0>; 48 status = "disabled"; 49 }; 50 51 mcu_spi1: spi@4b10000 { 52 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 53 reg = <0x00 0x04b10000 0x00 0x400>; 54 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 55 #address-cells = <1>; 56 #size-cells = <0>; 57 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 58 clocks = <&k3_clks 148 0>; 59 status = "disabled"; 60 }; 61 62 mcu_gpio_intr: interrupt-controller@4210000 { 63 compatible = "ti,sci-intr"; 64 reg = <0x00 0x04210000 0x00 0x200>; 65 ti,intr-trigger-type = <1>; 66 interrupt-controller; 67 interrupt-parent = <&gic500>; 68 #interrupt-cells = <1>; 69 ti,sci = <&dmsc>; 70 ti,sci-dev-id = <5>; 71 ti,interrupt-ranges = <0 104 4>; 72 }; 73 74 mcu_gpio0: gpio@4201000 { 75 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 76 reg = <0x00 0x04201000 0x00 0x100>; 77 gpio-controller; 78 #gpio-cells = <2>; 79 interrupt-parent = <&mcu_gpio_intr>; 80 interrupts = <30>, <31>; 81 interrupt-controller; 82 #interrupt-cells = <2>; 83 ti,ngpio = <24>; 84 ti,davinci-gpio-unbanked = <0>; 85 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; 86 clocks = <&k3_clks 79 0>; 87 clock-names = "gpio"; 88 status = "disabled"; 89 }; 90}; 91