1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM62A SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 oc_sram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x10000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x00 0x70000000 0x10000>; 15 }; 16 17 gic500: interrupt-controller@1800000 { 18 compatible = "arm,gic-v3"; 19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 20 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 21 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 22 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 23 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 24 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 25 #address-cells = <2>; 26 #size-cells = <2>; 27 ranges; 28 #interrupt-cells = <3>; 29 interrupt-controller; 30 /* 31 * vcpumntirq: 32 * virtual CPU interface maintenance interrupt 33 */ 34 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 35 36 gic_its: msi-controller@1820000 { 37 compatible = "arm,gic-v3-its"; 38 reg = <0x00 0x01820000 0x00 0x10000>; 39 socionext,synquacer-pre-its = <0x1000000 0x400000>; 40 msi-controller; 41 #msi-cells = <1>; 42 }; 43 }; 44 45 main_conf: syscon@100000 { 46 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 47 reg = <0x00 0x00100000 0x00 0x20000>; 48 #address-cells = <1>; 49 #size-cells = <1>; 50 ranges = <0x00 0x00 0x00100000 0x20000>; 51 }; 52 53 dmss: bus@48000000 { 54 compatible = "simple-bus"; 55 #address-cells = <2>; 56 #size-cells = <2>; 57 dma-ranges; 58 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>; 59 60 ti,sci-dev-id = <25>; 61 62 secure_proxy_main: mailbox@4d000000 { 63 compatible = "ti,am654-secure-proxy"; 64 reg = <0x00 0x4d000000 0x00 0x80000>, 65 <0x00 0x4a600000 0x00 0x80000>, 66 <0x00 0x4a400000 0x00 0x80000>; 67 reg-names = "target_data", "rt", "scfg"; 68 #mbox-cells = <1>; 69 interrupt-names = "rx_012"; 70 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 71 }; 72 }; 73 74 dmsc: system-controller@44043000 { 75 compatible = "ti,k2g-sci"; 76 reg = <0x00 0x44043000 0x00 0xfe0>; 77 reg-names = "debug_messages"; 78 ti,host-id = <12>; 79 mbox-names = "rx", "tx"; 80 mboxes= <&secure_proxy_main 12>, 81 <&secure_proxy_main 13>; 82 83 k3_pds: power-controller { 84 compatible = "ti,sci-pm-domain"; 85 #power-domain-cells = <2>; 86 }; 87 88 k3_clks: clock-controller { 89 compatible = "ti,k2g-sci-clk"; 90 #clock-cells = <2>; 91 }; 92 93 k3_reset: reset-controller { 94 compatible = "ti,sci-reset"; 95 #reset-cells = <2>; 96 }; 97 }; 98 99 main_pmx0: pinctrl@f4000 { 100 compatible = "pinctrl-single"; 101 reg = <0x00 0xf4000 0x00 0x2ac>; 102 #pinctrl-cells = <1>; 103 pinctrl-single,register-width = <32>; 104 pinctrl-single,function-mask = <0xffffffff>; 105 }; 106 107 main_uart0: serial@2800000 { 108 compatible = "ti,am64-uart", "ti,am654-uart"; 109 reg = <0x00 0x02800000 0x00 0x100>; 110 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 111 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 112 clocks = <&k3_clks 146 0>; 113 clock-names = "fclk"; 114 status = "disabled"; 115 }; 116 117 main_uart1: serial@2810000 { 118 compatible = "ti,am64-uart", "ti,am654-uart"; 119 reg = <0x00 0x02810000 0x00 0x100>; 120 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 121 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 122 clocks = <&k3_clks 152 0>; 123 clock-names = "fclk"; 124 status = "disabled"; 125 }; 126 127 main_uart2: serial@2820000 { 128 compatible = "ti,am64-uart", "ti,am654-uart"; 129 reg = <0x00 0x02820000 0x00 0x100>; 130 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 131 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 132 clocks = <&k3_clks 153 0>; 133 clock-names = "fclk"; 134 status = "disabled"; 135 }; 136 137 main_uart3: serial@2830000 { 138 compatible = "ti,am64-uart", "ti,am654-uart"; 139 reg = <0x00 0x02830000 0x00 0x100>; 140 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 141 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 142 clocks = <&k3_clks 154 0>; 143 clock-names = "fclk"; 144 status = "disabled"; 145 }; 146 147 main_uart4: serial@2840000 { 148 compatible = "ti,am64-uart", "ti,am654-uart"; 149 reg = <0x00 0x02840000 0x00 0x100>; 150 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 151 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 152 clocks = <&k3_clks 155 0>; 153 clock-names = "fclk"; 154 status = "disabled"; 155 }; 156 157 main_uart5: serial@2850000 { 158 compatible = "ti,am64-uart", "ti,am654-uart"; 159 reg = <0x00 0x02850000 0x00 0x100>; 160 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 161 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 162 clocks = <&k3_clks 156 0>; 163 clock-names = "fclk"; 164 status = "disabled"; 165 }; 166 167 main_uart6: serial@2860000 { 168 compatible = "ti,am64-uart", "ti,am654-uart"; 169 reg = <0x00 0x02860000 0x00 0x100>; 170 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 171 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 172 clocks = <&k3_clks 158 0>; 173 clock-names = "fclk"; 174 status = "disabled"; 175 }; 176 177 main_i2c0: i2c@20000000 { 178 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 179 reg = <0x00 0x20000000 0x00 0x100>; 180 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 181 #address-cells = <1>; 182 #size-cells = <0>; 183 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 184 clocks = <&k3_clks 102 2>; 185 clock-names = "fck"; 186 status = "disabled"; 187 }; 188 189 main_i2c1: i2c@20010000 { 190 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 191 reg = <0x00 0x20010000 0x00 0x100>; 192 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 193 #address-cells = <1>; 194 #size-cells = <0>; 195 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 196 clocks = <&k3_clks 103 2>; 197 clock-names = "fck"; 198 status = "disabled"; 199 }; 200 201 main_i2c2: i2c@20020000 { 202 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 203 reg = <0x00 0x20020000 0x00 0x100>; 204 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 208 clocks = <&k3_clks 104 2>; 209 clock-names = "fck"; 210 status = "disabled"; 211 }; 212 213 main_i2c3: i2c@20030000 { 214 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 215 reg = <0x00 0x20030000 0x00 0x100>; 216 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 217 #address-cells = <1>; 218 #size-cells = <0>; 219 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 220 clocks = <&k3_clks 105 2>; 221 clock-names = "fck"; 222 status = "disabled"; 223 }; 224 225 main_gpio_intr: interrupt-controller@a00000 { 226 compatible = "ti,sci-intr"; 227 reg = <0x00 0x00a00000 0x00 0x800>; 228 ti,intr-trigger-type = <1>; 229 interrupt-controller; 230 interrupt-parent = <&gic500>; 231 #interrupt-cells = <1>; 232 ti,sci = <&dmsc>; 233 ti,sci-dev-id = <3>; 234 ti,interrupt-ranges = <0 32 16>; 235 status = "disabled"; 236 }; 237 238 main_gpio0: gpio@600000 { 239 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 240 reg = <0x00 0x00600000 0x0 0x100>; 241 gpio-controller; 242 #gpio-cells = <2>; 243 interrupt-parent = <&main_gpio_intr>; 244 interrupts = <190>, <191>, <192>, 245 <193>, <194>, <195>; 246 interrupt-controller; 247 #interrupt-cells = <2>; 248 ti,ngpio = <87>; 249 ti,davinci-gpio-unbanked = <0>; 250 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 251 clocks = <&k3_clks 77 0>; 252 clock-names = "gpio"; 253 status = "disabled"; 254 }; 255 256 main_gpio1: gpio@601000 { 257 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 258 reg = <0x00 0x00601000 0x0 0x100>; 259 gpio-controller; 260 #gpio-cells = <2>; 261 interrupt-parent = <&main_gpio_intr>; 262 interrupts = <180>, <181>, <182>, 263 <183>, <184>, <185>; 264 interrupt-controller; 265 #interrupt-cells = <2>; 266 ti,ngpio = <88>; 267 ti,davinci-gpio-unbanked = <0>; 268 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 269 clocks = <&k3_clks 78 0>; 270 clock-names = "gpio"; 271 status = "disabled"; 272 }; 273 274 sdhci1: mmc@fa00000 { 275 compatible = "ti,am62-sdhci"; 276 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; 277 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 278 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 279 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; 280 clock-names = "clk_ahb", "clk_xin"; 281 ti,trm-icp = <0x2>; 282 ti,otap-del-sel-legacy = <0x0>; 283 ti,otap-del-sel-sd-hs = <0x0>; 284 ti,otap-del-sel-sdr12 = <0xf>; 285 ti,otap-del-sel-sdr25 = <0xf>; 286 ti,otap-del-sel-sdr50 = <0xc>; 287 ti,otap-del-sel-sdr104 = <0x6>; 288 ti,otap-del-sel-ddr50 = <0x9>; 289 ti,itap-del-sel-legacy = <0x0>; 290 ti,itap-del-sel-sd-hs = <0x0>; 291 ti,itap-del-sel-sdr12 = <0x0>; 292 ti,itap-del-sel-sdr25 = <0x0>; 293 ti,clkbuf-sel = <0x7>; 294 bus-width = <4>; 295 no-1-8-v; 296 status = "disabled"; 297 }; 298}; 299