1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM62A SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 oc_sram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x10000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x00 0x70000000 0x10000>; 15 }; 16 17 gic500: interrupt-controller@1800000 { 18 compatible = "arm,gic-v3"; 19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 20 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 21 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 22 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 23 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 24 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 25 #address-cells = <2>; 26 #size-cells = <2>; 27 ranges; 28 #interrupt-cells = <3>; 29 interrupt-controller; 30 /* 31 * vcpumntirq: 32 * virtual CPU interface maintenance interrupt 33 */ 34 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 35 36 gic_its: msi-controller@1820000 { 37 compatible = "arm,gic-v3-its"; 38 reg = <0x00 0x01820000 0x00 0x10000>; 39 socionext,synquacer-pre-its = <0x1000000 0x400000>; 40 msi-controller; 41 #msi-cells = <1>; 42 }; 43 }; 44 45 main_conf: syscon@100000 { 46 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 47 reg = <0x00 0x00100000 0x00 0x20000>; 48 #address-cells = <1>; 49 #size-cells = <1>; 50 ranges = <0x00 0x00 0x00100000 0x20000>; 51 52 phy_gmii_sel: phy@4044 { 53 compatible = "ti,am654-phy-gmii-sel"; 54 reg = <0x4044 0x8>; 55 #phy-cells = <1>; 56 }; 57 58 epwm_tbclk: clock-controller@4130 { 59 compatible = "ti,am62-epwm-tbclk", "syscon"; 60 reg = <0x4130 0x4>; 61 #clock-cells = <1>; 62 }; 63 }; 64 65 dmss: bus@48000000 { 66 compatible = "simple-bus"; 67 #address-cells = <2>; 68 #size-cells = <2>; 69 dma-ranges; 70 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>; 71 72 ti,sci-dev-id = <25>; 73 74 secure_proxy_main: mailbox@4d000000 { 75 compatible = "ti,am654-secure-proxy"; 76 reg = <0x00 0x4d000000 0x00 0x80000>, 77 <0x00 0x4a600000 0x00 0x80000>, 78 <0x00 0x4a400000 0x00 0x80000>; 79 reg-names = "target_data", "rt", "scfg"; 80 #mbox-cells = <1>; 81 interrupt-names = "rx_012"; 82 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 83 }; 84 85 inta_main_dmss: interrupt-controller@48000000 { 86 compatible = "ti,sci-inta"; 87 reg = <0x00 0x48000000 0x00 0x100000>; 88 #interrupt-cells = <0>; 89 interrupt-controller; 90 interrupt-parent = <&gic500>; 91 msi-controller; 92 ti,sci = <&dmsc>; 93 ti,sci-dev-id = <28>; 94 ti,interrupt-ranges = <6 70 34>; 95 ti,unmapped-event-sources = <&main_bcdma>, <&main_pktdma>; 96 }; 97 98 main_bcdma: dma-controller@485c0100 { 99 compatible = "ti,am64-dmss-bcdma"; 100 reg = <0x00 0x485c0100 0x00 0x100>, 101 <0x00 0x4c000000 0x00 0x20000>, 102 <0x00 0x4a820000 0x00 0x20000>, 103 <0x00 0x4aa40000 0x00 0x20000>, 104 <0x00 0x4bc00000 0x00 0x100000>; 105 reg-names = "gcfg", "bchanrt", "rchanrt", "tchanrt", "ringrt"; 106 msi-parent = <&inta_main_dmss>; 107 #dma-cells = <3>; 108 ti,sci = <&dmsc>; 109 ti,sci-dev-id = <26>; 110 ti,sci-rm-range-bchan = <0x20>; /* BLOCK_COPY_CHAN */ 111 ti,sci-rm-range-rchan = <0x21>; /* SPLIT_TR_RX_CHAN */ 112 ti,sci-rm-range-tchan = <0x22>; /* SPLIT_TR_TX_CHAN */ 113 }; 114 115 main_pktdma: dma-controller@485c0000 { 116 compatible = "ti,am64-dmss-pktdma"; 117 reg = <0x00 0x485c0000 0x00 0x100>, 118 <0x00 0x4a800000 0x00 0x20000>, 119 <0x00 0x4aa00000 0x00 0x40000>, 120 <0x00 0x4b800000 0x00 0x400000>; 121 reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt"; 122 msi-parent = <&inta_main_dmss>; 123 #dma-cells = <2>; 124 ti,sci = <&dmsc>; 125 ti,sci-dev-id = <30>; 126 ti,sci-rm-range-tchan = <0x23>, /* UNMAPPED_TX_CHAN */ 127 <0x24>, /* CPSW_TX_CHAN */ 128 <0x25>, /* SAUL_TX_0_CHAN */ 129 <0x26>; /* SAUL_TX_1_CHAN */ 130 ti,sci-rm-range-tflow = <0x10>, /* RING_UNMAPPED_TX_CHAN */ 131 <0x11>, /* RING_CPSW_TX_CHAN */ 132 <0x12>, /* RING_SAUL_TX_0_CHAN */ 133 <0x13>; /* RING_SAUL_TX_1_CHAN */ 134 ti,sci-rm-range-rchan = <0x29>, /* UNMAPPED_RX_CHAN */ 135 <0x2b>, /* CPSW_RX_CHAN */ 136 <0x2d>, /* SAUL_RX_0_CHAN */ 137 <0x2f>, /* SAUL_RX_1_CHAN */ 138 <0x31>, /* SAUL_RX_2_CHAN */ 139 <0x33>; /* SAUL_RX_3_CHAN */ 140 ti,sci-rm-range-rflow = <0x2a>, /* FLOW_UNMAPPED_RX_CHAN */ 141 <0x2c>, /* FLOW_CPSW_RX_CHAN */ 142 <0x2e>, /* FLOW_SAUL_RX_0/1_CHAN */ 143 <0x32>; /* FLOW_SAUL_RX_2/3_CHAN */ 144 }; 145 }; 146 147 dmsc: system-controller@44043000 { 148 compatible = "ti,k2g-sci"; 149 reg = <0x00 0x44043000 0x00 0xfe0>; 150 reg-names = "debug_messages"; 151 ti,host-id = <12>; 152 mbox-names = "rx", "tx"; 153 mboxes= <&secure_proxy_main 12>, 154 <&secure_proxy_main 13>; 155 156 k3_pds: power-controller { 157 compatible = "ti,sci-pm-domain"; 158 #power-domain-cells = <2>; 159 }; 160 161 k3_clks: clock-controller { 162 compatible = "ti,k2g-sci-clk"; 163 #clock-cells = <2>; 164 }; 165 166 k3_reset: reset-controller { 167 compatible = "ti,sci-reset"; 168 #reset-cells = <2>; 169 }; 170 }; 171 172 main_pmx0: pinctrl@f4000 { 173 compatible = "pinctrl-single"; 174 reg = <0x00 0xf4000 0x00 0x2ac>; 175 #pinctrl-cells = <1>; 176 pinctrl-single,register-width = <32>; 177 pinctrl-single,function-mask = <0xffffffff>; 178 }; 179 180 main_uart0: serial@2800000 { 181 compatible = "ti,am64-uart", "ti,am654-uart"; 182 reg = <0x00 0x02800000 0x00 0x100>; 183 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 184 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 185 clocks = <&k3_clks 146 0>; 186 clock-names = "fclk"; 187 status = "disabled"; 188 }; 189 190 main_uart1: serial@2810000 { 191 compatible = "ti,am64-uart", "ti,am654-uart"; 192 reg = <0x00 0x02810000 0x00 0x100>; 193 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 194 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 195 clocks = <&k3_clks 152 0>; 196 clock-names = "fclk"; 197 status = "disabled"; 198 }; 199 200 main_uart2: serial@2820000 { 201 compatible = "ti,am64-uart", "ti,am654-uart"; 202 reg = <0x00 0x02820000 0x00 0x100>; 203 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 204 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 205 clocks = <&k3_clks 153 0>; 206 clock-names = "fclk"; 207 status = "disabled"; 208 }; 209 210 main_uart3: serial@2830000 { 211 compatible = "ti,am64-uart", "ti,am654-uart"; 212 reg = <0x00 0x02830000 0x00 0x100>; 213 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 214 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 215 clocks = <&k3_clks 154 0>; 216 clock-names = "fclk"; 217 status = "disabled"; 218 }; 219 220 main_uart4: serial@2840000 { 221 compatible = "ti,am64-uart", "ti,am654-uart"; 222 reg = <0x00 0x02840000 0x00 0x100>; 223 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 224 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 225 clocks = <&k3_clks 155 0>; 226 clock-names = "fclk"; 227 status = "disabled"; 228 }; 229 230 main_uart5: serial@2850000 { 231 compatible = "ti,am64-uart", "ti,am654-uart"; 232 reg = <0x00 0x02850000 0x00 0x100>; 233 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 234 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 235 clocks = <&k3_clks 156 0>; 236 clock-names = "fclk"; 237 status = "disabled"; 238 }; 239 240 main_uart6: serial@2860000 { 241 compatible = "ti,am64-uart", "ti,am654-uart"; 242 reg = <0x00 0x02860000 0x00 0x100>; 243 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 244 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 245 clocks = <&k3_clks 158 0>; 246 clock-names = "fclk"; 247 status = "disabled"; 248 }; 249 250 main_i2c0: i2c@20000000 { 251 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 252 reg = <0x00 0x20000000 0x00 0x100>; 253 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 254 #address-cells = <1>; 255 #size-cells = <0>; 256 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 257 clocks = <&k3_clks 102 2>; 258 clock-names = "fck"; 259 status = "disabled"; 260 }; 261 262 main_i2c1: i2c@20010000 { 263 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 264 reg = <0x00 0x20010000 0x00 0x100>; 265 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 269 clocks = <&k3_clks 103 2>; 270 clock-names = "fck"; 271 status = "disabled"; 272 }; 273 274 main_i2c2: i2c@20020000 { 275 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 276 reg = <0x00 0x20020000 0x00 0x100>; 277 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 281 clocks = <&k3_clks 104 2>; 282 clock-names = "fck"; 283 status = "disabled"; 284 }; 285 286 main_i2c3: i2c@20030000 { 287 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 288 reg = <0x00 0x20030000 0x00 0x100>; 289 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 290 #address-cells = <1>; 291 #size-cells = <0>; 292 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 293 clocks = <&k3_clks 105 2>; 294 clock-names = "fck"; 295 status = "disabled"; 296 }; 297 298 main_spi0: spi@20100000 { 299 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 300 reg = <0x00 0x20100000 0x00 0x400>; 301 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 305 clocks = <&k3_clks 141 0>; 306 status = "disabled"; 307 }; 308 309 main_spi1: spi@20110000 { 310 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 311 reg = <0x00 0x20110000 0x00 0x400>; 312 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 316 clocks = <&k3_clks 142 0>; 317 status = "disabled"; 318 }; 319 320 main_spi2: spi@20120000 { 321 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 322 reg = <0x00 0x20120000 0x00 0x400>; 323 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 324 #address-cells = <1>; 325 #size-cells = <0>; 326 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 327 clocks = <&k3_clks 143 0>; 328 status = "disabled"; 329 }; 330 331 main_gpio_intr: interrupt-controller@a00000 { 332 compatible = "ti,sci-intr"; 333 reg = <0x00 0x00a00000 0x00 0x800>; 334 ti,intr-trigger-type = <1>; 335 interrupt-controller; 336 interrupt-parent = <&gic500>; 337 #interrupt-cells = <1>; 338 ti,sci = <&dmsc>; 339 ti,sci-dev-id = <3>; 340 ti,interrupt-ranges = <0 32 16>; 341 status = "disabled"; 342 }; 343 344 main_gpio0: gpio@600000 { 345 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 346 reg = <0x00 0x00600000 0x0 0x100>; 347 gpio-controller; 348 #gpio-cells = <2>; 349 interrupt-parent = <&main_gpio_intr>; 350 interrupts = <190>, <191>, <192>, 351 <193>, <194>, <195>; 352 interrupt-controller; 353 #interrupt-cells = <2>; 354 ti,ngpio = <87>; 355 ti,davinci-gpio-unbanked = <0>; 356 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 357 clocks = <&k3_clks 77 0>; 358 clock-names = "gpio"; 359 status = "disabled"; 360 }; 361 362 main_gpio1: gpio@601000 { 363 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 364 reg = <0x00 0x00601000 0x0 0x100>; 365 gpio-controller; 366 #gpio-cells = <2>; 367 interrupt-parent = <&main_gpio_intr>; 368 interrupts = <180>, <181>, <182>, 369 <183>, <184>, <185>; 370 interrupt-controller; 371 #interrupt-cells = <2>; 372 ti,ngpio = <88>; 373 ti,davinci-gpio-unbanked = <0>; 374 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 375 clocks = <&k3_clks 78 0>; 376 clock-names = "gpio"; 377 status = "disabled"; 378 }; 379 380 sdhci1: mmc@fa00000 { 381 compatible = "ti,am62-sdhci"; 382 reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; 383 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 384 power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; 385 clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; 386 clock-names = "clk_ahb", "clk_xin"; 387 ti,trm-icp = <0x2>; 388 ti,otap-del-sel-legacy = <0x0>; 389 ti,otap-del-sel-sd-hs = <0x0>; 390 ti,otap-del-sel-sdr12 = <0xf>; 391 ti,otap-del-sel-sdr25 = <0xf>; 392 ti,otap-del-sel-sdr50 = <0xc>; 393 ti,otap-del-sel-sdr104 = <0x6>; 394 ti,otap-del-sel-ddr50 = <0x9>; 395 ti,itap-del-sel-legacy = <0x0>; 396 ti,itap-del-sel-sd-hs = <0x0>; 397 ti,itap-del-sel-sdr12 = <0x0>; 398 ti,itap-del-sel-sdr25 = <0x0>; 399 ti,clkbuf-sel = <0x7>; 400 bus-width = <4>; 401 no-1-8-v; 402 status = "disabled"; 403 }; 404 405 usbss0: dwc3-usb@f900000 { 406 compatible = "ti,am62-usb"; 407 reg = <0x00 0x0f900000 0x00 0x800>; 408 clocks = <&k3_clks 161 3>; 409 clock-names = "ref"; 410 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4008>; 411 #address-cells = <2>; 412 #size-cells = <2>; 413 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>; 414 ranges; 415 status = "disabled"; 416 417 usb0: usb@31000000 { 418 compatible = "snps,dwc3"; 419 reg =<0x00 0x31000000 0x00 0x50000>; 420 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 421 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 422 interrupt-names = "host", "peripheral"; 423 maximum-speed = "high-speed"; 424 dr_mode = "otg"; 425 }; 426 }; 427 428 usbss1: dwc3-usb@f910000 { 429 compatible = "ti,am62-usb"; 430 reg = <0x00 0x0f910000 0x00 0x800>; 431 clocks = <&k3_clks 162 3>; 432 clock-names = "ref"; 433 ti,syscon-phy-pll-refclk = <&wkup_conf 0x4018>; 434 #address-cells = <2>; 435 #size-cells = <2>; 436 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>; 437 ranges; 438 status = "disabled"; 439 440 usb1: usb@31100000 { 441 compatible = "snps,dwc3"; 442 reg =<0x00 0x31100000 0x00 0x50000>; 443 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */ 444 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */ 445 interrupt-names = "host", "peripheral"; 446 maximum-speed = "high-speed"; 447 dr_mode = "otg"; 448 }; 449 }; 450 451 fss: bus@fc00000 { 452 compatible = "simple-bus"; 453 reg = <0x00 0x0fc00000 0x00 0x70000>; 454 #address-cells = <2>; 455 #size-cells = <2>; 456 ranges; 457 status = "disabled"; 458 459 ospi0: spi@fc40000 { 460 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 461 reg = <0x00 0x0fc40000 0x00 0x100>, 462 <0x05 0x00000000 0x01 0x00000000>; 463 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 464 cdns,fifo-depth = <256>; 465 cdns,fifo-width = <4>; 466 cdns,trigger-address = <0x0>; 467 clocks = <&k3_clks 75 7>; 468 assigned-clocks = <&k3_clks 75 7>; 469 assigned-clock-parents = <&k3_clks 75 8>; 470 assigned-clock-rates = <166666666>; 471 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 472 #address-cells = <1>; 473 #size-cells = <0>; 474 }; 475 }; 476 477 cpsw3g: ethernet@8000000 { 478 compatible = "ti,am642-cpsw-nuss"; 479 #address-cells = <2>; 480 #size-cells = <2>; 481 reg = <0x0 0x8000000 0x0 0x200000>; 482 reg-names = "cpsw_nuss"; 483 ranges = <0x0 0x0 0x0 0x8000000 0x0 0x200000>; 484 clocks = <&k3_clks 13 0>; 485 assigned-clocks = <&k3_clks 13 3>; 486 assigned-clock-parents = <&k3_clks 13 11>; 487 clock-names = "fck"; 488 power-domains = <&k3_pds 13 TI_SCI_PD_EXCLUSIVE>; 489 status = "disabled"; 490 491 dmas = <&main_pktdma 0xc600 15>, 492 <&main_pktdma 0xc601 15>, 493 <&main_pktdma 0xc602 15>, 494 <&main_pktdma 0xc603 15>, 495 <&main_pktdma 0xc604 15>, 496 <&main_pktdma 0xc605 15>, 497 <&main_pktdma 0xc606 15>, 498 <&main_pktdma 0xc607 15>, 499 <&main_pktdma 0x4600 15>; 500 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", 501 "tx7", "rx"; 502 503 ethernet-ports { 504 #address-cells = <1>; 505 #size-cells = <0>; 506 507 cpsw_port1: port@1 { 508 reg = <1>; 509 ti,mac-only; 510 label = "port1"; 511 phys = <&phy_gmii_sel 1>; 512 mac-address = [00 00 00 00 00 00]; 513 ti,syscon-efuse = <&wkup_conf 0x200>; 514 }; 515 516 cpsw_port2: port@2 { 517 reg = <2>; 518 ti,mac-only; 519 label = "port2"; 520 phys = <&phy_gmii_sel 2>; 521 mac-address = [00 00 00 00 00 00]; 522 }; 523 }; 524 525 cpsw3g_mdio: mdio@f00 { 526 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 527 reg = <0x0 0xf00 0x0 0x100>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 clocks = <&k3_clks 13 0>; 531 clock-names = "fck"; 532 bus_freq = <1000000>; 533 }; 534 535 cpts@3d000 { 536 compatible = "ti,j721e-cpts"; 537 reg = <0x0 0x3d000 0x0 0x400>; 538 clocks = <&k3_clks 13 3>; 539 clock-names = "cpts"; 540 interrupts-extended = <&gic500 GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 541 interrupt-names = "cpts"; 542 ti,cpts-ext-ts-inputs = <4>; 543 ti,cpts-periodic-outputs = <2>; 544 }; 545 }; 546 547 hwspinlock: spinlock@2a000000 { 548 compatible = "ti,am64-hwspinlock"; 549 reg = <0x00 0x2a000000 0x00 0x1000>; 550 #hwlock-cells = <1>; 551 }; 552 553 mailbox0_cluster0: mailbox@29000000 { 554 compatible = "ti,am64-mailbox"; 555 reg = <0x00 0x29000000 0x00 0x200>; 556 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 557 #mbox-cells = <1>; 558 ti,mbox-num-users = <4>; 559 ti,mbox-num-fifos = <16>; 560 }; 561 562 mailbox0_cluster1: mailbox@29010000 { 563 compatible = "ti,am64-mailbox"; 564 reg = <0x00 0x29010000 0x00 0x200>; 565 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 566 #mbox-cells = <1>; 567 ti,mbox-num-users = <4>; 568 ti,mbox-num-fifos = <16>; 569 }; 570 571 mailbox0_cluster2: mailbox@29020000 { 572 compatible = "ti,am64-mailbox"; 573 reg = <0x00 0x29020000 0x00 0x200>; 574 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 575 #mbox-cells = <1>; 576 ti,mbox-num-users = <4>; 577 ti,mbox-num-fifos = <16>; 578 }; 579 580 mailbox0_cluster3: mailbox@29030000 { 581 compatible = "ti,am64-mailbox"; 582 reg = <0x00 0x29030000 0x00 0x200>; 583 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 584 #mbox-cells = <1>; 585 ti,mbox-num-users = <4>; 586 ti,mbox-num-fifos = <16>; 587 }; 588 589 main_mcan0: can@20701000 { 590 compatible = "bosch,m_can"; 591 reg = <0x00 0x20701000 0x00 0x200>, 592 <0x00 0x20708000 0x00 0x8000>; 593 reg-names = "m_can", "message_ram"; 594 power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>; 595 clocks = <&k3_clks 98 6>, <&k3_clks 98 1>; 596 clock-names = "hclk", "cclk"; 597 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 599 interrupt-names = "int0", "int1"; 600 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 601 status = "disabled"; 602 }; 603 604 epwm0: pwm@23000000 { 605 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 606 #pwm-cells = <3>; 607 reg = <0x00 0x23000000 0x00 0x100>; 608 power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; 609 clocks = <&epwm_tbclk 0>, <&k3_clks 86 0>; 610 clock-names = "tbclk", "fck"; 611 status = "disabled"; 612 }; 613 614 epwm1: pwm@23010000 { 615 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 616 #pwm-cells = <3>; 617 reg = <0x00 0x23010000 0x00 0x100>; 618 power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; 619 clocks = <&epwm_tbclk 1>, <&k3_clks 87 0>; 620 clock-names = "tbclk", "fck"; 621 status = "disabled"; 622 }; 623 624 epwm2: pwm@23020000 { 625 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 626 #pwm-cells = <3>; 627 reg = <0x00 0x23020000 0x00 0x100>; 628 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 629 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 630 clock-names = "tbclk", "fck"; 631 status = "disabled"; 632 }; 633 634 ecap0: pwm@23100000 { 635 compatible = "ti,am3352-ecap"; 636 #pwm-cells = <3>; 637 reg = <0x00 0x23100000 0x00 0x100>; 638 power-domains = <&k3_pds 51 TI_SCI_PD_EXCLUSIVE>; 639 clocks = <&k3_clks 51 0>; 640 clock-names = "fck"; 641 status = "disabled"; 642 }; 643 644 ecap1: pwm@23110000 { 645 compatible = "ti,am3352-ecap"; 646 #pwm-cells = <3>; 647 reg = <0x00 0x23110000 0x00 0x100>; 648 power-domains = <&k3_pds 52 TI_SCI_PD_EXCLUSIVE>; 649 clocks = <&k3_clks 52 0>; 650 clock-names = "fck"; 651 status = "disabled"; 652 }; 653 654 ecap2: pwm@23120000 { 655 compatible = "ti,am3352-ecap"; 656 #pwm-cells = <3>; 657 reg = <0x00 0x23120000 0x00 0x100>; 658 power-domains = <&k3_pds 53 TI_SCI_PD_EXCLUSIVE>; 659 clocks = <&k3_clks 53 0>; 660 clock-names = "fck"; 661 status = "disabled"; 662 }; 663}; 664