1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * AM625 SK: https://www.ti.com/lit/zip/sprr448 4 * 5 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8/dts-v1/; 9 10#include "k3-am62x-sk-common.dtsi" 11 12/ { 13 compatible = "ti,am625-sk", "ti,am625"; 14 model = "Texas Instruments AM625 SK"; 15 16 opp-table { 17 /* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */ 18 opp-1400000000 { 19 opp-hz = /bits/ 64 <1400000000>; 20 opp-supported-hw = <0x01 0x0004>; 21 clock-latency-ns = <6000000>; 22 }; 23 }; 24 25 memory@80000000 { 26 device_type = "memory"; 27 /* 2G RAM */ 28 reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 29 30 }; 31 32 vmain_pd: regulator-0 { 33 /* TPS65988 PD CONTROLLER OUTPUT */ 34 bootph-all; 35 compatible = "regulator-fixed"; 36 regulator-name = "vmain_pd"; 37 regulator-min-microvolt = <5000000>; 38 regulator-max-microvolt = <5000000>; 39 regulator-always-on; 40 regulator-boot-on; 41 }; 42 43 vcc_5v0: regulator-1 { 44 /* Output of LM34936 */ 45 bootph-all; 46 compatible = "regulator-fixed"; 47 regulator-name = "vcc_5v0"; 48 regulator-min-microvolt = <5000000>; 49 regulator-max-microvolt = <5000000>; 50 vin-supply = <&vmain_pd>; 51 regulator-always-on; 52 regulator-boot-on; 53 }; 54 55 vcc_3v3_sys: regulator-2 { 56 /* output of LM61460-Q1 */ 57 bootph-all; 58 compatible = "regulator-fixed"; 59 regulator-name = "vcc_3v3_sys"; 60 regulator-min-microvolt = <3300000>; 61 regulator-max-microvolt = <3300000>; 62 vin-supply = <&vmain_pd>; 63 regulator-always-on; 64 regulator-boot-on; 65 }; 66 67 vdd_mmc1: regulator-3 { 68 /* TPS22918DBVR */ 69 bootph-all; 70 compatible = "regulator-fixed"; 71 regulator-name = "vdd_mmc1"; 72 regulator-min-microvolt = <3300000>; 73 regulator-max-microvolt = <3300000>; 74 regulator-boot-on; 75 enable-active-high; 76 vin-supply = <&vcc_3v3_sys>; 77 gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; 78 }; 79 80 vdd_sd_dv: regulator-4 { 81 /* Output of TLV71033 */ 82 bootph-all; 83 compatible = "regulator-gpio"; 84 regulator-name = "tlv71033"; 85 pinctrl-names = "default"; 86 pinctrl-0 = <&vdd_sd_dv_pins_default>; 87 regulator-min-microvolt = <1800000>; 88 regulator-max-microvolt = <3300000>; 89 regulator-boot-on; 90 vin-supply = <&vcc_5v0>; 91 gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; 92 states = <1800000 0x0>, 93 <3300000 0x1>; 94 }; 95 96 vcc_1v8: regulator-5 { 97 /* output of TPS6282518DMQ */ 98 compatible = "regulator-fixed"; 99 regulator-name = "vcc_1v8"; 100 regulator-min-microvolt = <1800000>; 101 regulator-max-microvolt = <1800000>; 102 vin-supply = <&vcc_3v3_sys>; 103 regulator-always-on; 104 regulator-boot-on; 105 }; 106}; 107 108&main_pmx0 { 109 main_mmc0_pins_default: main-mmc0-default-pins { 110 bootph-all; 111 pinctrl-single,pins = < 112 AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ 113 AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ 114 AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ 115 AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ 116 AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ 117 AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ 118 AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ 119 AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ 120 AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ 121 AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ 122 >; 123 }; 124 125 main_rgmii2_pins_default: main-rgmii2-default-pins { 126 bootph-all; 127 pinctrl-single,pins = < 128 AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ 129 AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ 130 AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ 131 AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ 132 AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ 133 AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ 134 AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ 135 AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ 136 AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ 137 AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ 138 AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ 139 AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ 140 >; 141 }; 142 143 ospi0_pins_default: ospi0-default-pins { 144 bootph-all; 145 pinctrl-single,pins = < 146 AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ 147 AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ 148 AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ 149 AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ 150 AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ 151 AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ 152 AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ 153 AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ 154 AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ 155 AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ 156 AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ 157 >; 158 }; 159 160 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 161 bootph-all; 162 pinctrl-single,pins = < 163 AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ 164 >; 165 }; 166 167 main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-default-pins { 168 bootph-all; 169 pinctrl-single,pins = < 170 AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ 171 >; 172 }; 173}; 174 175&main_gpio0 { 176 bootph-all; 177}; 178 179&main_gpio1 { 180 bootph-all; 181}; 182 183&main_i2c1 { 184 bootph-all; 185 exp1: gpio@22 { 186 bootph-all; 187 compatible = "ti,tca6424"; 188 reg = <0x22>; 189 gpio-controller; 190 #gpio-cells = <2>; 191 gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", 192 "PRU_DETECT", "MMC1_SD_EN", 193 "VPP_LDO_EN", "EXP_PS_3V3_En", 194 "EXP_PS_5V0_En", "EXP_HAT_DETECT", 195 "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", 196 "UART1_FET_BUF_EN", "WL_LT_EN", 197 "GPIO_HDMI_RSTn", "CSI_GPIO1", 198 "CSI_GPIO2", "PRU_3V3_EN", 199 "HDMI_INTn", "PD_I2C_IRQ", 200 "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", 201 "MCASP1_FET_SEL", "UART1_FET_SEL", 202 "TSINT#", "IO_EXP_TEST_LED"; 203 204 interrupt-parent = <&main_gpio1>; 205 interrupts = <23 IRQ_TYPE_EDGE_FALLING>; 206 interrupt-controller; 207 #interrupt-cells = <2>; 208 209 pinctrl-names = "default"; 210 pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; 211 }; 212}; 213 214&sdhci0 { 215 bootph-all; 216 non-removable; 217 pinctrl-names = "default"; 218 pinctrl-0 = <&main_mmc0_pins_default>; 219 status = "okay"; 220}; 221 222&sdhci1 { 223 vmmc-supply = <&vdd_mmc1>; 224 vqmmc-supply = <&vdd_sd_dv>; 225}; 226 227&cpsw3g { 228 pinctrl-names = "default"; 229 pinctrl-0 = <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; 230}; 231 232&cpsw_port2 { 233 phy-mode = "rgmii-rxid"; 234 phy-handle = <&cpsw3g_phy1>; 235}; 236 237&cpsw3g_mdio { 238 cpsw3g_phy1: ethernet-phy@1 { 239 reg = <1>; 240 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 241 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 242 ti,min-output-impedance; 243 }; 244}; 245 246&fss { 247 bootph-all; 248}; 249 250&ospi0 { 251 bootph-all; 252 status = "okay"; 253 pinctrl-names = "default"; 254 pinctrl-0 = <&ospi0_pins_default>; 255 256 flash@0 { 257 bootph-all; 258 compatible = "jedec,spi-nor"; 259 reg = <0x0>; 260 spi-tx-bus-width = <8>; 261 spi-rx-bus-width = <8>; 262 spi-max-frequency = <25000000>; 263 cdns,tshsl-ns = <60>; 264 cdns,tsd2d-ns = <60>; 265 cdns,tchsh-ns = <60>; 266 cdns,tslch-ns = <60>; 267 cdns,read-delay = <4>; 268 269 partitions { 270 bootph-all; 271 compatible = "fixed-partitions"; 272 #address-cells = <1>; 273 #size-cells = <1>; 274 275 partition@0 { 276 label = "ospi.tiboot3"; 277 reg = <0x0 0x80000>; 278 }; 279 280 partition@80000 { 281 label = "ospi.tispl"; 282 reg = <0x80000 0x200000>; 283 }; 284 285 partition@280000 { 286 label = "ospi.u-boot"; 287 reg = <0x280000 0x400000>; 288 }; 289 290 partition@680000 { 291 label = "ospi.env"; 292 reg = <0x680000 0x40000>; 293 }; 294 295 partition@6c0000 { 296 label = "ospi.env.backup"; 297 reg = <0x6c0000 0x40000>; 298 }; 299 300 partition@800000 { 301 label = "ospi.rootfs"; 302 reg = <0x800000 0x37c0000>; 303 }; 304 305 partition@3fc0000 { 306 bootph-pre-ram; 307 label = "ospi.phypattern"; 308 reg = <0x3fc0000 0x40000>; 309 }; 310 }; 311 }; 312}; 313 314&tlv320aic3106 { 315 DVDD-supply = <&vcc_1v8>; 316}; 317