1// SPDX-License-Identifier: GPL-2.0 2/* 3 * AM625 SK: https://www.ti.com/lit/zip/sprr448 4 * 5 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8/dts-v1/; 9 10#include <dt-bindings/leds/common.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/net/ti-dp83867.h> 13#include "k3-am625.dtsi" 14 15/ { 16 compatible = "ti,am625-sk", "ti,am625"; 17 model = "Texas Instruments AM625 SK"; 18 19 aliases { 20 serial2 = &main_uart0; 21 mmc0 = &sdhci0; 22 mmc1 = &sdhci1; 23 mmc2 = &sdhci2; 24 spi0 = &ospi0; 25 ethernet0 = &cpsw_port1; 26 ethernet1 = &cpsw_port2; 27 }; 28 29 chosen { 30 stdout-path = "serial2:115200n8"; 31 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; 32 }; 33 34 memory@80000000 { 35 device_type = "memory"; 36 /* 2G RAM */ 37 reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 38 39 }; 40 41 reserved-memory { 42 #address-cells = <2>; 43 #size-cells = <2>; 44 ranges; 45 46 ramoops@9ca00000 { 47 compatible = "ramoops"; 48 reg = <0x00 0x9ca00000 0x00 0x00100000>; 49 record-size = <0x8000>; 50 console-size = <0x8000>; 51 ftrace-size = <0x00>; 52 pmsg-size = <0x8000>; 53 }; 54 55 secure_tfa_ddr: tfa@9e780000 { 56 reg = <0x00 0x9e780000 0x00 0x80000>; 57 alignment = <0x1000>; 58 no-map; 59 }; 60 61 secure_ddr: optee@9e800000 { 62 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 63 alignment = <0x1000>; 64 no-map; 65 }; 66 67 wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { 68 compatible = "shared-dma-pool"; 69 reg = <0x00 0x9db00000 0x00 0xc00000>; 70 no-map; 71 }; 72 }; 73 74 vmain_pd: regulator-0 { 75 /* TPS65988 PD CONTROLLER OUTPUT */ 76 compatible = "regulator-fixed"; 77 regulator-name = "vmain_pd"; 78 regulator-min-microvolt = <5000000>; 79 regulator-max-microvolt = <5000000>; 80 regulator-always-on; 81 regulator-boot-on; 82 }; 83 84 vcc_5v0: regulator-1 { 85 /* Output of LM34936 */ 86 compatible = "regulator-fixed"; 87 regulator-name = "vcc_5v0"; 88 regulator-min-microvolt = <5000000>; 89 regulator-max-microvolt = <5000000>; 90 vin-supply = <&vmain_pd>; 91 regulator-always-on; 92 regulator-boot-on; 93 }; 94 95 vcc_3v3_sys: regulator-2 { 96 /* output of LM61460-Q1 */ 97 compatible = "regulator-fixed"; 98 regulator-name = "vcc_3v3_sys"; 99 regulator-min-microvolt = <3300000>; 100 regulator-max-microvolt = <3300000>; 101 vin-supply = <&vmain_pd>; 102 regulator-always-on; 103 regulator-boot-on; 104 }; 105 106 vdd_mmc1: regulator-3 { 107 /* TPS22918DBVR */ 108 compatible = "regulator-fixed"; 109 regulator-name = "vdd_mmc1"; 110 regulator-min-microvolt = <3300000>; 111 regulator-max-microvolt = <3300000>; 112 regulator-boot-on; 113 enable-active-high; 114 vin-supply = <&vcc_3v3_sys>; 115 gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; 116 }; 117 118 vdd_sd_dv: regulator-4 { 119 /* Output of TLV71033 */ 120 compatible = "regulator-gpio"; 121 regulator-name = "tlv71033"; 122 pinctrl-names = "default"; 123 pinctrl-0 = <&vdd_sd_dv_pins_default>; 124 regulator-min-microvolt = <1800000>; 125 regulator-max-microvolt = <3300000>; 126 regulator-boot-on; 127 vin-supply = <&vcc_5v0>; 128 gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; 129 states = <1800000 0x0>, 130 <3300000 0x1>; 131 }; 132 133 leds { 134 compatible = "gpio-leds"; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&usr_led_pins_default>; 137 138 led-0 { 139 label = "am62-sk:green:heartbeat"; 140 gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; 141 linux,default-trigger = "heartbeat"; 142 function = LED_FUNCTION_HEARTBEAT; 143 default-state = "off"; 144 }; 145 }; 146}; 147 148&main_pmx0 { 149 main_uart0_pins_default: main-uart0-pins-default { 150 pinctrl-single,pins = < 151 AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ 152 AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ 153 >; 154 }; 155 156 main_i2c0_pins_default: main-i2c0-pins-default { 157 pinctrl-single,pins = < 158 AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ 159 AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ 160 >; 161 }; 162 163 main_i2c1_pins_default: main-i2c1-pins-default { 164 pinctrl-single,pins = < 165 AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ 166 AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ 167 >; 168 }; 169 170 main_i2c2_pins_default: main-i2c2-pins-default { 171 pinctrl-single,pins = < 172 AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ 173 AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ 174 >; 175 }; 176 177 main_mmc0_pins_default: main-mmc0-pins-default { 178 pinctrl-single,pins = < 179 AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ 180 AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ 181 AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ 182 AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ 183 AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ 184 AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ 185 AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ 186 AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ 187 AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ 188 AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ 189 >; 190 }; 191 192 main_mmc1_pins_default: main-mmc1-pins-default { 193 pinctrl-single,pins = < 194 AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ 195 AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ 196 AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ 197 AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ 198 AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ 199 AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ 200 AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */ 201 >; 202 }; 203 204 usr_led_pins_default: usr-led-pins-default { 205 pinctrl-single,pins = < 206 AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ 207 >; 208 }; 209 210 main_mdio1_pins_default: main-mdio1-pins-default { 211 pinctrl-single,pins = < 212 AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ 213 AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ 214 >; 215 }; 216 217 main_rgmii1_pins_default: main-rgmii1-pins-default { 218 pinctrl-single,pins = < 219 AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ 220 AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ 221 AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ 222 AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ 223 AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ 224 AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ 225 AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ 226 AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ 227 AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ 228 AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ 229 AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ 230 AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ 231 >; 232 }; 233 234 main_rgmii2_pins_default: main-rgmii2-pins-default { 235 pinctrl-single,pins = < 236 AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ 237 AM62X_IOPAD(0x188, PIN_INPUT, 0) /* (AB20) RGMII2_RD1 */ 238 AM62X_IOPAD(0x18c, PIN_INPUT, 0) /* (AC21) RGMII2_RD2 */ 239 AM62X_IOPAD(0x190, PIN_INPUT, 0) /* (AE22) RGMII2_RD3 */ 240 AM62X_IOPAD(0x180, PIN_INPUT, 0) /* (AD23) RGMII2_RXC */ 241 AM62X_IOPAD(0x17c, PIN_INPUT, 0) /* (AD22) RGMII2_RX_CTL */ 242 AM62X_IOPAD(0x16c, PIN_OUTPUT, 0) /* (Y18) RGMII2_TD0 */ 243 AM62X_IOPAD(0x170, PIN_OUTPUT, 0) /* (AA18) RGMII2_TD1 */ 244 AM62X_IOPAD(0x174, PIN_OUTPUT, 0) /* (AD21) RGMII2_TD2 */ 245 AM62X_IOPAD(0x178, PIN_OUTPUT, 0) /* (AC20) RGMII2_TD3 */ 246 AM62X_IOPAD(0x168, PIN_OUTPUT, 0) /* (AE21) RGMII2_TXC */ 247 AM62X_IOPAD(0x164, PIN_OUTPUT, 0) /* (AA19) RGMII2_TX_CTL */ 248 >; 249 }; 250 251 ospi0_pins_default: ospi0-pins-default { 252 pinctrl-single,pins = < 253 AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ 254 AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ 255 AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ 256 AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ 257 AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ 258 AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ 259 AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ 260 AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ 261 AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ 262 AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ 263 AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ 264 >; 265 }; 266 267 vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { 268 pinctrl-single,pins = < 269 AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (P25) GPMC0_CLK.GPIO0_31 */ 270 >; 271 }; 272 273 main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default { 274 pinctrl-single,pins = < 275 AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ 276 >; 277 }; 278}; 279 280&wkup_uart0 { 281 /* WKUP UART0 is used by DM firmware */ 282 status = "reserved"; 283}; 284 285&mcu_uart0 { 286 status = "disabled"; 287}; 288 289&main_uart0 { 290 pinctrl-names = "default"; 291 pinctrl-0 = <&main_uart0_pins_default>; 292}; 293 294&main_uart1 { 295 /* Main UART1 is used by TIFS firmware */ 296 status = "reserved"; 297}; 298 299&main_uart2 { 300 status = "disabled"; 301}; 302 303&main_uart3 { 304 status = "disabled"; 305}; 306 307&main_uart4 { 308 status = "disabled"; 309}; 310 311&main_uart5 { 312 status = "disabled"; 313}; 314 315&main_uart6 { 316 status = "disabled"; 317}; 318 319&mcu_i2c0 { 320 status = "disabled"; 321}; 322 323&wkup_i2c0 { 324 status = "disabled"; 325}; 326 327&main_i2c0 { 328 pinctrl-names = "default"; 329 pinctrl-0 = <&main_i2c0_pins_default>; 330 clock-frequency = <400000>; 331}; 332 333&main_i2c1 { 334 pinctrl-names = "default"; 335 pinctrl-0 = <&main_i2c1_pins_default>; 336 clock-frequency = <400000>; 337 338 exp1: gpio@22 { 339 compatible = "ti,tca6424"; 340 reg = <0x22>; 341 gpio-controller; 342 #gpio-cells = <2>; 343 gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", 344 "PRU_DETECT", "MMC1_SD_EN", 345 "VPP_LDO_EN", "EXP_PS_3V3_En", 346 "EXP_PS_5V0_En", "EXP_HAT_DETECT", 347 "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", 348 "UART1_FET_BUF_EN", "WL_LT_EN", 349 "GPIO_HDMI_RSTn", "CSI_GPIO1", 350 "CSI_GPIO2", "PRU_3V3_EN", 351 "HDMI_INTn", "TEST_GPIO2", 352 "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", 353 "MCASP1_FET_SEL", "UART1_FET_SEL", 354 "TSINT#", "IO_EXP_TEST_LED"; 355 356 interrupt-parent = <&main_gpio1>; 357 interrupts = <23 IRQ_TYPE_EDGE_FALLING>; 358 interrupt-controller; 359 #interrupt-cells = <2>; 360 361 pinctrl-names = "default"; 362 pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; 363 }; 364}; 365 366&main_i2c2 { 367 status = "disabled"; 368}; 369 370&main_i2c3 { 371 status = "disabled"; 372}; 373 374&sdhci0 { 375 pinctrl-names = "default"; 376 pinctrl-0 = <&main_mmc0_pins_default>; 377 ti,driver-strength-ohm = <50>; 378 disable-wp; 379}; 380 381&sdhci1 { 382 /* SD/MMC */ 383 vmmc-supply = <&vdd_mmc1>; 384 vqmmc-supply = <&vdd_sd_dv>; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&main_mmc1_pins_default>; 387 ti,driver-strength-ohm = <50>; 388 disable-wp; 389}; 390 391&cpsw3g { 392 pinctrl-names = "default"; 393 pinctrl-0 = <&main_mdio1_pins_default 394 &main_rgmii1_pins_default 395 &main_rgmii2_pins_default>; 396}; 397 398&cpsw_port1 { 399 phy-mode = "rgmii-rxid"; 400 phy-handle = <&cpsw3g_phy0>; 401}; 402 403&cpsw_port2 { 404 phy-mode = "rgmii-rxid"; 405 phy-handle = <&cpsw3g_phy1>; 406}; 407 408&cpsw3g_mdio { 409 cpsw3g_phy0: ethernet-phy@0 { 410 reg = <0>; 411 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 412 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 413 ti,min-output-impedance; 414 }; 415 416 cpsw3g_phy1: ethernet-phy@1 { 417 reg = <1>; 418 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 419 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 420 ti,min-output-impedance; 421 }; 422}; 423 424&mailbox0_cluster0 { 425 mbox_m4_0: mbox-m4-0 { 426 ti,mbox-rx = <0 0 0>; 427 ti,mbox-tx = <1 0 0>; 428 }; 429}; 430 431&ospi0 { 432 pinctrl-names = "default"; 433 pinctrl-0 = <&ospi0_pins_default>; 434 435 flash@0{ 436 compatible = "jedec,spi-nor"; 437 reg = <0x0>; 438 spi-tx-bus-width = <8>; 439 spi-rx-bus-width = <8>; 440 spi-max-frequency = <25000000>; 441 cdns,tshsl-ns = <60>; 442 cdns,tsd2d-ns = <60>; 443 cdns,tchsh-ns = <60>; 444 cdns,tslch-ns = <60>; 445 cdns,read-delay = <4>; 446 447 partitions { 448 compatible = "fixed-partitions"; 449 #address-cells = <1>; 450 #size-cells = <1>; 451 452 partition@0 { 453 label = "ospi.tiboot3"; 454 reg = <0x0 0x80000>; 455 }; 456 457 partition@80000 { 458 label = "ospi.tispl"; 459 reg = <0x80000 0x200000>; 460 }; 461 462 partition@280000 { 463 label = "ospi.u-boot"; 464 reg = <0x280000 0x400000>; 465 }; 466 467 partition@680000 { 468 label = "ospi.env"; 469 reg = <0x680000 0x40000>; 470 }; 471 472 partition@6c0000 { 473 label = "ospi.env.backup"; 474 reg = <0x6c0000 0x40000>; 475 }; 476 477 partition@800000 { 478 label = "ospi.rootfs"; 479 reg = <0x800000 0x37c0000>; 480 }; 481 482 partition@3fc0000 { 483 label = "ospi.phypattern"; 484 reg = <0x3fc0000 0x40000>; 485 }; 486 }; 487 }; 488}; 489 490&ecap0 { 491 status = "disabled"; 492}; 493 494&ecap1 { 495 status = "disabled"; 496}; 497 498&ecap2 { 499 status = "disabled"; 500}; 501 502&main_mcan0 { 503 status = "disabled"; 504}; 505