1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM625 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 gic500: interrupt-controller@1800000 { 10 compatible = "arm,gic-v3"; 11 #address-cells = <2>; 12 #size-cells = <2>; 13 ranges; 14 #interrupt-cells = <3>; 15 interrupt-controller; 16 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 17 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 18 <0x00 0x01880000 0x00 0xc0000>, /* GICR */ 19 <0x01 0x00000000 0x00 0x2000>, /* GICC */ 20 <0x01 0x00010000 0x00 0x1000>, /* GICH */ 21 <0x01 0x00020000 0x00 0x2000>; /* GICV */ 22 /* 23 * vcpumntirq: 24 * virtual CPU interface maintenance interrupt 25 */ 26 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 27 28 gic_its: msi-controller@1820000 { 29 compatible = "arm,gic-v3-its"; 30 reg = <0x00 0x01820000 0x00 0x10000>; 31 socionext,synquacer-pre-its = <0x1000000 0x400000>; 32 msi-controller; 33 #msi-cells = <1>; 34 }; 35 }; 36 37 main_conf: syscon@100000 { 38 compatible = "syscon", "simple-mfd"; 39 reg = <0x00 0x00100000 0x00 0x20000>; 40 #address-cells = <1>; 41 #size-cells = <1>; 42 ranges = <0x0 0x00 0x00100000 0x20000>; 43 }; 44 45 dmss: bus@48000000 { 46 compatible = "simple-mfd"; 47 #address-cells = <2>; 48 #size-cells = <2>; 49 dma-ranges; 50 ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>; 51 52 ti,sci-dev-id = <25>; 53 54 secure_proxy_main: mailbox@4d000000 { 55 compatible = "ti,am654-secure-proxy"; 56 #mbox-cells = <1>; 57 reg-names = "target_data", "rt", "scfg"; 58 reg = <0x00 0x4d000000 0x00 0x80000>, 59 <0x00 0x4a600000 0x00 0x80000>, 60 <0x00 0x4a400000 0x00 0x80000>; 61 interrupt-names = "rx_012"; 62 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 63 }; 64 }; 65 66 dmsc: system-controller@44043000 { 67 compatible = "ti,k2g-sci"; 68 ti,host-id = <12>; 69 mbox-names = "rx", "tx"; 70 mboxes= <&secure_proxy_main 12>, 71 <&secure_proxy_main 13>; 72 reg-names = "debug_messages"; 73 reg = <0x00 0x44043000 0x00 0xfe0>; 74 75 k3_pds: power-controller { 76 compatible = "ti,sci-pm-domain"; 77 #power-domain-cells = <2>; 78 }; 79 80 k3_clks: clock-controller { 81 compatible = "ti,k2g-sci-clk"; 82 #clock-cells = <2>; 83 }; 84 85 k3_reset: reset-controller { 86 compatible = "ti,sci-reset"; 87 #reset-cells = <2>; 88 }; 89 }; 90 91 main_pmx0: pinctrl@f4000 { 92 compatible = "pinctrl-single"; 93 reg = <0x00 0xf4000 0x00 0x2ac>; 94 #pinctrl-cells = <1>; 95 pinctrl-single,register-width = <32>; 96 pinctrl-single,function-mask = <0xffffffff>; 97 }; 98 99 main_uart0: serial@2800000 { 100 compatible = "ti,am64-uart", "ti,am654-uart"; 101 reg = <0x00 0x02800000 0x00 0x100>; 102 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 103 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 104 clocks = <&k3_clks 146 0>; 105 clock-names = "fclk"; 106 }; 107 108 main_uart1: serial@2810000 { 109 compatible = "ti,am64-uart", "ti,am654-uart"; 110 reg = <0x00 0x02810000 0x00 0x100>; 111 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 112 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 113 clocks = <&k3_clks 152 0>; 114 clock-names = "fclk"; 115 }; 116 117 main_uart2: serial@2820000 { 118 compatible = "ti,am64-uart", "ti,am654-uart"; 119 reg = <0x00 0x02820000 0x00 0x100>; 120 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 121 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 122 clocks = <&k3_clks 153 0>; 123 clock-names = "fclk"; 124 }; 125 126 main_uart3: serial@2830000 { 127 compatible = "ti,am64-uart", "ti,am654-uart"; 128 reg = <0x00 0x02830000 0x00 0x100>; 129 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 130 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 131 clocks = <&k3_clks 154 0>; 132 clock-names = "fclk"; 133 }; 134 135 main_uart4: serial@2840000 { 136 compatible = "ti,am64-uart", "ti,am654-uart"; 137 reg = <0x00 0x02840000 0x00 0x100>; 138 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 139 power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; 140 clocks = <&k3_clks 155 0>; 141 clock-names = "fclk"; 142 }; 143 144 main_uart5: serial@2850000 { 145 compatible = "ti,am64-uart", "ti,am654-uart"; 146 reg = <0x00 0x02850000 0x00 0x100>; 147 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 148 power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; 149 clocks = <&k3_clks 156 0>; 150 clock-names = "fclk"; 151 }; 152 153 main_uart6: serial@2860000 { 154 compatible = "ti,am64-uart", "ti,am654-uart"; 155 reg = <0x00 0x02860000 0x00 0x100>; 156 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 157 power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; 158 clocks = <&k3_clks 158 0>; 159 clock-names = "fclk"; 160 }; 161 162 main_i2c0: i2c@20000000 { 163 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 164 reg = <0x00 0x20000000 0x00 0x100>; 165 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 166 #address-cells = <1>; 167 #size-cells = <0>; 168 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 169 clocks = <&k3_clks 102 2>; 170 clock-names = "fck"; 171 }; 172 173 main_i2c1: i2c@20010000 { 174 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 175 reg = <0x00 0x20010000 0x00 0x100>; 176 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 177 #address-cells = <1>; 178 #size-cells = <0>; 179 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 180 clocks = <&k3_clks 103 2>; 181 clock-names = "fck"; 182 }; 183 184 main_i2c2: i2c@20020000 { 185 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 186 reg = <0x00 0x20020000 0x00 0x100>; 187 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 188 #address-cells = <1>; 189 #size-cells = <0>; 190 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 191 clocks = <&k3_clks 104 2>; 192 clock-names = "fck"; 193 }; 194 195 main_i2c3: i2c@20030000 { 196 compatible = "ti,am64-i2c", "ti,omap4-i2c"; 197 reg = <0x00 0x20030000 0x00 0x100>; 198 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 199 #address-cells = <1>; 200 #size-cells = <0>; 201 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 202 clocks = <&k3_clks 105 2>; 203 clock-names = "fck"; 204 }; 205 206 main_gpio_intr: interrupt-controller@a00000 { 207 compatible = "ti,sci-intr"; 208 reg = <0x00 0x00a00000 0x00 0x800>; 209 ti,intr-trigger-type = <1>; 210 interrupt-controller; 211 interrupt-parent = <&gic500>; 212 #interrupt-cells = <1>; 213 ti,sci = <&dmsc>; 214 ti,sci-dev-id = <3>; 215 ti,interrupt-ranges = <0 32 16>; 216 }; 217 218 main_gpio0: gpio@600000 { 219 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 220 reg = <0x0 0x00600000 0x0 0x100>; 221 gpio-controller; 222 #gpio-cells = <2>; 223 interrupt-parent = <&main_gpio_intr>; 224 interrupts = <190>, <191>, <192>, 225 <193>, <194>, <195>; 226 interrupt-controller; 227 #interrupt-cells = <2>; 228 ti,ngpio = <87>; 229 ti,davinci-gpio-unbanked = <0>; 230 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 231 clocks = <&k3_clks 77 0>; 232 clock-names = "gpio"; 233 }; 234 235 main_gpio1: gpio@601000 { 236 compatible = "ti,am64-gpio", "ti,keystone-gpio"; 237 reg = <0x0 0x00601000 0x0 0x100>; 238 gpio-controller; 239 #gpio-cells = <2>; 240 interrupt-parent = <&main_gpio_intr>; 241 interrupts = <180>, <181>, <182>, 242 <183>, <184>, <185>; 243 interrupt-controller; 244 #interrupt-cells = <2>; 245 ti,ngpio = <88>; 246 ti,davinci-gpio-unbanked = <0>; 247 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 248 clocks = <&k3_clks 78 0>; 249 clock-names = "gpio"; 250 }; 251 252 hwspinlock: spinlock@2a000000 { 253 compatible = "ti,am64-hwspinlock"; 254 reg = <0x00 0x2a000000 0x00 0x1000>; 255 #hwlock-cells = <1>; 256 }; 257 258 mailbox0_cluster0: mailbox@29000000 { 259 compatible = "ti,am64-mailbox"; 260 reg = <0x00 0x29000000 0x00 0x200>; 261 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 263 #mbox-cells = <1>; 264 ti,mbox-num-users = <4>; 265 ti,mbox-num-fifos = <16>; 266 }; 267}; 268