1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Tesla Full Self-Driving SoC device tree source 4 * 5 * Copyright (c) 2017-2022 Samsung Electronics Co., Ltd. 6 * https://www.samsung.com 7 * Copyright (c) 2017-2022 Tesla, Inc. 8 * https://www.tesla.com 9 */ 10 11#include <dt-bindings/clock/fsd-clk.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14/ { 15 compatible = "tesla,fsd"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 i2c0 = &hsi2c_0; 22 i2c1 = &hsi2c_1; 23 i2c2 = &hsi2c_2; 24 i2c3 = &hsi2c_3; 25 i2c4 = &hsi2c_4; 26 i2c5 = &hsi2c_5; 27 i2c6 = &hsi2c_6; 28 i2c7 = &hsi2c_7; 29 pinctrl0 = &pinctrl_fsys0; 30 pinctrl1 = &pinctrl_peric; 31 pinctrl2 = &pinctrl_pmu; 32 spi0 = &spi_0; 33 spi1 = &spi_1; 34 spi2 = &spi_2; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 cpu-map { 42 cluster0 { 43 core0 { 44 cpu = <&cpucl0_0>; 45 }; 46 core1 { 47 cpu = <&cpucl0_1>; 48 }; 49 core2 { 50 cpu = <&cpucl0_2>; 51 }; 52 core3 { 53 cpu = <&cpucl0_3>; 54 }; 55 }; 56 57 cluster1 { 58 core0 { 59 cpu = <&cpucl1_0>; 60 }; 61 core1 { 62 cpu = <&cpucl1_1>; 63 }; 64 core2 { 65 cpu = <&cpucl1_2>; 66 }; 67 core3 { 68 cpu = <&cpucl1_3>; 69 }; 70 }; 71 72 cluster2 { 73 core0 { 74 cpu = <&cpucl2_0>; 75 }; 76 core1 { 77 cpu = <&cpucl2_1>; 78 }; 79 core2 { 80 cpu = <&cpucl2_2>; 81 }; 82 core3 { 83 cpu = <&cpucl2_3>; 84 }; 85 }; 86 }; 87 88 /* Cluster 0 */ 89 cpucl0_0: cpu@0 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a72"; 92 reg = <0x0 0x000>; 93 enable-method = "psci"; 94 clock-frequency = <2400000000>; 95 cpu-idle-states = <&CPU_SLEEP>; 96 i-cache-size = <0xc000>; 97 i-cache-line-size = <64>; 98 i-cache-sets = <256>; 99 d-cache-size = <0x8000>; 100 d-cache-line-size = <64>; 101 d-cache-sets = <256>; 102 next-level-cache = <&cpucl_l2>; 103 }; 104 105 cpucl0_1: cpu@1 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a72"; 108 reg = <0x0 0x001>; 109 enable-method = "psci"; 110 clock-frequency = <2400000000>; 111 cpu-idle-states = <&CPU_SLEEP>; 112 i-cache-size = <0xc000>; 113 i-cache-line-size = <64>; 114 i-cache-sets = <256>; 115 d-cache-size = <0x8000>; 116 d-cache-line-size = <64>; 117 d-cache-sets = <256>; 118 next-level-cache = <&cpucl_l2>; 119 }; 120 121 cpucl0_2: cpu@2 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a72"; 124 reg = <0x0 0x002>; 125 enable-method = "psci"; 126 clock-frequency = <2400000000>; 127 cpu-idle-states = <&CPU_SLEEP>; 128 i-cache-size = <0xc000>; 129 i-cache-line-size = <64>; 130 i-cache-sets = <256>; 131 d-cache-size = <0x8000>; 132 d-cache-line-size = <64>; 133 d-cache-sets = <256>; 134 next-level-cache = <&cpucl_l2>; 135 }; 136 137 cpucl0_3: cpu@3 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a72"; 140 reg = <0x0 0x003>; 141 enable-method = "psci"; 142 cpu-idle-states = <&CPU_SLEEP>; 143 i-cache-size = <0xc000>; 144 i-cache-line-size = <64>; 145 i-cache-sets = <256>; 146 d-cache-size = <0x8000>; 147 d-cache-line-size = <64>; 148 d-cache-sets = <256>; 149 next-level-cache = <&cpucl_l2>; 150 }; 151 152 /* Cluster 1 */ 153 cpucl1_0: cpu@100 { 154 device_type = "cpu"; 155 compatible = "arm,cortex-a72"; 156 reg = <0x0 0x100>; 157 enable-method = "psci"; 158 clock-frequency = <2400000000>; 159 cpu-idle-states = <&CPU_SLEEP>; 160 i-cache-size = <0xc000>; 161 i-cache-line-size = <64>; 162 i-cache-sets = <256>; 163 d-cache-size = <0x8000>; 164 d-cache-line-size = <64>; 165 d-cache-sets = <256>; 166 next-level-cache = <&cpucl_l2>; 167 }; 168 169 cpucl1_1: cpu@101 { 170 device_type = "cpu"; 171 compatible = "arm,cortex-a72"; 172 reg = <0x0 0x101>; 173 enable-method = "psci"; 174 clock-frequency = <2400000000>; 175 cpu-idle-states = <&CPU_SLEEP>; 176 i-cache-size = <0xc000>; 177 i-cache-line-size = <64>; 178 i-cache-sets = <256>; 179 d-cache-size = <0x8000>; 180 d-cache-line-size = <64>; 181 d-cache-sets = <256>; 182 next-level-cache = <&cpucl_l2>; 183 }; 184 185 cpucl1_2: cpu@102 { 186 device_type = "cpu"; 187 compatible = "arm,cortex-a72"; 188 reg = <0x0 0x102>; 189 enable-method = "psci"; 190 clock-frequency = <2400000000>; 191 cpu-idle-states = <&CPU_SLEEP>; 192 i-cache-size = <0xc000>; 193 i-cache-line-size = <64>; 194 i-cache-sets = <256>; 195 d-cache-size = <0x8000>; 196 d-cache-line-size = <64>; 197 d-cache-sets = <256>; 198 next-level-cache = <&cpucl_l2>; 199 }; 200 201 cpucl1_3: cpu@103 { 202 device_type = "cpu"; 203 compatible = "arm,cortex-a72"; 204 reg = <0x0 0x103>; 205 enable-method = "psci"; 206 clock-frequency = <2400000000>; 207 cpu-idle-states = <&CPU_SLEEP>; 208 i-cache-size = <0xc000>; 209 i-cache-line-size = <64>; 210 i-cache-sets = <256>; 211 d-cache-size = <0x8000>; 212 d-cache-line-size = <64>; 213 d-cache-sets = <256>; 214 next-level-cache = <&cpucl_l2>; 215 }; 216 217 /* Cluster 2 */ 218 cpucl2_0: cpu@200 { 219 device_type = "cpu"; 220 compatible = "arm,cortex-a72"; 221 reg = <0x0 0x200>; 222 enable-method = "psci"; 223 clock-frequency = <2400000000>; 224 cpu-idle-states = <&CPU_SLEEP>; 225 i-cache-size = <0xc000>; 226 i-cache-line-size = <64>; 227 i-cache-sets = <256>; 228 d-cache-size = <0x8000>; 229 d-cache-line-size = <64>; 230 d-cache-sets = <256>; 231 next-level-cache = <&cpucl_l2>; 232 }; 233 234 cpucl2_1: cpu@201 { 235 device_type = "cpu"; 236 compatible = "arm,cortex-a72"; 237 reg = <0x0 0x201>; 238 enable-method = "psci"; 239 clock-frequency = <2400000000>; 240 cpu-idle-states = <&CPU_SLEEP>; 241 i-cache-size = <0xc000>; 242 i-cache-line-size = <64>; 243 i-cache-sets = <256>; 244 d-cache-size = <0x8000>; 245 d-cache-line-size = <64>; 246 d-cache-sets = <256>; 247 next-level-cache = <&cpucl_l2>; 248 }; 249 250 cpucl2_2: cpu@202 { 251 device_type = "cpu"; 252 compatible = "arm,cortex-a72"; 253 reg = <0x0 0x202>; 254 enable-method = "psci"; 255 clock-frequency = <2400000000>; 256 cpu-idle-states = <&CPU_SLEEP>; 257 i-cache-size = <0xc000>; 258 i-cache-line-size = <64>; 259 i-cache-sets = <256>; 260 d-cache-size = <0x8000>; 261 d-cache-line-size = <64>; 262 d-cache-sets = <256>; 263 next-level-cache = <&cpucl_l2>; 264 }; 265 266 cpucl2_3: cpu@203 { 267 device_type = "cpu"; 268 compatible = "arm,cortex-a72"; 269 reg = <0x0 0x203>; 270 enable-method = "psci"; 271 clock-frequency = <2400000000>; 272 cpu-idle-states = <&CPU_SLEEP>; 273 i-cache-size = <0xc000>; 274 i-cache-line-size = <64>; 275 i-cache-sets = <256>; 276 d-cache-size = <0x8000>; 277 d-cache-line-size = <64>; 278 d-cache-sets = <256>; 279 next-level-cache = <&cpucl_l2>; 280 }; 281 282 cpucl_l2: l2-cache0 { 283 compatible = "cache"; 284 cache-size = <0x400000>; 285 cache-line-size = <64>; 286 cache-sets = <4096>; 287 }; 288 289 idle-states { 290 entry-method = "psci"; 291 292 CPU_SLEEP: cpu-sleep { 293 idle-state-name = "c2"; 294 compatible = "arm,idle-state"; 295 local-timer-stop; 296 arm,psci-suspend-param = <0x0010000>; 297 entry-latency-us = <30>; 298 exit-latency-us = <75>; 299 min-residency-us = <300>; 300 }; 301 }; 302 }; 303 304 arm-pmu { 305 compatible = "arm,armv8-pmuv3"; 306 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>; 318 interrupt-affinity = <&cpucl0_0>, <&cpucl0_1>, <&cpucl0_2>, 319 <&cpucl0_3>, <&cpucl1_0>, <&cpucl1_1>, 320 <&cpucl1_2>, <&cpucl1_3>, <&cpucl2_0>, 321 <&cpucl2_1>, <&cpucl2_2>, <&cpucl2_3>; 322 }; 323 324 psci { 325 compatible = "arm,psci-1.0"; 326 method = "smc"; 327 }; 328 329 timer { 330 compatible = "arm,armv8-timer"; 331 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 332 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 333 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 334 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 335 }; 336 337 fin_pll: clock { 338 compatible = "fixed-clock"; 339 clock-output-names = "fin_pll"; 340 #clock-cells = <0>; 341 }; 342 343 soc: soc@0 { 344 compatible = "simple-bus"; 345 #address-cells = <2>; 346 #size-cells = <2>; 347 ranges = <0x0 0x0 0x0 0x0 0x0 0x18000000>; 348 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; 349 350 gic: interrupt-controller@10400000 { 351 compatible = "arm,gic-v3"; 352 #interrupt-cells = <3>; 353 interrupt-controller; 354 reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */ 355 <0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */ 356 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 357 }; 358 359 smmu_imem: iommu@10200000 { 360 compatible = "arm,mmu-500"; 361 reg = <0x0 0x10200000 0x0 0x10000>; 362 #iommu-cells = <2>; 363 #global-interrupts = <7>; 364 interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */ 365 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */ 366 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */ 367 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */ 368 /* Performance counter interrupts */ 369 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_0 */ 370 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_1 */ 371 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, /* for IMEM_0 */ 372 /* Per context non-secure context interrupts, 0-3 interrupts */ 373 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */ 374 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */ 375 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */ 376 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_3 */ 377 }; 378 379 smmu_isp: iommu@12100000 { 380 compatible = "arm,mmu-500"; 381 reg = <0x0 0x12100000 0x0 0x10000>; 382 #iommu-cells = <2>; 383 #global-interrupts = <11>; 384 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */ 385 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */ 386 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */ 387 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */ 388 /* Performance counter interrupts */ 389 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_CSI */ 390 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_0 */ 391 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_1 */ 392 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_0 */ 393 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_1 */ 394 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_0 */ 395 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_1 */ 396 /* Per context non-secure context interrupts, 0-7 interrupts */ 397 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */ 398 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */ 399 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */ 400 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_3 */ 401 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_4 */ 402 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_5 */ 403 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_6 */ 404 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_7 */ 405 }; 406 407 smmu_peric: iommu@14900000 { 408 compatible = "arm,mmu-500"; 409 reg = <0x0 0x14900000 0x0 0x10000>; 410 #iommu-cells = <2>; 411 #global-interrupts = <5>; 412 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */ 413 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */ 414 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */ 415 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */ 416 /* Performance counter interrupts */ 417 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, /* for PERIC */ 418 /* Per context non-secure context interrupts, 0-1 interrupts */ 419 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */ 420 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */ 421 }; 422 423 smmu_fsys0: iommu@15450000 { 424 compatible = "arm,mmu-500"; 425 reg = <0x0 0x15450000 0x0 0x10000>; 426 #iommu-cells = <2>; 427 #global-interrupts = <5>; 428 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */ 429 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */ 430 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */ 431 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */ 432 /* Performance counter interrupts */ 433 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS0 */ 434 /* Per context non-secure context interrupts, 0-1 interrupts */ 435 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */ 436 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */ 437 }; 438 439 clock_imem: clock-controller@10010000 { 440 compatible = "tesla,fsd-clock-imem"; 441 reg = <0x0 0x10010000 0x0 0x3000>; 442 #clock-cells = <1>; 443 clocks = <&fin_pll>, 444 <&clock_cmu DOUT_CMU_IMEM_TCUCLK>, 445 <&clock_cmu DOUT_CMU_IMEM_ACLK>, 446 <&clock_cmu DOUT_CMU_IMEM_DMACLK>; 447 clock-names = "fin_pll", 448 "dout_cmu_imem_tcuclk", 449 "dout_cmu_imem_aclk", 450 "dout_cmu_imem_dmaclk"; 451 }; 452 453 clock_cmu: clock-controller@11c10000 { 454 compatible = "tesla,fsd-clock-cmu"; 455 reg = <0x0 0x11c10000 0x0 0x3000>; 456 #clock-cells = <1>; 457 clocks = <&fin_pll>; 458 clock-names = "fin_pll"; 459 }; 460 461 clock_csi: clock-controller@12610000 { 462 compatible = "tesla,fsd-clock-cam_csi"; 463 reg = <0x0 0x12610000 0x0 0x3000>; 464 #clock-cells = <1>; 465 clocks = <&fin_pll>; 466 clock-names = "fin_pll"; 467 }; 468 469 clock_mfc: clock-controller@12810000 { 470 compatible = "tesla,fsd-clock-mfc"; 471 reg = <0x0 0x12810000 0x0 0x3000>; 472 #clock-cells = <1>; 473 clocks = <&fin_pll>; 474 clock-names = "fin_pll"; 475 }; 476 477 clock_peric: clock-controller@14010000 { 478 compatible = "tesla,fsd-clock-peric"; 479 reg = <0x0 0x14010000 0x0 0x3000>; 480 #clock-cells = <1>; 481 clocks = <&fin_pll>, 482 <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV4>, 483 <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV36>, 484 <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK>, 485 <&clock_cmu DOUT_CMU_PERIC_SHARED0DIV20>, 486 <&clock_cmu DOUT_CMU_PERIC_SHARED1DIV4_DMACLK>; 487 clock-names = "fin_pll", 488 "dout_cmu_pll_shared0_div4", 489 "dout_cmu_peric_shared1div36", 490 "dout_cmu_peric_shared0div3_tbuclk", 491 "dout_cmu_peric_shared0div20", 492 "dout_cmu_peric_shared1div4_dmaclk"; 493 }; 494 495 clock_fsys0: clock-controller@15010000 { 496 compatible = "tesla,fsd-clock-fsys0"; 497 reg = <0x0 0x15010000 0x0 0x3000>; 498 #clock-cells = <1>; 499 clocks = <&fin_pll>, 500 <&clock_cmu DOUT_CMU_PLL_SHARED0_DIV6>, 501 <&clock_cmu DOUT_CMU_FSYS0_SHARED1DIV4>, 502 <&clock_cmu DOUT_CMU_FSYS0_SHARED0DIV4>; 503 clock-names = "fin_pll", 504 "dout_cmu_pll_shared0_div6", 505 "dout_cmu_fsys0_shared1div4", 506 "dout_cmu_fsys0_shared0div4"; 507 }; 508 509 clock_fsys1: clock-controller@16810000 { 510 compatible = "tesla,fsd-clock-fsys1"; 511 reg = <0x0 0x16810000 0x0 0x3000>; 512 #clock-cells = <1>; 513 clocks = <&fin_pll>, 514 <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>, 515 <&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>; 516 clock-names = "fin_pll", 517 "dout_cmu_fsys1_shared0div8", 518 "dout_cmu_fsys1_shared0div4"; 519 }; 520 521 mdma0: dma-controller@10100000 { 522 compatible = "arm,pl330", "arm,primecell"; 523 reg = <0x0 0x10100000 0x0 0x1000>; 524 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>; 525 #dma-cells = <1>; 526 clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>; 527 clock-names = "apb_pclk"; 528 iommus = <&smmu_imem 0x800 0x0>; 529 }; 530 531 mdma1: dma-controller@10110000 { 532 compatible = "arm,pl330", "arm,primecell"; 533 reg = <0x0 0x10110000 0x0 0x1000>; 534 interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 535 #dma-cells = <1>; 536 clocks = <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK>; 537 clock-names = "apb_pclk"; 538 iommus = <&smmu_imem 0x801 0x0>; 539 }; 540 541 pdma0: dma-controller@14280000 { 542 compatible = "arm,pl330", "arm,primecell"; 543 reg = <0x0 0x14280000 0x0 0x1000>; 544 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 545 #dma-cells = <1>; 546 clocks = <&clock_peric PERIC_DMA0_IPCLKPORT_ACLK>; 547 clock-names = "apb_pclk"; 548 iommus = <&smmu_peric 0x2 0x0>; 549 }; 550 551 pdma1: dma-controller@14290000 { 552 compatible = "arm,pl330", "arm,primecell"; 553 reg = <0x0 0x14290000 0x0 0x1000>; 554 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 555 #dma-cells = <1>; 556 clocks = <&clock_peric PERIC_DMA1_IPCLKPORT_ACLK>; 557 clock-names = "apb_pclk"; 558 iommus = <&smmu_peric 0x1 0x0>; 559 }; 560 561 serial_0: serial@14180000 { 562 compatible = "samsung,exynos4210-uart"; 563 reg = <0x0 0x14180000 0x0 0x100>; 564 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 565 dmas = <&pdma1 1>, <&pdma1 0>; 566 dma-names = "rx", "tx"; 567 clocks = <&clock_peric PERIC_PCLK_UART0>, 568 <&clock_peric PERIC_SCLK_UART0>; 569 clock-names = "uart", "clk_uart_baud0"; 570 status = "disabled"; 571 }; 572 573 serial_1: serial@14190000 { 574 compatible = "samsung,exynos4210-uart"; 575 reg = <0x0 0x14190000 0x0 0x100>; 576 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 577 dmas = <&pdma1 3>, <&pdma1 2>; 578 dma-names = "rx", "tx"; 579 clocks = <&clock_peric PERIC_PCLK_UART1>, 580 <&clock_peric PERIC_SCLK_UART1>; 581 clock-names = "uart", "clk_uart_baud0"; 582 status = "disabled"; 583 }; 584 585 pmu_system_controller: system-controller@11400000 { 586 compatible = "samsung,exynos7-pmu", "syscon"; 587 reg = <0x0 0x11400000 0x0 0x5000>; 588 }; 589 590 watchdog_0: watchdog@100a0000 { 591 compatible = "samsung,exynos7-wdt"; 592 reg = <0x0 0x100a0000 0x0 0x100>; 593 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 594 samsung,syscon-phandle = <&pmu_system_controller>; 595 clocks = <&fin_pll>; 596 clock-names = "watchdog"; 597 }; 598 599 watchdog_1: watchdog@100b0000 { 600 compatible = "samsung,exynos7-wdt"; 601 reg = <0x0 0x100b0000 0x0 0x100>; 602 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 603 samsung,syscon-phandle = <&pmu_system_controller>; 604 clocks = <&fin_pll>; 605 clock-names = "watchdog"; 606 }; 607 608 watchdog_2: watchdog@100c0000 { 609 compatible = "samsung,exynos7-wdt"; 610 reg = <0x0 0x100c0000 0x0 0x100>; 611 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 612 samsung,syscon-phandle = <&pmu_system_controller>; 613 clocks = <&fin_pll>; 614 clock-names = "watchdog"; 615 }; 616 617 pwm_0: pwm@14100000 { 618 compatible = "samsung,exynos4210-pwm"; 619 reg = <0x0 0x14100000 0x0 0x100>; 620 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 621 #pwm-cells = <3>; 622 clocks = <&clock_peric PERIC_PWM0_IPCLKPORT_I_PCLK_S0>; 623 clock-names = "timers"; 624 status = "disabled"; 625 }; 626 627 pwm_1: pwm@14110000 { 628 compatible = "samsung,exynos4210-pwm"; 629 reg = <0x0 0x14110000 0x0 0x100>; 630 samsung,pwm-outputs = <0>, <1>, <2>, <3>; 631 #pwm-cells = <3>; 632 clocks = <&clock_peric PERIC_PWM1_IPCLKPORT_I_PCLK_S0>; 633 clock-names = "timers"; 634 status = "disabled"; 635 }; 636 637 hsi2c_0: i2c@14200000 { 638 compatible = "samsung,exynos7-hsi2c"; 639 reg = <0x0 0x14200000 0x0 0x1000>; 640 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 641 #address-cells = <1>; 642 #size-cells = <0>; 643 pinctrl-names = "default"; 644 pinctrl-0 = <&hs_i2c0_bus>; 645 clocks = <&clock_peric PERIC_PCLK_HSI2C0>; 646 clock-names = "hsi2c"; 647 status = "disabled"; 648 }; 649 650 hsi2c_1: i2c@14210000 { 651 compatible = "samsung,exynos7-hsi2c"; 652 reg = <0x0 0x14210000 0x0 0x1000>; 653 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 654 #address-cells = <1>; 655 #size-cells = <0>; 656 pinctrl-names = "default"; 657 pinctrl-0 = <&hs_i2c1_bus>; 658 clocks = <&clock_peric PERIC_PCLK_HSI2C1>; 659 clock-names = "hsi2c"; 660 status = "disabled"; 661 }; 662 663 hsi2c_2: i2c@14220000 { 664 compatible = "samsung,exynos7-hsi2c"; 665 reg = <0x0 0x14220000 0x0 0x1000>; 666 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 667 #address-cells = <1>; 668 #size-cells = <0>; 669 pinctrl-names = "default"; 670 pinctrl-0 = <&hs_i2c2_bus>; 671 clocks = <&clock_peric PERIC_PCLK_HSI2C2>; 672 clock-names = "hsi2c"; 673 status = "disabled"; 674 }; 675 676 hsi2c_3: i2c@14230000 { 677 compatible = "samsung,exynos7-hsi2c"; 678 reg = <0x0 0x14230000 0x0 0x1000>; 679 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 680 #address-cells = <1>; 681 #size-cells = <0>; 682 pinctrl-names = "default"; 683 pinctrl-0 = <&hs_i2c3_bus>; 684 clocks = <&clock_peric PERIC_PCLK_HSI2C3>; 685 clock-names = "hsi2c"; 686 status = "disabled"; 687 }; 688 689 hsi2c_4: i2c@14240000 { 690 compatible = "samsung,exynos7-hsi2c"; 691 reg = <0x0 0x14240000 0x0 0x1000>; 692 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 693 #address-cells = <1>; 694 #size-cells = <0>; 695 pinctrl-names = "default"; 696 pinctrl-0 = <&hs_i2c4_bus>; 697 clocks = <&clock_peric PERIC_PCLK_HSI2C4>; 698 clock-names = "hsi2c"; 699 status = "disabled"; 700 }; 701 702 hsi2c_5: i2c@14250000 { 703 compatible = "samsung,exynos7-hsi2c"; 704 reg = <0x0 0x14250000 0x0 0x1000>; 705 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 706 #address-cells = <1>; 707 #size-cells = <0>; 708 pinctrl-names = "default"; 709 pinctrl-0 = <&hs_i2c5_bus>; 710 clocks = <&clock_peric PERIC_PCLK_HSI2C5>; 711 clock-names = "hsi2c"; 712 status = "disabled"; 713 }; 714 715 hsi2c_6: i2c@14260000 { 716 compatible = "samsung,exynos7-hsi2c"; 717 reg = <0x0 0x14260000 0x0 0x1000>; 718 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 719 #address-cells = <1>; 720 #size-cells = <0>; 721 pinctrl-names = "default"; 722 pinctrl-0 = <&hs_i2c6_bus>; 723 clocks = <&clock_peric PERIC_PCLK_HSI2C6>; 724 clock-names = "hsi2c"; 725 status = "disabled"; 726 }; 727 728 hsi2c_7: i2c@14270000 { 729 compatible = "samsung,exynos7-hsi2c"; 730 reg = <0x0 0x14270000 0x0 0x1000>; 731 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 732 #address-cells = <1>; 733 #size-cells = <0>; 734 pinctrl-names = "default"; 735 pinctrl-0 = <&hs_i2c7_bus>; 736 clocks = <&clock_peric PERIC_PCLK_HSI2C7>; 737 clock-names = "hsi2c"; 738 status = "disabled"; 739 }; 740 741 pinctrl_pmu: pinctrl@114f0000 { 742 compatible = "tesla,fsd-pinctrl"; 743 reg = <0x0 0x114f0000 0x0 0x1000>; 744 }; 745 746 pinctrl_peric: pinctrl@141f0000 { 747 compatible = "tesla,fsd-pinctrl"; 748 reg = <0x0 0x141f0000 0x0 0x1000>; 749 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 750 }; 751 752 pinctrl_fsys0: pinctrl@15020000 { 753 compatible = "tesla,fsd-pinctrl"; 754 reg = <0x0 0x15020000 0x0 0x1000>; 755 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 756 }; 757 758 spi_0: spi@14140000 { 759 compatible = "tesla,fsd-spi"; 760 reg = <0x0 0x14140000 0x0 0x100>; 761 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 762 dmas = <&pdma1 4>, <&pdma1 5>; 763 dma-names = "tx", "rx"; 764 #address-cells = <1>; 765 #size-cells = <0>; 766 clocks = <&clock_peric PERIC_PCLK_SPI0>, 767 <&clock_peric PERIC_SCLK_SPI0>; 768 clock-names = "spi", "spi_busclk0"; 769 samsung,spi-src-clk = <0>; 770 pinctrl-names = "default"; 771 pinctrl-0 = <&spi0_bus>; 772 num-cs = <1>; 773 status = "disabled"; 774 }; 775 776 spi_1: spi@14150000 { 777 compatible = "tesla,fsd-spi"; 778 reg = <0x0 0x14150000 0x0 0x100>; 779 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 780 dmas = <&pdma1 6>, <&pdma1 7>; 781 dma-names = "tx", "rx"; 782 #address-cells = <1>; 783 #size-cells = <0>; 784 clocks = <&clock_peric PERIC_PCLK_SPI1>, 785 <&clock_peric PERIC_SCLK_SPI1>; 786 clock-names = "spi", "spi_busclk0"; 787 samsung,spi-src-clk = <0>; 788 pinctrl-names = "default"; 789 pinctrl-0 = <&spi1_bus>; 790 num-cs = <1>; 791 status = "disabled"; 792 }; 793 794 spi_2: spi@14160000 { 795 compatible = "tesla,fsd-spi"; 796 reg = <0x0 0x14160000 0x0 0x100>; 797 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 798 dmas = <&pdma1 8>, <&pdma1 9>; 799 dma-names = "tx", "rx"; 800 #address-cells = <1>; 801 #size-cells = <0>; 802 clocks = <&clock_peric PERIC_PCLK_SPI2>, 803 <&clock_peric PERIC_SCLK_SPI2>; 804 clock-names = "spi", "spi_busclk0"; 805 samsung,spi-src-clk = <0>; 806 pinctrl-names = "default"; 807 pinctrl-0 = <&spi2_bus>; 808 num-cs = <1>; 809 status = "disabled"; 810 }; 811 812 timer@10040000 { 813 compatible = "tesla,fsd-mct", "samsung,exynos4210-mct"; 814 reg = <0x0 0x10040000 0x0 0x800>; 815 interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 831 clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>; 832 clock-names = "fin_pll", "mct"; 833 }; 834 835 ufs: ufs@15120000 { 836 compatible = "tesla,fsd-ufs"; 837 reg = <0x0 0x15120000 0x0 0x200>, /* 0: HCI standard */ 838 <0x0 0x15121100 0x0 0x200>, /* 1: Vendor specified */ 839 <0x0 0x15110000 0x0 0x8000>, /* 2: UNIPRO */ 840 <0x0 0x15130000 0x0 0x100>; /* 3: UFS protector */ 841 reg-names = "hci", "vs_hci", "unipro", "ufsp"; 842 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 843 clocks = <&clock_fsys0 UFS0_TOP0_HCLK_BUS>, 844 <&clock_fsys0 UFS0_TOP0_CLK_UNIPRO>; 845 clock-names = "core_clk", "sclk_unipro_main"; 846 freq-table-hz = <0 0>, <0 0>; 847 pinctrl-names = "default"; 848 pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>; 849 phys = <&ufs_phy>; 850 phy-names = "ufs-phy"; 851 status = "disabled"; 852 }; 853 854 ufs_phy: ufs-phy@15124000 { 855 compatible = "tesla,fsd-ufs-phy"; 856 reg = <0x0 0x15124000 0x0 0x800>; 857 reg-names = "phy-pma"; 858 samsung,pmu-syscon = <&pmu_system_controller>; 859 #phy-cells = <0>; 860 clocks = <&clock_fsys0 UFS0_MPHY_REFCLK_IXTAL26>; 861 clock-names = "ref_clk"; 862 }; 863 }; 864}; 865 866#include "fsd-pinctrl.dtsi" 867