1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) 2/* 3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved 4 * Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics. 5 */ 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7 8/ { 9 #address-cells = <2>; 10 #size-cells = <2>; 11 12 cpus { 13 #address-cells = <1>; 14 #size-cells = <0>; 15 16 cpu0: cpu@0 { 17 compatible = "arm,cortex-a35"; 18 device_type = "cpu"; 19 reg = <0>; 20 enable-method = "psci"; 21 }; 22 }; 23 24 arm-pmu { 25 compatible = "arm,cortex-a35-pmu"; 26 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 27 interrupt-affinity = <&cpu0>; 28 interrupt-parent = <&intc>; 29 }; 30 31 arm_wdt: watchdog { 32 compatible = "arm,smc-wdt"; 33 arm,smc-id = <0xb200005a>; 34 status = "disabled"; 35 }; 36 37 clocks { 38 ck_flexgen_08: ck-flexgen-08 { 39 #clock-cells = <0>; 40 compatible = "fixed-clock"; 41 clock-frequency = <100000000>; 42 }; 43 44 ck_flexgen_51: ck-flexgen-51 { 45 #clock-cells = <0>; 46 compatible = "fixed-clock"; 47 clock-frequency = <200000000>; 48 }; 49 50 ck_icn_ls_mcu: ck-icn-ls-mcu { 51 #clock-cells = <0>; 52 compatible = "fixed-clock"; 53 clock-frequency = <200000000>; 54 }; 55 }; 56 57 firmware { 58 optee { 59 compatible = "linaro,optee-tz"; 60 method = "smc"; 61 }; 62 63 scmi { 64 compatible = "linaro,scmi-optee"; 65 #address-cells = <1>; 66 #size-cells = <0>; 67 linaro,optee-channel-id = <0>; 68 69 scmi_clk: protocol@14 { 70 reg = <0x14>; 71 #clock-cells = <1>; 72 }; 73 74 scmi_reset: protocol@16 { 75 reg = <0x16>; 76 #reset-cells = <1>; 77 }; 78 }; 79 }; 80 81 intc: interrupt-controller@4ac00000 { 82 compatible = "arm,cortex-a7-gic"; 83 #interrupt-cells = <3>; 84 #address-cells = <1>; 85 interrupt-controller; 86 reg = <0x0 0x4ac10000 0x0 0x1000>, 87 <0x0 0x4ac20000 0x0 0x2000>, 88 <0x0 0x4ac40000 0x0 0x2000>, 89 <0x0 0x4ac60000 0x0 0x2000>; 90 }; 91 92 psci { 93 compatible = "arm,psci-1.0"; 94 method = "smc"; 95 }; 96 97 timer { 98 compatible = "arm,armv8-timer"; 99 interrupt-parent = <&intc>; 100 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 101 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 102 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 103 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 104 always-on; 105 }; 106 107 soc@0 { 108 compatible = "simple-bus"; 109 #address-cells = <1>; 110 #size-cells = <1>; 111 interrupt-parent = <&intc>; 112 ranges = <0x0 0x0 0x0 0x80000000>; 113 114 rifsc: rifsc-bus@42080000 { 115 compatible = "simple-bus"; 116 reg = <0x42080000 0x1000>; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 ranges; 120 121 usart2: serial@400e0000 { 122 compatible = "st,stm32h7-uart"; 123 reg = <0x400e0000 0x400>; 124 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&ck_flexgen_08>; 126 status = "disabled"; 127 }; 128 129 sdmmc1: mmc@48220000 { 130 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell"; 131 arm,primecell-periphid = <0x00353180>; 132 reg = <0x48220000 0x400>, <0x44230400 0x8>; 133 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 134 clocks = <&ck_flexgen_51>; 135 clock-names = "apb_pclk"; 136 cap-sd-highspeed; 137 cap-mmc-highspeed; 138 max-frequency = <120000000>; 139 status = "disabled"; 140 }; 141 }; 142 143 bsec: efuse@44000000 { 144 compatible = "st,stm32mp25-bsec"; 145 reg = <0x44000000 0x1000>; 146 #address-cells = <1>; 147 #size-cells = <1>; 148 149 part_number_otp@24 { 150 reg = <0x24 0x4>; 151 }; 152 153 package_otp@1e8 { 154 reg = <0x1e8 0x1>; 155 bits = <0 3>; 156 }; 157 }; 158 159 syscfg: syscon@44230000 { 160 compatible = "st,stm32mp25-syscfg", "syscon"; 161 reg = <0x44230000 0x10000>; 162 }; 163 164 pinctrl: pinctrl@44240000 { 165 #address-cells = <1>; 166 #size-cells = <1>; 167 compatible = "st,stm32mp257-pinctrl"; 168 ranges = <0 0x44240000 0xa0400>; 169 pins-are-numbered; 170 171 gpioa: gpio@44240000 { 172 gpio-controller; 173 #gpio-cells = <2>; 174 interrupt-controller; 175 #interrupt-cells = <2>; 176 reg = <0x0 0x400>; 177 clocks = <&ck_icn_ls_mcu>; 178 st,bank-name = "GPIOA"; 179 status = "disabled"; 180 }; 181 182 gpiob: gpio@44250000 { 183 gpio-controller; 184 #gpio-cells = <2>; 185 interrupt-controller; 186 #interrupt-cells = <2>; 187 reg = <0x10000 0x400>; 188 clocks = <&ck_icn_ls_mcu>; 189 st,bank-name = "GPIOB"; 190 status = "disabled"; 191 }; 192 193 gpioc: gpio@44260000 { 194 gpio-controller; 195 #gpio-cells = <2>; 196 interrupt-controller; 197 #interrupt-cells = <2>; 198 reg = <0x20000 0x400>; 199 clocks = <&ck_icn_ls_mcu>; 200 st,bank-name = "GPIOC"; 201 status = "disabled"; 202 }; 203 204 gpiod: gpio@44270000 { 205 gpio-controller; 206 #gpio-cells = <2>; 207 interrupt-controller; 208 #interrupt-cells = <2>; 209 reg = <0x30000 0x400>; 210 clocks = <&ck_icn_ls_mcu>; 211 st,bank-name = "GPIOD"; 212 status = "disabled"; 213 }; 214 215 gpioe: gpio@44280000 { 216 gpio-controller; 217 #gpio-cells = <2>; 218 interrupt-controller; 219 #interrupt-cells = <2>; 220 reg = <0x40000 0x400>; 221 clocks = <&ck_icn_ls_mcu>; 222 st,bank-name = "GPIOE"; 223 status = "disabled"; 224 }; 225 226 gpiof: gpio@44290000 { 227 gpio-controller; 228 #gpio-cells = <2>; 229 interrupt-controller; 230 #interrupt-cells = <2>; 231 reg = <0x50000 0x400>; 232 clocks = <&ck_icn_ls_mcu>; 233 st,bank-name = "GPIOF"; 234 status = "disabled"; 235 }; 236 237 gpiog: gpio@442a0000 { 238 gpio-controller; 239 #gpio-cells = <2>; 240 interrupt-controller; 241 #interrupt-cells = <2>; 242 reg = <0x60000 0x400>; 243 clocks = <&ck_icn_ls_mcu>; 244 st,bank-name = "GPIOG"; 245 status = "disabled"; 246 }; 247 248 gpioh: gpio@442b0000 { 249 gpio-controller; 250 #gpio-cells = <2>; 251 interrupt-controller; 252 #interrupt-cells = <2>; 253 reg = <0x70000 0x400>; 254 clocks = <&ck_icn_ls_mcu>; 255 st,bank-name = "GPIOH"; 256 status = "disabled"; 257 }; 258 259 gpioi: gpio@442c0000 { 260 gpio-controller; 261 #gpio-cells = <2>; 262 interrupt-controller; 263 #interrupt-cells = <2>; 264 reg = <0x80000 0x400>; 265 clocks = <&ck_icn_ls_mcu>; 266 st,bank-name = "GPIOI"; 267 status = "disabled"; 268 }; 269 270 gpioj: gpio@442d0000 { 271 gpio-controller; 272 #gpio-cells = <2>; 273 interrupt-controller; 274 #interrupt-cells = <2>; 275 reg = <0x90000 0x400>; 276 clocks = <&ck_icn_ls_mcu>; 277 st,bank-name = "GPIOJ"; 278 status = "disabled"; 279 }; 280 281 gpiok: gpio@442e0000 { 282 gpio-controller; 283 #gpio-cells = <2>; 284 interrupt-controller; 285 #interrupt-cells = <2>; 286 reg = <0xa0000 0x400>; 287 clocks = <&ck_icn_ls_mcu>; 288 st,bank-name = "GPIOK"; 289 status = "disabled"; 290 }; 291 }; 292 293 pinctrl_z: pinctrl@46200000 { 294 #address-cells = <1>; 295 #size-cells = <1>; 296 compatible = "st,stm32mp257-z-pinctrl"; 297 ranges = <0 0x46200000 0x400>; 298 pins-are-numbered; 299 300 gpioz: gpio@46200000 { 301 gpio-controller; 302 #gpio-cells = <2>; 303 interrupt-controller; 304 #interrupt-cells = <2>; 305 reg = <0 0x400>; 306 clocks = <&ck_icn_ls_mcu>; 307 st,bank-name = "GPIOZ"; 308 st,bank-ioport = <11>; 309 status = "disabled"; 310 }; 311 312 }; 313 }; 314}; 315