1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier PXs3 SoC 4// 5// Copyright (C) 2017 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/gpio/uniphier-gpio.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/thermal/thermal.h> 12 13/ { 14 compatible = "socionext,uniphier-pxs3"; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 interrupt-parent = <&gic>; 18 19 cpus { 20 #address-cells = <2>; 21 #size-cells = <0>; 22 23 cpu-map { 24 cluster0 { 25 core0 { 26 cpu = <&cpu0>; 27 }; 28 core1 { 29 cpu = <&cpu1>; 30 }; 31 core2 { 32 cpu = <&cpu2>; 33 }; 34 core3 { 35 cpu = <&cpu3>; 36 }; 37 }; 38 }; 39 40 cpu0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53"; 43 reg = <0 0x000>; 44 clocks = <&sys_clk 33>; 45 enable-method = "psci"; 46 next-level-cache = <&l2>; 47 operating-points-v2 = <&cluster0_opp>; 48 #cooling-cells = <2>; 49 }; 50 51 cpu1: cpu@1 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 reg = <0 0x001>; 55 clocks = <&sys_clk 33>; 56 enable-method = "psci"; 57 next-level-cache = <&l2>; 58 operating-points-v2 = <&cluster0_opp>; 59 #cooling-cells = <2>; 60 }; 61 62 cpu2: cpu@2 { 63 device_type = "cpu"; 64 compatible = "arm,cortex-a53"; 65 reg = <0 0x002>; 66 clocks = <&sys_clk 33>; 67 enable-method = "psci"; 68 next-level-cache = <&l2>; 69 operating-points-v2 = <&cluster0_opp>; 70 #cooling-cells = <2>; 71 }; 72 73 cpu3: cpu@3 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53"; 76 reg = <0 0x003>; 77 clocks = <&sys_clk 33>; 78 enable-method = "psci"; 79 next-level-cache = <&l2>; 80 operating-points-v2 = <&cluster0_opp>; 81 #cooling-cells = <2>; 82 }; 83 84 l2: l2-cache { 85 compatible = "cache"; 86 }; 87 }; 88 89 cluster0_opp: opp-table { 90 compatible = "operating-points-v2"; 91 opp-shared; 92 93 opp-250000000 { 94 opp-hz = /bits/ 64 <250000000>; 95 clock-latency-ns = <300>; 96 }; 97 opp-325000000 { 98 opp-hz = /bits/ 64 <325000000>; 99 clock-latency-ns = <300>; 100 }; 101 opp-500000000 { 102 opp-hz = /bits/ 64 <500000000>; 103 clock-latency-ns = <300>; 104 }; 105 opp-650000000 { 106 opp-hz = /bits/ 64 <650000000>; 107 clock-latency-ns = <300>; 108 }; 109 opp-666667000 { 110 opp-hz = /bits/ 64 <666667000>; 111 clock-latency-ns = <300>; 112 }; 113 opp-866667000 { 114 opp-hz = /bits/ 64 <866667000>; 115 clock-latency-ns = <300>; 116 }; 117 opp-1000000000 { 118 opp-hz = /bits/ 64 <1000000000>; 119 clock-latency-ns = <300>; 120 }; 121 opp-1300000000 { 122 opp-hz = /bits/ 64 <1300000000>; 123 clock-latency-ns = <300>; 124 }; 125 }; 126 127 psci { 128 compatible = "arm,psci-1.0"; 129 method = "smc"; 130 }; 131 132 clocks { 133 refclk: ref { 134 compatible = "fixed-clock"; 135 #clock-cells = <0>; 136 clock-frequency = <25000000>; 137 }; 138 }; 139 140 emmc_pwrseq: emmc-pwrseq { 141 compatible = "mmc-pwrseq-emmc"; 142 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(5, 7) GPIO_ACTIVE_LOW>; 143 }; 144 145 timer { 146 compatible = "arm,armv8-timer"; 147 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 151 }; 152 153 thermal-zones { 154 cpu-thermal { 155 polling-delay-passive = <250>; /* 250ms */ 156 polling-delay = <1000>; /* 1000ms */ 157 thermal-sensors = <&pvtctl>; 158 159 trips { 160 cpu_crit: cpu-crit { 161 temperature = <110000>; /* 110C */ 162 hysteresis = <2000>; 163 type = "critical"; 164 }; 165 cpu_alert: cpu-alert { 166 temperature = <100000>; /* 100C */ 167 hysteresis = <2000>; 168 type = "passive"; 169 }; 170 }; 171 172 cooling-maps { 173 map0 { 174 trip = <&cpu_alert>; 175 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 176 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 177 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 178 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 179 }; 180 }; 181 }; 182 }; 183 184 reserved-memory { 185 #address-cells = <2>; 186 #size-cells = <2>; 187 ranges; 188 189 secure-memory@81000000 { 190 reg = <0x0 0x81000000 0x0 0x01000000>; 191 no-map; 192 }; 193 }; 194 195 soc@0 { 196 compatible = "simple-bus"; 197 #address-cells = <1>; 198 #size-cells = <1>; 199 ranges = <0 0 0 0xffffffff>; 200 201 spi0: spi@54006000 { 202 compatible = "socionext,uniphier-scssi"; 203 status = "disabled"; 204 reg = <0x54006000 0x100>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 208 pinctrl-names = "default"; 209 pinctrl-0 = <&pinctrl_spi0>; 210 clocks = <&peri_clk 11>; 211 resets = <&peri_rst 11>; 212 }; 213 214 spi1: spi@54006100 { 215 compatible = "socionext,uniphier-scssi"; 216 status = "disabled"; 217 reg = <0x54006100 0x100>; 218 #address-cells = <1>; 219 #size-cells = <0>; 220 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 221 pinctrl-names = "default"; 222 pinctrl-0 = <&pinctrl_spi1>; 223 clocks = <&peri_clk 12>; 224 resets = <&peri_rst 12>; 225 }; 226 227 serial0: serial@54006800 { 228 compatible = "socionext,uniphier-uart"; 229 status = "disabled"; 230 reg = <0x54006800 0x40>; 231 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 232 pinctrl-names = "default"; 233 pinctrl-0 = <&pinctrl_uart0>; 234 clocks = <&peri_clk 0>; 235 resets = <&peri_rst 0>; 236 }; 237 238 serial1: serial@54006900 { 239 compatible = "socionext,uniphier-uart"; 240 status = "disabled"; 241 reg = <0x54006900 0x40>; 242 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 243 pinctrl-names = "default"; 244 pinctrl-0 = <&pinctrl_uart1>; 245 clocks = <&peri_clk 1>; 246 resets = <&peri_rst 1>; 247 }; 248 249 serial2: serial@54006a00 { 250 compatible = "socionext,uniphier-uart"; 251 status = "disabled"; 252 reg = <0x54006a00 0x40>; 253 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 254 pinctrl-names = "default"; 255 pinctrl-0 = <&pinctrl_uart2>; 256 clocks = <&peri_clk 2>; 257 resets = <&peri_rst 2>; 258 }; 259 260 serial3: serial@54006b00 { 261 compatible = "socionext,uniphier-uart"; 262 status = "disabled"; 263 reg = <0x54006b00 0x40>; 264 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 265 pinctrl-names = "default"; 266 pinctrl-0 = <&pinctrl_uart3>; 267 clocks = <&peri_clk 3>; 268 resets = <&peri_rst 3>; 269 }; 270 271 gpio: gpio@55000000 { 272 compatible = "socionext,uniphier-gpio"; 273 reg = <0x55000000 0x200>; 274 interrupt-parent = <&aidet>; 275 interrupt-controller; 276 #interrupt-cells = <2>; 277 gpio-controller; 278 #gpio-cells = <2>; 279 gpio-ranges = <&pinctrl 0 0 0>, 280 <&pinctrl 104 0 0>, 281 <&pinctrl 168 0 0>; 282 gpio-ranges-group-names = "gpio_range0", 283 "gpio_range1", 284 "gpio_range2"; 285 ngpios = <286>; 286 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, 287 <21 217 3>; 288 }; 289 290 i2c0: i2c@58780000 { 291 compatible = "socionext,uniphier-fi2c"; 292 status = "disabled"; 293 reg = <0x58780000 0x80>; 294 #address-cells = <1>; 295 #size-cells = <0>; 296 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 297 pinctrl-names = "default"; 298 pinctrl-0 = <&pinctrl_i2c0>; 299 clocks = <&peri_clk 4>; 300 resets = <&peri_rst 4>; 301 clock-frequency = <100000>; 302 }; 303 304 i2c1: i2c@58781000 { 305 compatible = "socionext,uniphier-fi2c"; 306 status = "disabled"; 307 reg = <0x58781000 0x80>; 308 #address-cells = <1>; 309 #size-cells = <0>; 310 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 311 pinctrl-names = "default"; 312 pinctrl-0 = <&pinctrl_i2c1>; 313 clocks = <&peri_clk 5>; 314 resets = <&peri_rst 5>; 315 clock-frequency = <100000>; 316 }; 317 318 i2c2: i2c@58782000 { 319 compatible = "socionext,uniphier-fi2c"; 320 status = "disabled"; 321 reg = <0x58782000 0x80>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 325 pinctrl-names = "default"; 326 pinctrl-0 = <&pinctrl_i2c2>; 327 clocks = <&peri_clk 6>; 328 resets = <&peri_rst 6>; 329 clock-frequency = <100000>; 330 }; 331 332 i2c3: i2c@58783000 { 333 compatible = "socionext,uniphier-fi2c"; 334 status = "disabled"; 335 reg = <0x58783000 0x80>; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 339 pinctrl-names = "default"; 340 pinctrl-0 = <&pinctrl_i2c3>; 341 clocks = <&peri_clk 7>; 342 resets = <&peri_rst 7>; 343 clock-frequency = <100000>; 344 }; 345 346 /* chip-internal connection for HDMI */ 347 i2c6: i2c@58786000 { 348 compatible = "socionext,uniphier-fi2c"; 349 reg = <0x58786000 0x80>; 350 #address-cells = <1>; 351 #size-cells = <0>; 352 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 353 clocks = <&peri_clk 10>; 354 resets = <&peri_rst 10>; 355 clock-frequency = <400000>; 356 }; 357 358 system_bus: system-bus@58c00000 { 359 compatible = "socionext,uniphier-system-bus"; 360 status = "disabled"; 361 reg = <0x58c00000 0x400>; 362 #address-cells = <2>; 363 #size-cells = <1>; 364 pinctrl-names = "default"; 365 pinctrl-0 = <&pinctrl_system_bus>; 366 }; 367 368 smpctrl@59801000 { 369 compatible = "socionext,uniphier-smpctrl"; 370 reg = <0x59801000 0x400>; 371 }; 372 373 sdctrl: syscon@59810000 { 374 compatible = "socionext,uniphier-pxs3-sdctrl", 375 "simple-mfd", "syscon"; 376 reg = <0x59810000 0x400>; 377 378 sd_clk: clock-controller { 379 compatible = "socionext,uniphier-pxs3-sd-clock"; 380 #clock-cells = <1>; 381 }; 382 383 sd_rst: reset-controller { 384 compatible = "socionext,uniphier-pxs3-sd-reset"; 385 #reset-cells = <1>; 386 }; 387 }; 388 389 syscon@59820000 { 390 compatible = "socionext,uniphier-pxs3-perictrl", 391 "simple-mfd", "syscon"; 392 reg = <0x59820000 0x200>; 393 394 peri_clk: clock-controller { 395 compatible = "socionext,uniphier-pxs3-peri-clock"; 396 #clock-cells = <1>; 397 }; 398 399 peri_rst: reset-controller { 400 compatible = "socionext,uniphier-pxs3-peri-reset"; 401 #reset-cells = <1>; 402 }; 403 }; 404 405 emmc: mmc@5a000000 { 406 compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc"; 407 reg = <0x5a000000 0x400>; 408 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 409 pinctrl-names = "default"; 410 pinctrl-0 = <&pinctrl_emmc>; 411 clocks = <&sys_clk 4>; 412 resets = <&sys_rst 4>; 413 bus-width = <8>; 414 mmc-ddr-1_8v; 415 mmc-hs200-1_8v; 416 mmc-pwrseq = <&emmc_pwrseq>; 417 cdns,phy-input-delay-legacy = <9>; 418 cdns,phy-input-delay-mmc-highspeed = <2>; 419 cdns,phy-input-delay-mmc-ddr = <3>; 420 cdns,phy-dll-delay-sdclk = <21>; 421 cdns,phy-dll-delay-sdclk-hsmmc = <21>; 422 }; 423 424 sd: mmc@5a400000 { 425 compatible = "socionext,uniphier-sd-v3.1.1"; 426 status = "disabled"; 427 reg = <0x5a400000 0x800>; 428 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 429 pinctrl-names = "default", "uhs"; 430 pinctrl-0 = <&pinctrl_sd>; 431 pinctrl-1 = <&pinctrl_sd_uhs>; 432 clocks = <&sd_clk 0>; 433 reset-names = "host"; 434 resets = <&sd_rst 0>; 435 bus-width = <4>; 436 cap-sd-highspeed; 437 sd-uhs-sdr12; 438 sd-uhs-sdr25; 439 sd-uhs-sdr50; 440 socionext,syscon-uhs-mode = <&sdctrl 0>; 441 }; 442 443 soc_glue: syscon@5f800000 { 444 compatible = "socionext,uniphier-pxs3-soc-glue", 445 "simple-mfd", "syscon"; 446 reg = <0x5f800000 0x2000>; 447 448 pinctrl: pinctrl { 449 compatible = "socionext,uniphier-pxs3-pinctrl"; 450 }; 451 }; 452 453 syscon@5f900000 { 454 compatible = "socionext,uniphier-pxs3-soc-glue-debug", 455 "simple-mfd", "syscon"; 456 reg = <0x5f900000 0x2000>; 457 #address-cells = <1>; 458 #size-cells = <1>; 459 ranges = <0 0x5f900000 0x2000>; 460 461 efuse@100 { 462 compatible = "socionext,uniphier-efuse"; 463 reg = <0x100 0x28>; 464 }; 465 466 efuse@200 { 467 compatible = "socionext,uniphier-efuse"; 468 reg = <0x200 0x68>; 469 #address-cells = <1>; 470 #size-cells = <1>; 471 472 /* USB cells */ 473 usb_rterm0: trim@54,4 { 474 reg = <0x54 1>; 475 bits = <4 2>; 476 }; 477 usb_rterm1: trim@55,4 { 478 reg = <0x55 1>; 479 bits = <4 2>; 480 }; 481 usb_rterm2: trim@58,4 { 482 reg = <0x58 1>; 483 bits = <4 2>; 484 }; 485 usb_rterm3: trim@59,4 { 486 reg = <0x59 1>; 487 bits = <4 2>; 488 }; 489 usb_sel_t0: trim@54,0 { 490 reg = <0x54 1>; 491 bits = <0 4>; 492 }; 493 usb_sel_t1: trim@55,0 { 494 reg = <0x55 1>; 495 bits = <0 4>; 496 }; 497 usb_sel_t2: trim@58,0 { 498 reg = <0x58 1>; 499 bits = <0 4>; 500 }; 501 usb_sel_t3: trim@59,0 { 502 reg = <0x59 1>; 503 bits = <0 4>; 504 }; 505 usb_hs_i0: trim@56,0 { 506 reg = <0x56 1>; 507 bits = <0 4>; 508 }; 509 usb_hs_i2: trim@5a,0 { 510 reg = <0x5a 1>; 511 bits = <0 4>; 512 }; 513 }; 514 }; 515 516 xdmac: dma-controller@5fc10000 { 517 compatible = "socionext,uniphier-xdmac"; 518 reg = <0x5fc10000 0x5300>; 519 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 520 dma-channels = <16>; 521 #dma-cells = <2>; 522 }; 523 524 aidet: interrupt-controller@5fc20000 { 525 compatible = "socionext,uniphier-pxs3-aidet"; 526 reg = <0x5fc20000 0x200>; 527 interrupt-controller; 528 #interrupt-cells = <2>; 529 }; 530 531 gic: interrupt-controller@5fe00000 { 532 compatible = "arm,gic-v3"; 533 reg = <0x5fe00000 0x10000>, /* GICD */ 534 <0x5fe80000 0x80000>; /* GICR */ 535 interrupt-controller; 536 #interrupt-cells = <3>; 537 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 538 }; 539 540 syscon@61840000 { 541 compatible = "socionext,uniphier-pxs3-sysctrl", 542 "simple-mfd", "syscon"; 543 reg = <0x61840000 0x10000>; 544 545 sys_clk: clock-controller { 546 compatible = "socionext,uniphier-pxs3-clock"; 547 #clock-cells = <1>; 548 }; 549 550 sys_rst: reset-controller { 551 compatible = "socionext,uniphier-pxs3-reset"; 552 #reset-cells = <1>; 553 }; 554 555 watchdog { 556 compatible = "socionext,uniphier-wdt"; 557 }; 558 559 pvtctl: thermal-sensor { 560 compatible = "socionext,uniphier-pxs3-thermal"; 561 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 562 #thermal-sensor-cells = <0>; 563 socionext,tmod-calibration = <0x0f22 0x68ee>; 564 }; 565 }; 566 567 eth0: ethernet@65000000 { 568 compatible = "socionext,uniphier-pxs3-ave4"; 569 status = "disabled"; 570 reg = <0x65000000 0x8500>; 571 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 572 pinctrl-names = "default"; 573 pinctrl-0 = <&pinctrl_ether_rgmii>; 574 clock-names = "ether"; 575 clocks = <&sys_clk 6>; 576 reset-names = "ether"; 577 resets = <&sys_rst 6>; 578 phy-mode = "rgmii-id"; 579 local-mac-address = [00 00 00 00 00 00]; 580 socionext,syscon-phy-mode = <&soc_glue 0>; 581 582 mdio0: mdio { 583 #address-cells = <1>; 584 #size-cells = <0>; 585 }; 586 }; 587 588 eth1: ethernet@65200000 { 589 compatible = "socionext,uniphier-pxs3-ave4"; 590 status = "disabled"; 591 reg = <0x65200000 0x8500>; 592 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 593 pinctrl-names = "default"; 594 pinctrl-0 = <&pinctrl_ether1_rgmii>; 595 clock-names = "ether"; 596 clocks = <&sys_clk 7>; 597 reset-names = "ether"; 598 resets = <&sys_rst 7>; 599 phy-mode = "rgmii-id"; 600 local-mac-address = [00 00 00 00 00 00]; 601 socionext,syscon-phy-mode = <&soc_glue 1>; 602 603 mdio1: mdio { 604 #address-cells = <1>; 605 #size-cells = <0>; 606 }; 607 }; 608 609 ahci0: sata@65600000 { 610 compatible = "socionext,uniphier-pxs3-ahci", 611 "generic-ahci"; 612 status = "disabled"; 613 reg = <0x65600000 0x10000>; 614 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&sys_clk 28>; 616 resets = <&sys_rst 28>, <&ahci0_rst 0>; 617 ports-implemented = <1>; 618 phys = <&ahci0_phy>; 619 }; 620 621 sata-controller@65700000 { 622 compatible = "socionext,uniphier-pxs3-ahci-glue", 623 "simple-mfd"; 624 reg = <0x65700000 0x100>; 625 #address-cells = <1>; 626 #size-cells = <1>; 627 ranges = <0 0x65700000 0x100>; 628 629 ahci0_rst: reset-controller@0 { 630 compatible = "socionext,uniphier-pxs3-ahci-reset"; 631 reg = <0x0 0x4>; 632 clock-names = "link"; 633 clocks = <&sys_clk 28>; 634 reset-names = "link"; 635 resets = <&sys_rst 28>; 636 #reset-cells = <1>; 637 }; 638 639 ahci0_phy: sata-phy@10 { 640 compatible = "socionext,uniphier-pxs3-ahci-phy"; 641 reg = <0x10 0x10>; 642 clock-names = "link", "phy"; 643 clocks = <&sys_clk 28>, <&sys_clk 30>; 644 reset-names = "link", "phy"; 645 resets = <&sys_rst 28>, <&sys_rst 30>; 646 #phy-cells = <0>; 647 }; 648 }; 649 650 ahci1: sata@65800000 { 651 compatible = "socionext,uniphier-pxs3-ahci", 652 "generic-ahci"; 653 status = "disabled"; 654 reg = <0x65800000 0x10000>; 655 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&sys_clk 29>; 657 resets = <&sys_rst 29>, <&ahci1_rst 0>; 658 ports-implemented = <1>; 659 phys = <&ahci1_phy>; 660 }; 661 662 sata-controller@65900000 { 663 compatible = "socionext,uniphier-pxs3-ahci-glue", 664 "simple-mfd"; 665 reg = <0x65900000 0x100>; 666 #address-cells = <1>; 667 #size-cells = <1>; 668 ranges = <0 0x65900000 0x100>; 669 670 ahci1_rst: reset-controller@0 { 671 compatible = "socionext,uniphier-pxs3-ahci-reset"; 672 reg = <0x0 0x4>; 673 clock-names = "link"; 674 clocks = <&sys_clk 29>; 675 reset-names = "link"; 676 resets = <&sys_rst 29>; 677 #reset-cells = <1>; 678 }; 679 680 ahci1_phy: sata-phy@10 { 681 compatible = "socionext,uniphier-pxs3-ahci-phy"; 682 reg = <0x10 0x10>; 683 clock-names = "link", "phy"; 684 clocks = <&sys_clk 29>, <&sys_clk 30>; 685 reset-names = "link", "phy"; 686 resets = <&sys_rst 29>, <&sys_rst 30>; 687 #phy-cells = <0>; 688 }; 689 }; 690 691 usb0: usb@65a00000 { 692 compatible = "socionext,uniphier-dwc3", "snps,dwc3"; 693 status = "disabled"; 694 reg = <0x65a00000 0xcd00>; 695 interrupt-names = "dwc_usb3"; 696 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 697 pinctrl-names = "default"; 698 pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>; 699 clock-names = "ref", "bus_early", "suspend"; 700 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>; 701 resets = <&usb0_rst 15>; 702 phys = <&usb0_hsphy0>, <&usb0_hsphy1>, 703 <&usb0_ssphy0>, <&usb0_ssphy1>; 704 dr_mode = "host"; 705 }; 706 707 usb-controller@65b00000 { 708 compatible = "socionext,uniphier-pxs3-dwc3-glue", 709 "simple-mfd"; 710 reg = <0x65b00000 0x400>; 711 #address-cells = <1>; 712 #size-cells = <1>; 713 ranges = <0 0x65b00000 0x400>; 714 715 usb0_rst: reset-controller@0 { 716 compatible = "socionext,uniphier-pxs3-usb3-reset"; 717 reg = <0x0 0x4>; 718 #reset-cells = <1>; 719 clock-names = "link"; 720 clocks = <&sys_clk 12>; 721 reset-names = "link"; 722 resets = <&sys_rst 12>; 723 }; 724 725 usb0_vbus0: regulator@100 { 726 compatible = "socionext,uniphier-pxs3-usb3-regulator"; 727 reg = <0x100 0x10>; 728 clock-names = "link"; 729 clocks = <&sys_clk 12>; 730 reset-names = "link"; 731 resets = <&sys_rst 12>; 732 }; 733 734 usb0_vbus1: regulator@110 { 735 compatible = "socionext,uniphier-pxs3-usb3-regulator"; 736 reg = <0x110 0x10>; 737 clock-names = "link"; 738 clocks = <&sys_clk 12>; 739 reset-names = "link"; 740 resets = <&sys_rst 12>; 741 }; 742 743 usb0_hsphy0: phy@200 { 744 compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 745 reg = <0x200 0x10>; 746 #phy-cells = <0>; 747 clock-names = "link", "phy"; 748 clocks = <&sys_clk 12>, <&sys_clk 16>; 749 reset-names = "link", "phy"; 750 resets = <&sys_rst 12>, <&sys_rst 16>; 751 vbus-supply = <&usb0_vbus0>; 752 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 753 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, 754 <&usb_hs_i0>; 755 }; 756 757 usb0_hsphy1: phy@210 { 758 compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 759 reg = <0x210 0x10>; 760 #phy-cells = <0>; 761 clock-names = "link", "phy"; 762 clocks = <&sys_clk 12>, <&sys_clk 16>; 763 reset-names = "link", "phy"; 764 resets = <&sys_rst 12>, <&sys_rst 16>; 765 vbus-supply = <&usb0_vbus1>; 766 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 767 nvmem-cells = <&usb_rterm1>, <&usb_sel_t1>, 768 <&usb_hs_i0>; 769 }; 770 771 usb0_ssphy0: phy@300 { 772 compatible = "socionext,uniphier-pxs3-usb3-ssphy"; 773 reg = <0x300 0x10>; 774 #phy-cells = <0>; 775 clock-names = "link", "phy"; 776 clocks = <&sys_clk 12>, <&sys_clk 17>; 777 reset-names = "link", "phy"; 778 resets = <&sys_rst 12>, <&sys_rst 17>; 779 vbus-supply = <&usb0_vbus0>; 780 }; 781 782 usb0_ssphy1: phy@310 { 783 compatible = "socionext,uniphier-pxs3-usb3-ssphy"; 784 reg = <0x310 0x10>; 785 #phy-cells = <0>; 786 clock-names = "link", "phy"; 787 clocks = <&sys_clk 12>, <&sys_clk 18>; 788 reset-names = "link", "phy"; 789 resets = <&sys_rst 12>, <&sys_rst 18>; 790 vbus-supply = <&usb0_vbus1>; 791 }; 792 }; 793 794 usb1: usb@65c00000 { 795 compatible = "socionext,uniphier-dwc3", "snps,dwc3"; 796 status = "disabled"; 797 reg = <0x65c00000 0xcd00>; 798 interrupt-names = "dwc_usb3"; 799 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 800 pinctrl-names = "default"; 801 pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>; 802 clock-names = "ref", "bus_early", "suspend"; 803 clocks = <&sys_clk 13>, <&sys_clk 13>, <&sys_clk 13>; 804 resets = <&usb1_rst 15>; 805 phys = <&usb1_hsphy0>, <&usb1_hsphy1>, 806 <&usb1_ssphy0>; 807 dr_mode = "host"; 808 }; 809 810 usb-controller@65d00000 { 811 compatible = "socionext,uniphier-pxs3-dwc3-glue", 812 "simple-mfd"; 813 reg = <0x65d00000 0x400>; 814 #address-cells = <1>; 815 #size-cells = <1>; 816 ranges = <0 0x65d00000 0x400>; 817 818 usb1_rst: reset-controller@0 { 819 compatible = "socionext,uniphier-pxs3-usb3-reset"; 820 reg = <0x0 0x4>; 821 #reset-cells = <1>; 822 clock-names = "link"; 823 clocks = <&sys_clk 13>; 824 reset-names = "link"; 825 resets = <&sys_rst 13>; 826 }; 827 828 usb1_vbus0: regulator@100 { 829 compatible = "socionext,uniphier-pxs3-usb3-regulator"; 830 reg = <0x100 0x10>; 831 clock-names = "link"; 832 clocks = <&sys_clk 13>; 833 reset-names = "link"; 834 resets = <&sys_rst 13>; 835 }; 836 837 usb1_vbus1: regulator@110 { 838 compatible = "socionext,uniphier-pxs3-usb3-regulator"; 839 reg = <0x110 0x10>; 840 clock-names = "link"; 841 clocks = <&sys_clk 13>; 842 reset-names = "link"; 843 resets = <&sys_rst 13>; 844 }; 845 846 usb1_hsphy0: phy@200 { 847 compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 848 reg = <0x200 0x10>; 849 #phy-cells = <0>; 850 clock-names = "link", "phy", "phy-ext"; 851 clocks = <&sys_clk 13>, <&sys_clk 20>, 852 <&sys_clk 14>; 853 reset-names = "link", "phy"; 854 resets = <&sys_rst 13>, <&sys_rst 20>; 855 vbus-supply = <&usb1_vbus0>; 856 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 857 nvmem-cells = <&usb_rterm2>, <&usb_sel_t2>, 858 <&usb_hs_i2>; 859 }; 860 861 usb1_hsphy1: phy@210 { 862 compatible = "socionext,uniphier-pxs3-usb3-hsphy"; 863 reg = <0x210 0x10>; 864 #phy-cells = <0>; 865 clock-names = "link", "phy", "phy-ext"; 866 clocks = <&sys_clk 13>, <&sys_clk 20>, 867 <&sys_clk 14>; 868 reset-names = "link", "phy"; 869 resets = <&sys_rst 13>, <&sys_rst 20>; 870 vbus-supply = <&usb1_vbus1>; 871 nvmem-cell-names = "rterm", "sel_t", "hs_i"; 872 nvmem-cells = <&usb_rterm3>, <&usb_sel_t3>, 873 <&usb_hs_i2>; 874 }; 875 876 usb1_ssphy0: phy@300 { 877 compatible = "socionext,uniphier-pxs3-usb3-ssphy"; 878 reg = <0x300 0x10>; 879 #phy-cells = <0>; 880 clock-names = "link", "phy", "phy-ext"; 881 clocks = <&sys_clk 13>, <&sys_clk 21>, 882 <&sys_clk 14>; 883 reset-names = "link", "phy"; 884 resets = <&sys_rst 13>, <&sys_rst 21>; 885 vbus-supply = <&usb1_vbus0>; 886 }; 887 }; 888 889 pcie: pcie@66000000 { 890 compatible = "socionext,uniphier-pcie"; 891 status = "disabled"; 892 reg-names = "dbi", "link", "config"; 893 reg = <0x66000000 0x1000>, <0x66010000 0x10000>, 894 <0x2fff0000 0x10000>; 895 #address-cells = <3>; 896 #size-cells = <2>; 897 clocks = <&sys_clk 24>; 898 resets = <&sys_rst 24>; 899 num-lanes = <1>; 900 num-viewport = <1>; 901 bus-range = <0x0 0xff>; 902 device_type = "pci"; 903 ranges = 904 /* downstream I/O */ 905 <0x81000000 0 0x00000000 0x2ffe0000 0 0x00010000>, 906 /* non-prefetchable memory */ 907 <0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>; 908 #interrupt-cells = <1>; 909 interrupt-names = "dma", "msi"; 910 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 912 interrupt-map-mask = <0 0 0 7>; 913 interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */ 914 <0 0 0 2 &pcie_intc 1>, /* INTB */ 915 <0 0 0 3 &pcie_intc 2>, /* INTC */ 916 <0 0 0 4 &pcie_intc 3>; /* INTD */ 917 phy-names = "pcie-phy"; 918 phys = <&pcie_phy>; 919 920 pcie_intc: legacy-interrupt-controller { 921 interrupt-controller; 922 #interrupt-cells = <1>; 923 interrupt-parent = <&gic>; 924 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 925 }; 926 }; 927 928 pcie_phy: phy@66038000 { 929 compatible = "socionext,uniphier-pxs3-pcie-phy"; 930 reg = <0x66038000 0x4000>; 931 #phy-cells = <0>; 932 clock-names = "link"; 933 clocks = <&sys_clk 24>; 934 reset-names = "link"; 935 resets = <&sys_rst 24>; 936 socionext,syscon = <&soc_glue>; 937 }; 938 939 nand: nand-controller@68000000 { 940 compatible = "socionext,uniphier-denali-nand-v5b"; 941 status = "disabled"; 942 reg-names = "nand_data", "denali_reg"; 943 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 944 #address-cells = <1>; 945 #size-cells = <0>; 946 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 947 pinctrl-names = "default"; 948 pinctrl-0 = <&pinctrl_nand>; 949 clock-names = "nand", "nand_x", "ecc"; 950 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>; 951 reset-names = "nand", "reg"; 952 resets = <&sys_rst 2>, <&sys_rst 2>; 953 }; 954 }; 955}; 956 957#include "uniphier-pinctrl.dtsi" 958