1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Theobroma Systems Design und Consulting GmbH 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/leds/common.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include "rk8xx.h" 10#include "rk3588.dtsi" 11 12/ { 13 compatible = "tsd,rk3588-tiger", "rockchip,rk3588"; 14 15 aliases { 16 i2c10 = &i2c10; 17 mmc0 = &sdhci; 18 rtc0 = &rtc_twi; 19 }; 20 21 emmc_pwrseq: emmc-pwrseq { 22 compatible = "mmc-pwrseq-emmc"; 23 pinctrl-0 = <&emmc_reset>; 24 pinctrl-names = "default"; 25 reset-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; 26 }; 27 28 extcon_usb3: extcon-usb3 { 29 compatible = "linux,extcon-usb-gpio"; 30 id-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; 31 pinctrl-names = "default"; 32 pinctrl-0 = <&usb3_id>; 33 status = "disabled"; 34 }; 35 36 leds { 37 compatible = "gpio-leds"; 38 pinctrl-names = "default"; 39 pinctrl-0 = <&module_led_pin>; 40 41 /* Named LED1 on the board */ 42 led-1 { 43 gpios = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; 44 function = LED_FUNCTION_HEARTBEAT; 45 linux,default-trigger = "heartbeat"; 46 color = <LED_COLOR_ID_AMBER>; 47 }; 48 }; 49 50 /* 51 * 100MHz reference clock for PCIe peripherals from PI6C557-05BLE 52 * clock generator. 53 * The clock output is gated via the OE pin on the clock generator. 54 * This is modeled as a fixed-clock plus a gpio-gate-clock. 55 */ 56 pcie_refclk_gen: pcie-refclk-gen-clock { 57 compatible = "fixed-clock"; 58 #clock-cells = <0>; 59 clock-frequency = <100000000>; 60 }; 61 62 pcie_refclk: pcie-refclk-clock { 63 compatible = "gpio-gate-clock"; 64 clocks = <&pcie_refclk_gen>; 65 #clock-cells = <0>; 66 enable-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; /* PCIE30X4_CLKREQN_M1_L */ 67 }; 68 69 vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { 70 compatible = "regulator-fixed"; 71 regulator-name = "vcc_1v1_nldo_s3"; 72 regulator-always-on; 73 regulator-boot-on; 74 regulator-min-microvolt = <1100000>; 75 regulator-max-microvolt = <1100000>; 76 vin-supply = <&vcc5v0_sys>; 77 }; 78 79 vcc_1v2_s3: regulator-vcc-1v2-s3 { 80 compatible = "regulator-fixed"; 81 regulator-name = "vcc_1v2_s3"; 82 regulator-always-on; 83 regulator-boot-on; 84 regulator-min-microvolt = <1200000>; 85 regulator-max-microvolt = <1200000>; 86 vin-supply = <&vcc5v0_sys>; 87 }; 88 89 vcc5v0_sys: regulator-vcc5v0-sys { 90 compatible = "regulator-fixed"; 91 regulator-name = "vcc5v0_sys"; 92 regulator-always-on; 93 regulator-boot-on; 94 regulator-min-microvolt = <5000000>; 95 regulator-max-microvolt = <5000000>; 96 vin-supply = <&vcc5v0_baseboard>; 97 }; 98}; 99 100&cpu_b0 { 101 cpu-supply = <&vdd_cpu_big0_s0>; 102}; 103 104&cpu_b1 { 105 cpu-supply = <&vdd_cpu_big0_s0>; 106}; 107 108&cpu_b2 { 109 cpu-supply = <&vdd_cpu_big1_s0>; 110}; 111 112&cpu_b3 { 113 cpu-supply = <&vdd_cpu_big1_s0>; 114}; 115 116&cpu_l0 { 117 cpu-supply = <&vdd_cpu_lit_s0>; 118}; 119 120&cpu_l1 { 121 cpu-supply = <&vdd_cpu_lit_s0>; 122}; 123 124&cpu_l2 { 125 cpu-supply = <&vdd_cpu_lit_s0>; 126}; 127 128&cpu_l3 { 129 cpu-supply = <&vdd_cpu_lit_s0>; 130}; 131 132&gmac0 { 133 clock_in_out = "output"; 134 phy-handle = <&rgmii_phy>; 135 phy-mode = "rgmii"; 136 phy-supply = <&vcc_1v2_s3>; 137 pinctrl-names = "default"; 138 pinctrl-0 = <&gmac0_miim 139 &gmac0_rx_bus2 140 &gmac0_tx_bus2 141 &gmac0_rgmii_clk 142 &gmac0_rgmii_bus 143 ð0_pins 144 ð_reset>; 145 tx_delay = <0x10>; 146 rx_delay = <0x10>; 147 snps,reset-gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>; 148 snps,reset-active-low; 149 snps,reset-delays-us = <0 10000 100000>; 150}; 151 152&gpu { 153 mali-supply = <&vdd_gpu_s0>; 154 status = "okay"; 155}; 156 157&hdmi0 { 158 pinctrl-names = "default"; 159 pinctrl-0 = <&hdmim1_tx0_cec &hdmim0_tx0_hpd &hdmim1_tx0_scl 160 &hdmim1_tx0_sda>; 161}; 162 163&i2c1 { 164 pinctrl-0 = <&i2c1m0_xfer>; 165}; 166 167&i2c1m0_xfer { 168 rockchip,pins = 169 /* i2c1_scl_m0 */ 170 <0 RK_PB5 9 &pcfg_pull_none_drv_level_0>, 171 /* i2c1_sda_m0 */ 172 <0 RK_PB6 9 &pcfg_pull_none_drv_level_0>; 173}; 174 175&i2c2 { 176 pinctrl-0 = <&i2c2m3_xfer>; 177}; 178 179&i2c2m3_xfer { 180 rockchip,pins = 181 /* i2c2_scl_m3 */ 182 <1 RK_PC5 9 &pcfg_pull_none_drv_level_0>, 183 /* i2c2_sda_m3 */ 184 <1 RK_PC4 9 &pcfg_pull_none_drv_level_0>; 185}; 186 187&i2c3 { 188 pinctrl-0 = <&i2c3m0_xfer>; 189}; 190 191&i2c4 { 192 pinctrl-0 = <&i2c4m4_xfer>; 193 status = "okay"; 194 195 vdd_npu_s0: regulator@42 { 196 compatible = "rockchip,rk8602"; 197 reg = <0x42>; 198 fcs,suspend-voltage-selector = <1>; 199 regulator-name = "vdd_npu_s0"; 200 regulator-always-on; 201 regulator-boot-on; 202 regulator-min-microvolt = <550000>; 203 regulator-max-microvolt = <950000>; 204 regulator-ramp-delay = <2300>; 205 vin-supply = <&vcc5v0_sys>; 206 207 regulator-state-mem { 208 regulator-off-in-suspend; 209 }; 210 }; 211}; 212 213&i2c5 { 214 pinctrl-0 = <&i2c5m1_xfer>; 215}; 216 217&i2c5m1_xfer { 218 rockchip,pins = 219 /* i2c5_scl_m1 */ 220 <4 RK_PB6 9 &pcfg_pull_none_drv_level_0>, 221 /* i2c5_sda_m1 */ 222 <4 RK_PB7 9 &pcfg_pull_none_drv_level_0>; 223}; 224 225&i2c6 { 226 /* 227 * Mule-ATtiny can handle up to Fast mode Plus (1MHz) on I2C bus, 228 * but SOC can handle only up to (400kHz). 229 */ 230 clock-frequency = <400000>; 231 status = "okay"; 232 233 fan@18 { 234 compatible = "tsd,mule", "ti,amc6821"; 235 reg = <0x18>; 236 237 i2c-mux { 238 compatible = "tsd,mule-i2c-mux"; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 242 i2c10: i2c@0 { 243 reg = <0x0>; 244 #address-cells = <1>; 245 #size-cells = <0>; 246 247 rtc_twi: rtc@6f { 248 compatible = "isil,isl1208"; 249 reg = <0x6f>; 250 }; 251 }; 252 }; 253 }; 254}; 255 256&i2c6m0_xfer { 257 rockchip,pins = 258 /* i2c6_scl_m0 */ 259 <0 RK_PD0 9 &pcfg_pull_none_drv_level_0>, 260 /* i2c6_sda_m0 */ 261 <0 RK_PC7 9 &pcfg_pull_none_drv_level_0>; 262}; 263 264&i2c7 { 265 status = "okay"; 266 267 vdd_cpu_big0_s0: regulator@42 { 268 compatible = "rockchip,rk8602"; 269 reg = <0x42>; 270 fcs,suspend-voltage-selector = <1>; 271 regulator-name = "vdd_cpu_big0_s0"; 272 regulator-always-on; 273 regulator-boot-on; 274 regulator-min-microvolt = <550000>; 275 regulator-max-microvolt = <1050000>; 276 regulator-ramp-delay = <2300>; 277 vin-supply = <&vcc5v0_sys>; 278 279 regulator-state-mem { 280 regulator-off-in-suspend; 281 }; 282 }; 283 284 vdd_cpu_big1_s0: regulator@43 { 285 compatible = "rockchip,rk8603", "rockchip,rk8602"; 286 reg = <0x43>; 287 fcs,suspend-voltage-selector = <1>; 288 regulator-name = "vdd_cpu_big1_s0"; 289 regulator-always-on; 290 regulator-boot-on; 291 regulator-min-microvolt = <550000>; 292 regulator-max-microvolt = <1050000>; 293 regulator-ramp-delay = <2300>; 294 vin-supply = <&vcc5v0_sys>; 295 296 regulator-state-mem { 297 regulator-off-in-suspend; 298 }; 299 }; 300}; 301 302&i2c7m0_xfer { 303 rockchip,pins = 304 /* i2c7_scl_m0 */ 305 <1 RK_PD0 9 &pcfg_pull_none_drv_level_0>, 306 /* i2c7_sda_m0 */ 307 <1 RK_PD1 9 &pcfg_pull_none_drv_level_0>; 308}; 309 310&i2c8 { 311 pinctrl-0 = <&i2c8m2_xfer>; 312}; 313 314&mdio0 { 315 rgmii_phy: ethernet-phy@6 { 316 /* KSZ9031 or KSZ9131 */ 317 compatible = "ethernet-phy-ieee802.3-c22"; 318 reg = <0x6>; 319 clocks = <&cru REFCLKO25M_ETH0_OUT>; 320 }; 321}; 322 323&pcie3x4 { 324 /* 325 * The board has a gpio-controlled "pcie_refclk" generator, 326 * so add it to the list of clocks. 327 */ 328 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, 329 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, 330 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>, 331 <&pcie_refclk>; 332 clock-names = "aclk_mst", "aclk_slv", 333 "aclk_dbi", "pclk", 334 "aux", "pipe", 335 "ref"; 336 reset-gpios = <&gpio3 RK_PB6 GPIO_ACTIVE_HIGH>; 337}; 338 339&pd_gpu { 340 domain-supply = <&vdd_gpu_s0>; 341}; 342 343&pinctrl { 344 emmc { 345 emmc_reset: emmc-reset { 346 rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 347 }; 348 }; 349 350 ethernet { 351 eth_reset: eth-reset { 352 rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 353 }; 354 }; 355 356 leds { 357 module_led_pin: module-led-pin { 358 rockchip,pins = <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 359 }; 360 }; 361 362 usb3 { 363 usb3_id: usb3-id { 364 rockchip,pins = 365 <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; 366 }; 367 }; 368}; 369 370&pwm0 { 371 pinctrl-0 = <&pwm0m1_pins>; 372 pinctrl-names = "default"; 373}; 374 375&saradc { 376 vref-supply = <&vcc_1v8_s0>; 377 status = "okay"; 378}; 379 380&sdhci { 381 bus-width = <8>; 382 cap-mmc-highspeed; 383 mmc-ddr-1_8v; 384 mmc-hs200-1_8v; 385 mmc-hs400-1_8v; 386 mmc-hs400-enhanced-strobe; 387 mmc-pwrseq = <&emmc_pwrseq>; 388 no-sdio; 389 no-sd; 390 non-removable; 391 pinctrl-names = "default"; 392 pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_data_strobe>; 393 vmmc-supply = <&vcc_3v3_s3>; 394 vqmmc-supply = <&vcc_1v8_s3>; 395 status = "okay"; 396}; 397 398&sdmmc { 399 bus-width = <4>; 400 cap-sd-highspeed; 401 max-frequency = <150000000>; 402 vqmmc-supply = <&vccio_sd_s0>; 403}; 404 405&spi0 { 406 pinctrl-0 = <&spi0m1_cs0 &spi0m1_cs1 &spi0m3_pins>; 407}; 408 409&spi2 { 410 assigned-clocks = <&cru CLK_SPI2>; 411 assigned-clock-rates = <200000000>; 412 num-cs = <1>; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>; 415 status = "okay"; 416 417 pmic@0 { 418 compatible = "rockchip,rk806"; 419 reg = <0x0>; 420 interrupt-parent = <&gpio0>; 421 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 422 gpio-controller; 423 #gpio-cells = <2>; 424 pinctrl-names = "default"; 425 pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, 426 <&rk806_dvs2_null>, <&rk806_dvs3_null>; 427 spi-max-frequency = <1000000>; 428 system-power-controller; 429 vcc1-supply = <&vcc5v0_sys>; 430 vcc2-supply = <&vcc5v0_sys>; 431 vcc3-supply = <&vcc5v0_sys>; 432 vcc4-supply = <&vcc5v0_sys>; 433 vcc5-supply = <&vcc5v0_sys>; 434 vcc6-supply = <&vcc5v0_sys>; 435 vcc7-supply = <&vcc5v0_sys>; 436 vcc8-supply = <&vcc5v0_sys>; 437 vcc9-supply = <&vcc5v0_sys>; 438 vcc10-supply = <&vcc5v0_sys>; 439 vcc11-supply = <&vcc_2v0_pldo_s3>; 440 vcc12-supply = <&vcc5v0_sys>; 441 vcc13-supply = <&vcc_1v1_nldo_s3>; 442 vcc14-supply = <&vcc_1v1_nldo_s3>; 443 vcca-supply = <&vcc5v0_sys>; 444 rockchip,reset-mode = <RK806_RESTART>; 445 446 rk806_dvs1_null: dvs1-null-pins { 447 pins = "gpio_pwrctrl1"; 448 function = "pin_fun0"; 449 }; 450 451 rk806_dvs2_null: dvs2-null-pins { 452 pins = "gpio_pwrctrl2"; 453 function = "pin_fun0"; 454 }; 455 456 rk806_dvs3_null: dvs3-null-pins { 457 pins = "gpio_pwrctrl3"; 458 function = "pin_fun0"; 459 }; 460 461 regulators { 462 vdd_gpu_s0: dcdc-reg1 { 463 regulator-boot-on; 464 regulator-min-microvolt = <550000>; 465 regulator-max-microvolt = <950000>; 466 regulator-ramp-delay = <12500>; 467 regulator-name = "vdd_gpu_s0"; 468 regulator-enable-ramp-delay = <400>; 469 470 regulator-state-mem { 471 regulator-off-in-suspend; 472 }; 473 }; 474 475 vdd_cpu_lit_s0: dcdc-reg2 { 476 regulator-name = "vdd_cpu_lit_s0"; 477 regulator-always-on; 478 regulator-boot-on; 479 regulator-min-microvolt = <550000>; 480 regulator-max-microvolt = <950000>; 481 regulator-ramp-delay = <12500>; 482 483 regulator-state-mem { 484 regulator-off-in-suspend; 485 }; 486 }; 487 488 vdd_log_s0: dcdc-reg3 { 489 regulator-name = "vdd_log_s0"; 490 regulator-always-on; 491 regulator-boot-on; 492 regulator-min-microvolt = <675000>; 493 regulator-max-microvolt = <750000>; 494 regulator-ramp-delay = <12500>; 495 496 regulator-state-mem { 497 regulator-off-in-suspend; 498 regulator-suspend-microvolt = <750000>; 499 }; 500 }; 501 502 vdd_vdenc_s0: dcdc-reg4 { 503 regulator-name = "vdd_vdenc_s0"; 504 regulator-always-on; 505 regulator-boot-on; 506 regulator-min-microvolt = <550000>; 507 regulator-max-microvolt = <950000>; 508 regulator-ramp-delay = <12500>; 509 510 regulator-state-mem { 511 regulator-off-in-suspend; 512 }; 513 }; 514 515 vdd_ddr_s0: dcdc-reg5 { 516 regulator-name = "vdd_ddr_s0"; 517 regulator-always-on; 518 regulator-boot-on; 519 regulator-min-microvolt = <675000>; 520 regulator-max-microvolt = <900000>; 521 regulator-ramp-delay = <12500>; 522 523 regulator-state-mem { 524 regulator-off-in-suspend; 525 regulator-suspend-microvolt = <850000>; 526 }; 527 }; 528 529 vdd2_ddr_s3: dcdc-reg6 { 530 regulator-name = "vdd2_ddr_s3"; 531 regulator-always-on; 532 regulator-boot-on; 533 534 regulator-state-mem { 535 regulator-on-in-suspend; 536 }; 537 }; 538 539 vcc_2v0_pldo_s3: dcdc-reg7 { 540 regulator-name = "vcc_2v0_pldo_s3"; 541 regulator-always-on; 542 regulator-boot-on; 543 regulator-min-microvolt = <2000000>; 544 regulator-max-microvolt = <2000000>; 545 regulator-ramp-delay = <12500>; 546 547 regulator-state-mem { 548 regulator-on-in-suspend; 549 regulator-suspend-microvolt = <2000000>; 550 }; 551 }; 552 553 vcc_3v3_s3: dcdc-reg8 { 554 regulator-name = "vcc_3v3_s3"; 555 regulator-always-on; 556 regulator-boot-on; 557 regulator-min-microvolt = <3300000>; 558 regulator-max-microvolt = <3300000>; 559 560 regulator-state-mem { 561 regulator-on-in-suspend; 562 regulator-suspend-microvolt = <3300000>; 563 }; 564 }; 565 566 vddq_ddr_s0: dcdc-reg9 { 567 regulator-name = "vddq_ddr_s0"; 568 regulator-always-on; 569 regulator-boot-on; 570 571 regulator-state-mem { 572 regulator-off-in-suspend; 573 }; 574 }; 575 576 vcc_1v8_s3: dcdc-reg10 { 577 regulator-name = "vcc_1v8_s3"; 578 regulator-always-on; 579 regulator-boot-on; 580 regulator-min-microvolt = <1800000>; 581 regulator-max-microvolt = <1800000>; 582 583 regulator-state-mem { 584 regulator-on-in-suspend; 585 regulator-suspend-microvolt = <1800000>; 586 }; 587 }; 588 589 vcca_1v8_s0: pldo-reg1 { 590 regulator-name = "vcca_1v8_s0"; 591 regulator-always-on; 592 regulator-boot-on; 593 regulator-min-microvolt = <1800000>; 594 regulator-max-microvolt = <1800000>; 595 596 regulator-state-mem { 597 regulator-off-in-suspend; 598 }; 599 }; 600 601 vcc_1v8_s0: pldo-reg2 { 602 regulator-name = "vcc_1v8_s0"; 603 regulator-always-on; 604 regulator-boot-on; 605 regulator-min-microvolt = <1800000>; 606 regulator-max-microvolt = <1800000>; 607 608 regulator-state-mem { 609 regulator-off-in-suspend; 610 regulator-suspend-microvolt = <1800000>; 611 }; 612 }; 613 614 vdda_1v2_s0: pldo-reg3 { 615 regulator-name = "vdda_1v2_s0"; 616 regulator-always-on; 617 regulator-boot-on; 618 regulator-min-microvolt = <1200000>; 619 regulator-max-microvolt = <1200000>; 620 621 regulator-state-mem { 622 regulator-off-in-suspend; 623 }; 624 }; 625 626 vcca_3v3_s0: pldo-reg4 { 627 regulator-name = "vcca_3v3_s0"; 628 regulator-always-on; 629 regulator-boot-on; 630 regulator-min-microvolt = <3300000>; 631 regulator-max-microvolt = <3300000>; 632 regulator-ramp-delay = <12500>; 633 634 regulator-state-mem { 635 regulator-off-in-suspend; 636 }; 637 }; 638 639 vccio_sd_s0: pldo-reg5 { 640 regulator-name = "vccio_sd_s0"; 641 regulator-always-on; 642 regulator-boot-on; 643 regulator-min-microvolt = <1800000>; 644 regulator-max-microvolt = <3300000>; 645 regulator-ramp-delay = <12500>; 646 647 regulator-state-mem { 648 regulator-off-in-suspend; 649 }; 650 }; 651 652 pldo6_s3: pldo-reg6 { 653 regulator-name = "pldo6_s3"; 654 regulator-always-on; 655 regulator-boot-on; 656 regulator-min-microvolt = <1800000>; 657 regulator-max-microvolt = <1800000>; 658 659 regulator-state-mem { 660 regulator-on-in-suspend; 661 regulator-suspend-microvolt = <1800000>; 662 }; 663 }; 664 665 vdd_0v75_s3: nldo-reg1 { 666 regulator-name = "vdd_0v75_s3"; 667 regulator-always-on; 668 regulator-boot-on; 669 regulator-min-microvolt = <750000>; 670 regulator-max-microvolt = <750000>; 671 672 regulator-state-mem { 673 regulator-on-in-suspend; 674 regulator-suspend-microvolt = <750000>; 675 }; 676 }; 677 678 vdda_ddr_pll_s0: nldo-reg2 { 679 regulator-name = "vdda_ddr_pll_s0"; 680 regulator-always-on; 681 regulator-boot-on; 682 regulator-min-microvolt = <850000>; 683 regulator-max-microvolt = <850000>; 684 685 regulator-state-mem { 686 regulator-off-in-suspend; 687 regulator-suspend-microvolt = <850000>; 688 }; 689 }; 690 691 vdda_0v75_s0: nldo-reg3 { 692 regulator-name = "vdda_0v75_s0"; 693 regulator-always-on; 694 regulator-boot-on; 695 regulator-min-microvolt = <750000>; 696 regulator-max-microvolt = <750000>; 697 698 regulator-state-mem { 699 regulator-off-in-suspend; 700 }; 701 }; 702 703 vdda_0v85_s0: nldo-reg4 { 704 regulator-name = "vdda_0v85_s0"; 705 regulator-always-on; 706 regulator-boot-on; 707 regulator-min-microvolt = <850000>; 708 regulator-max-microvolt = <850000>; 709 710 regulator-state-mem { 711 regulator-off-in-suspend; 712 }; 713 }; 714 715 vdd_0v75_s0: nldo-reg5 { 716 regulator-name = "vdd_0v75_s0"; 717 regulator-always-on; 718 regulator-boot-on; 719 regulator-min-microvolt = <750000>; 720 regulator-max-microvolt = <750000>; 721 722 regulator-state-mem { 723 regulator-off-in-suspend; 724 }; 725 }; 726 }; 727 }; 728}; 729 730&tsadc { 731 status = "okay"; 732}; 733 734/* Routed to UART0 on the Q7 connector */ 735&uart2 { 736 pinctrl-0 = <&uart2m2_xfer>; 737}; 738 739/* Mule-ATtiny UPDI */ 740&uart4 { 741 pinctrl-0 = <&uart4m2_xfer>; 742 status = "okay"; 743}; 744