1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 3#include "rk3568-fastrhino-r66s.dtsi" 4 5/ { 6 model = "Lunzn FastRhino R68S"; 7 compatible = "lunzn,fastrhino-r68s", "rockchip,rk3568"; 8 9 aliases { 10 ethernet0 = &gmac0; 11 ethernet1 = &gmac1; 12 mmc0 = &sdhci; 13 }; 14 15 adc-keys { 16 compatible = "adc-keys"; 17 io-channels = <&saradc 0>; 18 io-channel-names = "buttons"; 19 keyup-threshold-microvolt = <1800000>; 20 21 button-recovery { 22 label = "Recovery"; 23 linux,code = <KEY_VENDOR>; 24 press-threshold-microvolt = <1750>; 25 }; 26 }; 27}; 28 29&gmac0 { 30 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; 31 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; 32 assigned-clock-rates = <0>, <125000000>; 33 clock_in_out = "output"; 34 phy-handle = <&rgmii_phy0>; 35 phy-mode = "rgmii-id"; 36 pinctrl-names = "default"; 37 pinctrl-0 = <&gmac0_miim 38 &gmac0_tx_bus2 39 &gmac0_rx_bus2 40 &gmac0_rgmii_clk 41 &gmac0_rgmii_bus>; 42 snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>; 43 snps,reset-active-low; 44 /* Reset time is 15ms, 50ms for rtl8211f */ 45 snps,reset-delays-us = <0 15000 50000>; 46 tx_delay = <0x3c>; 47 rx_delay = <0x2f>; 48 status = "okay"; 49}; 50 51&gmac1 { 52 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 53 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; 54 assigned-clock-rates = <0>, <125000000>; 55 clock_in_out = "output"; 56 phy-handle = <&rgmii_phy1>; 57 phy-mode = "rgmii-id"; 58 pinctrl-names = "default"; 59 pinctrl-0 = <&gmac1m1_miim 60 &gmac1m1_tx_bus2 61 &gmac1m1_rx_bus2 62 &gmac1m1_rgmii_clk 63 &gmac1m1_rgmii_bus>; 64 snps,reset-gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_LOW>; 65 snps,reset-active-low; 66 /* Reset time is 15ms, 50ms for rtl8211f */ 67 snps,reset-delays-us = <0 15000 50000>; 68 tx_delay = <0x4f>; 69 rx_delay = <0x26>; 70 status = "okay"; 71}; 72 73&mdio0 { 74 rgmii_phy0: ethernet-phy@0 { 75 compatible = "ethernet-phy-ieee802.3-c22"; 76 reg = <0>; 77 pinctrl-0 = <ð_phy0_reset_pin>; 78 pinctrl-names = "default"; 79 }; 80}; 81 82&mdio1 { 83 rgmii_phy1: ethernet-phy@0 { 84 compatible = "ethernet-phy-ieee802.3-c22"; 85 reg = <0>; 86 pinctrl-0 = <ð_phy1_reset_pin>; 87 pinctrl-names = "default"; 88 }; 89}; 90 91&pinctrl { 92 gmac0 { 93 eth_phy0_reset_pin: eth-phy0-reset-pin { 94 rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; 95 }; 96 }; 97 98 gmac1 { 99 eth_phy1_reset_pin: eth-phy1-reset-pin { 100 rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; 101 }; 102 }; 103}; 104 105&sdhci { 106 bus-width = <8>; 107 max-frequency = <200000000>; 108 non-removable; 109 pinctrl-names = "default"; 110 pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; 111 status = "okay"; 112}; 113