1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3399-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3399-power.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "rockchip,rk3399"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 ethernet0 = &gmac; 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 }; 38 39 cpus { 40 #address-cells = <2>; 41 #size-cells = <0>; 42 43 cpu-map { 44 cluster0 { 45 core0 { 46 cpu = <&cpu_l0>; 47 }; 48 core1 { 49 cpu = <&cpu_l1>; 50 }; 51 core2 { 52 cpu = <&cpu_l2>; 53 }; 54 core3 { 55 cpu = <&cpu_l3>; 56 }; 57 }; 58 59 cluster1 { 60 core0 { 61 cpu = <&cpu_b0>; 62 }; 63 core1 { 64 cpu = <&cpu_b1>; 65 }; 66 }; 67 }; 68 69 cpu_l0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x0>; 73 enable-method = "psci"; 74 capacity-dmips-mhz = <485>; 75 clocks = <&cru ARMCLKL>; 76 #cooling-cells = <2>; /* min followed by max */ 77 dynamic-power-coefficient = <100>; 78 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 79 }; 80 81 cpu_l1: cpu@1 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x0 0x1>; 85 enable-method = "psci"; 86 capacity-dmips-mhz = <485>; 87 clocks = <&cru ARMCLKL>; 88 #cooling-cells = <2>; /* min followed by max */ 89 dynamic-power-coefficient = <100>; 90 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 91 }; 92 93 cpu_l2: cpu@2 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x0 0x2>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <485>; 99 clocks = <&cru ARMCLKL>; 100 #cooling-cells = <2>; /* min followed by max */ 101 dynamic-power-coefficient = <100>; 102 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 103 }; 104 105 cpu_l3: cpu@3 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53"; 108 reg = <0x0 0x3>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <485>; 111 clocks = <&cru ARMCLKL>; 112 #cooling-cells = <2>; /* min followed by max */ 113 dynamic-power-coefficient = <100>; 114 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 115 }; 116 117 cpu_b0: cpu@100 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a72"; 120 reg = <0x0 0x100>; 121 enable-method = "psci"; 122 capacity-dmips-mhz = <1024>; 123 clocks = <&cru ARMCLKB>; 124 #cooling-cells = <2>; /* min followed by max */ 125 dynamic-power-coefficient = <436>; 126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 127 }; 128 129 cpu_b1: cpu@101 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a72"; 132 reg = <0x0 0x101>; 133 enable-method = "psci"; 134 capacity-dmips-mhz = <1024>; 135 clocks = <&cru ARMCLKB>; 136 #cooling-cells = <2>; /* min followed by max */ 137 dynamic-power-coefficient = <436>; 138 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 139 }; 140 141 idle-states { 142 entry-method = "psci"; 143 144 CPU_SLEEP: cpu-sleep { 145 compatible = "arm,idle-state"; 146 local-timer-stop; 147 arm,psci-suspend-param = <0x0010000>; 148 entry-latency-us = <120>; 149 exit-latency-us = <250>; 150 min-residency-us = <900>; 151 }; 152 153 CLUSTER_SLEEP: cluster-sleep { 154 compatible = "arm,idle-state"; 155 local-timer-stop; 156 arm,psci-suspend-param = <0x1010000>; 157 entry-latency-us = <400>; 158 exit-latency-us = <500>; 159 min-residency-us = <2000>; 160 }; 161 }; 162 }; 163 164 display-subsystem { 165 compatible = "rockchip,display-subsystem"; 166 ports = <&vopl_out>, <&vopb_out>; 167 }; 168 169 pmu_a53 { 170 compatible = "arm,cortex-a53-pmu"; 171 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 172 }; 173 174 pmu_a72 { 175 compatible = "arm,cortex-a72-pmu"; 176 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 177 }; 178 179 psci { 180 compatible = "arm,psci-1.0"; 181 method = "smc"; 182 }; 183 184 timer { 185 compatible = "arm,armv8-timer"; 186 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 187 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 188 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 189 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 190 arm,no-tick-in-suspend; 191 }; 192 193 xin24m: xin24m { 194 compatible = "fixed-clock"; 195 clock-frequency = <24000000>; 196 clock-output-names = "xin24m"; 197 #clock-cells = <0>; 198 }; 199 200 amba: bus { 201 compatible = "simple-bus"; 202 #address-cells = <2>; 203 #size-cells = <2>; 204 ranges; 205 206 dmac_bus: dma-controller@ff6d0000 { 207 compatible = "arm,pl330", "arm,primecell"; 208 reg = <0x0 0xff6d0000 0x0 0x4000>; 209 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 210 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 211 #dma-cells = <1>; 212 arm,pl330-periph-burst; 213 clocks = <&cru ACLK_DMAC0_PERILP>; 214 clock-names = "apb_pclk"; 215 }; 216 217 dmac_peri: dma-controller@ff6e0000 { 218 compatible = "arm,pl330", "arm,primecell"; 219 reg = <0x0 0xff6e0000 0x0 0x4000>; 220 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 221 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 222 #dma-cells = <1>; 223 arm,pl330-periph-burst; 224 clocks = <&cru ACLK_DMAC1_PERILP>; 225 clock-names = "apb_pclk"; 226 }; 227 }; 228 229 pcie0: pcie@f8000000 { 230 compatible = "rockchip,rk3399-pcie"; 231 reg = <0x0 0xf8000000 0x0 0x2000000>, 232 <0x0 0xfd000000 0x0 0x1000000>; 233 reg-names = "axi-base", "apb-base"; 234 #address-cells = <3>; 235 #size-cells = <2>; 236 #interrupt-cells = <1>; 237 aspm-no-l0s; 238 bus-range = <0x0 0x1f>; 239 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 240 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 241 clock-names = "aclk", "aclk-perf", 242 "hclk", "pm"; 243 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 244 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 245 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 246 interrupt-names = "sys", "legacy", "client"; 247 interrupt-map-mask = <0 0 0 7>; 248 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 249 <0 0 0 2 &pcie0_intc 1>, 250 <0 0 0 3 &pcie0_intc 2>, 251 <0 0 0 4 &pcie0_intc 3>; 252 linux,pci-domain = <0>; 253 max-link-speed = <1>; 254 msi-map = <0x0 &its 0x0 0x1000>; 255 phys = <&pcie_phy 0>, <&pcie_phy 1>, 256 <&pcie_phy 2>, <&pcie_phy 3>; 257 phy-names = "pcie-phy-0", "pcie-phy-1", 258 "pcie-phy-2", "pcie-phy-3"; 259 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000 260 0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 261 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 262 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 263 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 264 <&cru SRST_A_PCIE>; 265 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 266 "pm", "pclk", "aclk"; 267 status = "disabled"; 268 269 pcie0_intc: interrupt-controller { 270 interrupt-controller; 271 #address-cells = <0>; 272 #interrupt-cells = <1>; 273 }; 274 }; 275 276 gmac: ethernet@fe300000 { 277 compatible = "rockchip,rk3399-gmac"; 278 reg = <0x0 0xfe300000 0x0 0x10000>; 279 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 280 interrupt-names = "macirq"; 281 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 282 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 283 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 284 <&cru PCLK_GMAC>; 285 clock-names = "stmmaceth", "mac_clk_rx", 286 "mac_clk_tx", "clk_mac_ref", 287 "clk_mac_refout", "aclk_mac", 288 "pclk_mac"; 289 power-domains = <&power RK3399_PD_GMAC>; 290 resets = <&cru SRST_A_GMAC>; 291 reset-names = "stmmaceth"; 292 rockchip,grf = <&grf>; 293 snps,txpbl = <0x4>; 294 status = "disabled"; 295 }; 296 297 sdio0: mmc@fe310000 { 298 compatible = "rockchip,rk3399-dw-mshc", 299 "rockchip,rk3288-dw-mshc"; 300 reg = <0x0 0xfe310000 0x0 0x4000>; 301 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 302 max-frequency = <150000000>; 303 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 304 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 305 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 306 fifo-depth = <0x100>; 307 power-domains = <&power RK3399_PD_SDIOAUDIO>; 308 resets = <&cru SRST_SDIO0>; 309 reset-names = "reset"; 310 status = "disabled"; 311 }; 312 313 sdmmc: mmc@fe320000 { 314 compatible = "rockchip,rk3399-dw-mshc", 315 "rockchip,rk3288-dw-mshc"; 316 reg = <0x0 0xfe320000 0x0 0x4000>; 317 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 318 max-frequency = <150000000>; 319 assigned-clocks = <&cru HCLK_SD>; 320 assigned-clock-rates = <200000000>; 321 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 322 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 323 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 324 fifo-depth = <0x100>; 325 power-domains = <&power RK3399_PD_SD>; 326 resets = <&cru SRST_SDMMC>; 327 reset-names = "reset"; 328 status = "disabled"; 329 }; 330 331 sdhci: sdhci@fe330000 { 332 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 333 reg = <0x0 0xfe330000 0x0 0x10000>; 334 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 335 arasan,soc-ctl-syscon = <&grf>; 336 assigned-clocks = <&cru SCLK_EMMC>; 337 assigned-clock-rates = <200000000>; 338 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 339 clock-names = "clk_xin", "clk_ahb"; 340 clock-output-names = "emmc_cardclock"; 341 #clock-cells = <0>; 342 phys = <&emmc_phy>; 343 phy-names = "phy_arasan"; 344 power-domains = <&power RK3399_PD_EMMC>; 345 disable-cqe-dcmd; 346 status = "disabled"; 347 }; 348 349 usb_host0_ehci: usb@fe380000 { 350 compatible = "generic-ehci"; 351 reg = <0x0 0xfe380000 0x0 0x20000>; 352 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 353 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 354 <&u2phy0>; 355 phys = <&u2phy0_host>; 356 phy-names = "usb"; 357 status = "disabled"; 358 }; 359 360 usb_host0_ohci: usb@fe3a0000 { 361 compatible = "generic-ohci"; 362 reg = <0x0 0xfe3a0000 0x0 0x20000>; 363 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 364 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 365 <&u2phy0>; 366 phys = <&u2phy0_host>; 367 phy-names = "usb"; 368 status = "disabled"; 369 }; 370 371 usb_host1_ehci: usb@fe3c0000 { 372 compatible = "generic-ehci"; 373 reg = <0x0 0xfe3c0000 0x0 0x20000>; 374 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 375 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 376 <&u2phy1>; 377 phys = <&u2phy1_host>; 378 phy-names = "usb"; 379 status = "disabled"; 380 }; 381 382 usb_host1_ohci: usb@fe3e0000 { 383 compatible = "generic-ohci"; 384 reg = <0x0 0xfe3e0000 0x0 0x20000>; 385 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 386 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 387 <&u2phy1>; 388 phys = <&u2phy1_host>; 389 phy-names = "usb"; 390 status = "disabled"; 391 }; 392 393 usbdrd3_0: usb@fe800000 { 394 compatible = "rockchip,rk3399-dwc3"; 395 #address-cells = <2>; 396 #size-cells = <2>; 397 ranges; 398 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 399 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 400 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 401 clock-names = "ref_clk", "suspend_clk", 402 "bus_clk", "aclk_usb3_rksoc_axi_perf", 403 "aclk_usb3", "grf_clk"; 404 resets = <&cru SRST_A_USB3_OTG0>; 405 reset-names = "usb3-otg"; 406 status = "disabled"; 407 408 usbdrd_dwc3_0: usb@fe800000 { 409 compatible = "snps,dwc3"; 410 reg = <0x0 0xfe800000 0x0 0x100000>; 411 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 412 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, 413 <&cru SCLK_USB3OTG0_SUSPEND>; 414 clock-names = "ref", "bus_early", "suspend"; 415 dr_mode = "otg"; 416 phys = <&u2phy0_otg>, <&tcphy0_usb3>; 417 phy-names = "usb2-phy", "usb3-phy"; 418 phy_type = "utmi_wide"; 419 snps,dis_enblslpm_quirk; 420 snps,dis-u2-freeclk-exists-quirk; 421 snps,dis_u2_susphy_quirk; 422 snps,dis-del-phy-power-chg-quirk; 423 snps,dis-tx-ipgap-linecheck-quirk; 424 power-domains = <&power RK3399_PD_USB3>; 425 status = "disabled"; 426 }; 427 }; 428 429 usbdrd3_1: usb@fe900000 { 430 compatible = "rockchip,rk3399-dwc3"; 431 #address-cells = <2>; 432 #size-cells = <2>; 433 ranges; 434 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 435 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 436 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 437 clock-names = "ref_clk", "suspend_clk", 438 "bus_clk", "aclk_usb3_rksoc_axi_perf", 439 "aclk_usb3", "grf_clk"; 440 resets = <&cru SRST_A_USB3_OTG1>; 441 reset-names = "usb3-otg"; 442 status = "disabled"; 443 444 usbdrd_dwc3_1: usb@fe900000 { 445 compatible = "snps,dwc3"; 446 reg = <0x0 0xfe900000 0x0 0x100000>; 447 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 448 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, 449 <&cru SCLK_USB3OTG1_SUSPEND>; 450 clock-names = "ref", "bus_early", "suspend"; 451 dr_mode = "otg"; 452 phys = <&u2phy1_otg>, <&tcphy1_usb3>; 453 phy-names = "usb2-phy", "usb3-phy"; 454 phy_type = "utmi_wide"; 455 snps,dis_enblslpm_quirk; 456 snps,dis-u2-freeclk-exists-quirk; 457 snps,dis_u2_susphy_quirk; 458 snps,dis-del-phy-power-chg-quirk; 459 snps,dis-tx-ipgap-linecheck-quirk; 460 power-domains = <&power RK3399_PD_USB3>; 461 status = "disabled"; 462 }; 463 }; 464 465 cdn_dp: dp@fec00000 { 466 compatible = "rockchip,rk3399-cdn-dp"; 467 reg = <0x0 0xfec00000 0x0 0x100000>; 468 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 469 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; 470 assigned-clock-rates = <100000000>, <200000000>; 471 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 472 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; 473 clock-names = "core-clk", "pclk", "spdif", "grf"; 474 phys = <&tcphy0_dp>, <&tcphy1_dp>; 475 power-domains = <&power RK3399_PD_HDCP>; 476 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, 477 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; 478 reset-names = "spdif", "dptx", "apb", "core"; 479 rockchip,grf = <&grf>; 480 #sound-dai-cells = <1>; 481 status = "disabled"; 482 483 ports { 484 dp_in: port { 485 #address-cells = <1>; 486 #size-cells = <0>; 487 488 dp_in_vopb: endpoint@0 { 489 reg = <0>; 490 remote-endpoint = <&vopb_out_dp>; 491 }; 492 493 dp_in_vopl: endpoint@1 { 494 reg = <1>; 495 remote-endpoint = <&vopl_out_dp>; 496 }; 497 }; 498 }; 499 }; 500 501 gic: interrupt-controller@fee00000 { 502 compatible = "arm,gic-v3"; 503 #interrupt-cells = <4>; 504 #address-cells = <2>; 505 #size-cells = <2>; 506 ranges; 507 interrupt-controller; 508 509 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 510 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 511 <0x0 0xfff00000 0 0x10000>, /* GICC */ 512 <0x0 0xfff10000 0 0x10000>, /* GICH */ 513 <0x0 0xfff20000 0 0x10000>; /* GICV */ 514 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 515 its: interrupt-controller@fee20000 { 516 compatible = "arm,gic-v3-its"; 517 msi-controller; 518 #msi-cells = <1>; 519 reg = <0x0 0xfee20000 0x0 0x20000>; 520 }; 521 522 ppi-partitions { 523 ppi_cluster0: interrupt-partition-0 { 524 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 525 }; 526 527 ppi_cluster1: interrupt-partition-1 { 528 affinity = <&cpu_b0 &cpu_b1>; 529 }; 530 }; 531 }; 532 533 saradc: saradc@ff100000 { 534 compatible = "rockchip,rk3399-saradc"; 535 reg = <0x0 0xff100000 0x0 0x100>; 536 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 537 #io-channel-cells = <1>; 538 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 539 clock-names = "saradc", "apb_pclk"; 540 resets = <&cru SRST_P_SARADC>; 541 reset-names = "saradc-apb"; 542 status = "disabled"; 543 }; 544 545 i2c1: i2c@ff110000 { 546 compatible = "rockchip,rk3399-i2c"; 547 reg = <0x0 0xff110000 0x0 0x1000>; 548 assigned-clocks = <&cru SCLK_I2C1>; 549 assigned-clock-rates = <200000000>; 550 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 551 clock-names = "i2c", "pclk"; 552 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 553 pinctrl-names = "default"; 554 pinctrl-0 = <&i2c1_xfer>; 555 #address-cells = <1>; 556 #size-cells = <0>; 557 status = "disabled"; 558 }; 559 560 i2c2: i2c@ff120000 { 561 compatible = "rockchip,rk3399-i2c"; 562 reg = <0x0 0xff120000 0x0 0x1000>; 563 assigned-clocks = <&cru SCLK_I2C2>; 564 assigned-clock-rates = <200000000>; 565 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 566 clock-names = "i2c", "pclk"; 567 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 568 pinctrl-names = "default"; 569 pinctrl-0 = <&i2c2_xfer>; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 status = "disabled"; 573 }; 574 575 i2c3: i2c@ff130000 { 576 compatible = "rockchip,rk3399-i2c"; 577 reg = <0x0 0xff130000 0x0 0x1000>; 578 assigned-clocks = <&cru SCLK_I2C3>; 579 assigned-clock-rates = <200000000>; 580 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 581 clock-names = "i2c", "pclk"; 582 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 583 pinctrl-names = "default"; 584 pinctrl-0 = <&i2c3_xfer>; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 status = "disabled"; 588 }; 589 590 i2c5: i2c@ff140000 { 591 compatible = "rockchip,rk3399-i2c"; 592 reg = <0x0 0xff140000 0x0 0x1000>; 593 assigned-clocks = <&cru SCLK_I2C5>; 594 assigned-clock-rates = <200000000>; 595 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 596 clock-names = "i2c", "pclk"; 597 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 598 pinctrl-names = "default"; 599 pinctrl-0 = <&i2c5_xfer>; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 status = "disabled"; 603 }; 604 605 i2c6: i2c@ff150000 { 606 compatible = "rockchip,rk3399-i2c"; 607 reg = <0x0 0xff150000 0x0 0x1000>; 608 assigned-clocks = <&cru SCLK_I2C6>; 609 assigned-clock-rates = <200000000>; 610 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 611 clock-names = "i2c", "pclk"; 612 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 613 pinctrl-names = "default"; 614 pinctrl-0 = <&i2c6_xfer>; 615 #address-cells = <1>; 616 #size-cells = <0>; 617 status = "disabled"; 618 }; 619 620 i2c7: i2c@ff160000 { 621 compatible = "rockchip,rk3399-i2c"; 622 reg = <0x0 0xff160000 0x0 0x1000>; 623 assigned-clocks = <&cru SCLK_I2C7>; 624 assigned-clock-rates = <200000000>; 625 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 626 clock-names = "i2c", "pclk"; 627 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 628 pinctrl-names = "default"; 629 pinctrl-0 = <&i2c7_xfer>; 630 #address-cells = <1>; 631 #size-cells = <0>; 632 status = "disabled"; 633 }; 634 635 uart0: serial@ff180000 { 636 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 637 reg = <0x0 0xff180000 0x0 0x100>; 638 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 639 clock-names = "baudclk", "apb_pclk"; 640 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 641 reg-shift = <2>; 642 reg-io-width = <4>; 643 pinctrl-names = "default"; 644 pinctrl-0 = <&uart0_xfer>; 645 status = "disabled"; 646 }; 647 648 uart1: serial@ff190000 { 649 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 650 reg = <0x0 0xff190000 0x0 0x100>; 651 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 652 clock-names = "baudclk", "apb_pclk"; 653 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 654 reg-shift = <2>; 655 reg-io-width = <4>; 656 pinctrl-names = "default"; 657 pinctrl-0 = <&uart1_xfer>; 658 status = "disabled"; 659 }; 660 661 uart2: serial@ff1a0000 { 662 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 663 reg = <0x0 0xff1a0000 0x0 0x100>; 664 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 665 clock-names = "baudclk", "apb_pclk"; 666 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 667 reg-shift = <2>; 668 reg-io-width = <4>; 669 pinctrl-names = "default"; 670 pinctrl-0 = <&uart2c_xfer>; 671 status = "disabled"; 672 }; 673 674 uart3: serial@ff1b0000 { 675 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 676 reg = <0x0 0xff1b0000 0x0 0x100>; 677 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 678 clock-names = "baudclk", "apb_pclk"; 679 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 680 reg-shift = <2>; 681 reg-io-width = <4>; 682 pinctrl-names = "default"; 683 pinctrl-0 = <&uart3_xfer>; 684 status = "disabled"; 685 }; 686 687 spi0: spi@ff1c0000 { 688 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 689 reg = <0x0 0xff1c0000 0x0 0x1000>; 690 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 691 clock-names = "spiclk", "apb_pclk"; 692 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 693 dmas = <&dmac_peri 10>, <&dmac_peri 11>; 694 dma-names = "tx", "rx"; 695 pinctrl-names = "default"; 696 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 697 #address-cells = <1>; 698 #size-cells = <0>; 699 status = "disabled"; 700 }; 701 702 spi1: spi@ff1d0000 { 703 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 704 reg = <0x0 0xff1d0000 0x0 0x1000>; 705 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 706 clock-names = "spiclk", "apb_pclk"; 707 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 708 dmas = <&dmac_peri 12>, <&dmac_peri 13>; 709 dma-names = "tx", "rx"; 710 pinctrl-names = "default"; 711 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 status = "disabled"; 715 }; 716 717 spi2: spi@ff1e0000 { 718 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 719 reg = <0x0 0xff1e0000 0x0 0x1000>; 720 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 721 clock-names = "spiclk", "apb_pclk"; 722 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 723 dmas = <&dmac_peri 14>, <&dmac_peri 15>; 724 dma-names = "tx", "rx"; 725 pinctrl-names = "default"; 726 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 727 #address-cells = <1>; 728 #size-cells = <0>; 729 status = "disabled"; 730 }; 731 732 spi4: spi@ff1f0000 { 733 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 734 reg = <0x0 0xff1f0000 0x0 0x1000>; 735 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 736 clock-names = "spiclk", "apb_pclk"; 737 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 738 dmas = <&dmac_peri 18>, <&dmac_peri 19>; 739 dma-names = "tx", "rx"; 740 pinctrl-names = "default"; 741 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 status = "disabled"; 745 }; 746 747 spi5: spi@ff200000 { 748 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 749 reg = <0x0 0xff200000 0x0 0x1000>; 750 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 751 clock-names = "spiclk", "apb_pclk"; 752 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 753 dmas = <&dmac_bus 8>, <&dmac_bus 9>; 754 dma-names = "tx", "rx"; 755 pinctrl-names = "default"; 756 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 757 power-domains = <&power RK3399_PD_SDIOAUDIO>; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 status = "disabled"; 761 }; 762 763 thermal_zones: thermal-zones { 764 cpu_thermal: cpu { 765 polling-delay-passive = <100>; 766 polling-delay = <1000>; 767 768 thermal-sensors = <&tsadc 0>; 769 770 trips { 771 cpu_alert0: cpu_alert0 { 772 temperature = <70000>; 773 hysteresis = <2000>; 774 type = "passive"; 775 }; 776 cpu_alert1: cpu_alert1 { 777 temperature = <75000>; 778 hysteresis = <2000>; 779 type = "passive"; 780 }; 781 cpu_crit: cpu_crit { 782 temperature = <95000>; 783 hysteresis = <2000>; 784 type = "critical"; 785 }; 786 }; 787 788 cooling-maps { 789 map0 { 790 trip = <&cpu_alert0>; 791 cooling-device = 792 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 793 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 794 }; 795 map1 { 796 trip = <&cpu_alert1>; 797 cooling-device = 798 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 799 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 800 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 801 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 802 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 803 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 804 }; 805 }; 806 }; 807 808 gpu_thermal: gpu { 809 polling-delay-passive = <100>; 810 polling-delay = <1000>; 811 812 thermal-sensors = <&tsadc 1>; 813 814 trips { 815 gpu_alert0: gpu_alert0 { 816 temperature = <75000>; 817 hysteresis = <2000>; 818 type = "passive"; 819 }; 820 gpu_crit: gpu_crit { 821 temperature = <95000>; 822 hysteresis = <2000>; 823 type = "critical"; 824 }; 825 }; 826 827 cooling-maps { 828 map0 { 829 trip = <&gpu_alert0>; 830 cooling-device = 831 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 832 }; 833 }; 834 }; 835 }; 836 837 tsadc: tsadc@ff260000 { 838 compatible = "rockchip,rk3399-tsadc"; 839 reg = <0x0 0xff260000 0x0 0x100>; 840 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 841 assigned-clocks = <&cru SCLK_TSADC>; 842 assigned-clock-rates = <750000>; 843 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 844 clock-names = "tsadc", "apb_pclk"; 845 resets = <&cru SRST_TSADC>; 846 reset-names = "tsadc-apb"; 847 rockchip,grf = <&grf>; 848 rockchip,hw-tshut-temp = <95000>; 849 pinctrl-names = "init", "default", "sleep"; 850 pinctrl-0 = <&otp_pin>; 851 pinctrl-1 = <&otp_out>; 852 pinctrl-2 = <&otp_pin>; 853 #thermal-sensor-cells = <1>; 854 status = "disabled"; 855 }; 856 857 qos_emmc: qos@ffa58000 { 858 compatible = "syscon"; 859 reg = <0x0 0xffa58000 0x0 0x20>; 860 }; 861 862 qos_gmac: qos@ffa5c000 { 863 compatible = "syscon"; 864 reg = <0x0 0xffa5c000 0x0 0x20>; 865 }; 866 867 qos_pcie: qos@ffa60080 { 868 compatible = "syscon"; 869 reg = <0x0 0xffa60080 0x0 0x20>; 870 }; 871 872 qos_usb_host0: qos@ffa60100 { 873 compatible = "syscon"; 874 reg = <0x0 0xffa60100 0x0 0x20>; 875 }; 876 877 qos_usb_host1: qos@ffa60180 { 878 compatible = "syscon"; 879 reg = <0x0 0xffa60180 0x0 0x20>; 880 }; 881 882 qos_usb_otg0: qos@ffa70000 { 883 compatible = "syscon"; 884 reg = <0x0 0xffa70000 0x0 0x20>; 885 }; 886 887 qos_usb_otg1: qos@ffa70080 { 888 compatible = "syscon"; 889 reg = <0x0 0xffa70080 0x0 0x20>; 890 }; 891 892 qos_sd: qos@ffa74000 { 893 compatible = "syscon"; 894 reg = <0x0 0xffa74000 0x0 0x20>; 895 }; 896 897 qos_sdioaudio: qos@ffa76000 { 898 compatible = "syscon"; 899 reg = <0x0 0xffa76000 0x0 0x20>; 900 }; 901 902 qos_hdcp: qos@ffa90000 { 903 compatible = "syscon"; 904 reg = <0x0 0xffa90000 0x0 0x20>; 905 }; 906 907 qos_iep: qos@ffa98000 { 908 compatible = "syscon"; 909 reg = <0x0 0xffa98000 0x0 0x20>; 910 }; 911 912 qos_isp0_m0: qos@ffaa0000 { 913 compatible = "syscon"; 914 reg = <0x0 0xffaa0000 0x0 0x20>; 915 }; 916 917 qos_isp0_m1: qos@ffaa0080 { 918 compatible = "syscon"; 919 reg = <0x0 0xffaa0080 0x0 0x20>; 920 }; 921 922 qos_isp1_m0: qos@ffaa8000 { 923 compatible = "syscon"; 924 reg = <0x0 0xffaa8000 0x0 0x20>; 925 }; 926 927 qos_isp1_m1: qos@ffaa8080 { 928 compatible = "syscon"; 929 reg = <0x0 0xffaa8080 0x0 0x20>; 930 }; 931 932 qos_rga_r: qos@ffab0000 { 933 compatible = "syscon"; 934 reg = <0x0 0xffab0000 0x0 0x20>; 935 }; 936 937 qos_rga_w: qos@ffab0080 { 938 compatible = "syscon"; 939 reg = <0x0 0xffab0080 0x0 0x20>; 940 }; 941 942 qos_video_m0: qos@ffab8000 { 943 compatible = "syscon"; 944 reg = <0x0 0xffab8000 0x0 0x20>; 945 }; 946 947 qos_video_m1_r: qos@ffac0000 { 948 compatible = "syscon"; 949 reg = <0x0 0xffac0000 0x0 0x20>; 950 }; 951 952 qos_video_m1_w: qos@ffac0080 { 953 compatible = "syscon"; 954 reg = <0x0 0xffac0080 0x0 0x20>; 955 }; 956 957 qos_vop_big_r: qos@ffac8000 { 958 compatible = "syscon"; 959 reg = <0x0 0xffac8000 0x0 0x20>; 960 }; 961 962 qos_vop_big_w: qos@ffac8080 { 963 compatible = "syscon"; 964 reg = <0x0 0xffac8080 0x0 0x20>; 965 }; 966 967 qos_vop_little: qos@ffad0000 { 968 compatible = "syscon"; 969 reg = <0x0 0xffad0000 0x0 0x20>; 970 }; 971 972 qos_perihp: qos@ffad8080 { 973 compatible = "syscon"; 974 reg = <0x0 0xffad8080 0x0 0x20>; 975 }; 976 977 qos_gpu: qos@ffae0000 { 978 compatible = "syscon"; 979 reg = <0x0 0xffae0000 0x0 0x20>; 980 }; 981 982 pmu: power-management@ff310000 { 983 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 984 reg = <0x0 0xff310000 0x0 0x1000>; 985 986 /* 987 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 988 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 989 * Some of the power domains are grouped together for every 990 * voltage domain. 991 * The detail contents as below. 992 */ 993 power: power-controller { 994 compatible = "rockchip,rk3399-power-controller"; 995 #power-domain-cells = <1>; 996 #address-cells = <1>; 997 #size-cells = <0>; 998 999 /* These power domains are grouped by VD_CENTER */ 1000 pd_iep@RK3399_PD_IEP { 1001 reg = <RK3399_PD_IEP>; 1002 clocks = <&cru ACLK_IEP>, 1003 <&cru HCLK_IEP>; 1004 pm_qos = <&qos_iep>; 1005 }; 1006 pd_rga@RK3399_PD_RGA { 1007 reg = <RK3399_PD_RGA>; 1008 clocks = <&cru ACLK_RGA>, 1009 <&cru HCLK_RGA>; 1010 pm_qos = <&qos_rga_r>, 1011 <&qos_rga_w>; 1012 }; 1013 pd_vcodec@RK3399_PD_VCODEC { 1014 reg = <RK3399_PD_VCODEC>; 1015 clocks = <&cru ACLK_VCODEC>, 1016 <&cru HCLK_VCODEC>; 1017 pm_qos = <&qos_video_m0>; 1018 }; 1019 pd_vdu@RK3399_PD_VDU { 1020 reg = <RK3399_PD_VDU>; 1021 clocks = <&cru ACLK_VDU>, 1022 <&cru HCLK_VDU>; 1023 pm_qos = <&qos_video_m1_r>, 1024 <&qos_video_m1_w>; 1025 }; 1026 1027 /* These power domains are grouped by VD_GPU */ 1028 pd_gpu@RK3399_PD_GPU { 1029 reg = <RK3399_PD_GPU>; 1030 clocks = <&cru ACLK_GPU>; 1031 pm_qos = <&qos_gpu>; 1032 }; 1033 1034 /* These power domains are grouped by VD_LOGIC */ 1035 pd_edp@RK3399_PD_EDP { 1036 reg = <RK3399_PD_EDP>; 1037 clocks = <&cru PCLK_EDP_CTRL>; 1038 }; 1039 pd_emmc@RK3399_PD_EMMC { 1040 reg = <RK3399_PD_EMMC>; 1041 clocks = <&cru ACLK_EMMC>; 1042 pm_qos = <&qos_emmc>; 1043 }; 1044 pd_gmac@RK3399_PD_GMAC { 1045 reg = <RK3399_PD_GMAC>; 1046 clocks = <&cru ACLK_GMAC>, 1047 <&cru PCLK_GMAC>; 1048 pm_qos = <&qos_gmac>; 1049 }; 1050 pd_sd@RK3399_PD_SD { 1051 reg = <RK3399_PD_SD>; 1052 clocks = <&cru HCLK_SDMMC>, 1053 <&cru SCLK_SDMMC>; 1054 pm_qos = <&qos_sd>; 1055 }; 1056 pd_sdioaudio@RK3399_PD_SDIOAUDIO { 1057 reg = <RK3399_PD_SDIOAUDIO>; 1058 clocks = <&cru HCLK_SDIO>; 1059 pm_qos = <&qos_sdioaudio>; 1060 }; 1061 pd_tcpc0@RK3399_PD_TCPD0 { 1062 reg = <RK3399_PD_TCPD0>; 1063 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1064 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1065 }; 1066 pd_tcpc1@RK3399_PD_TCPD1 { 1067 reg = <RK3399_PD_TCPD1>; 1068 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1069 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1070 }; 1071 pd_usb3@RK3399_PD_USB3 { 1072 reg = <RK3399_PD_USB3>; 1073 clocks = <&cru ACLK_USB3>; 1074 pm_qos = <&qos_usb_otg0>, 1075 <&qos_usb_otg1>; 1076 }; 1077 pd_vio@RK3399_PD_VIO { 1078 reg = <RK3399_PD_VIO>; 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 1082 pd_hdcp@RK3399_PD_HDCP { 1083 reg = <RK3399_PD_HDCP>; 1084 clocks = <&cru ACLK_HDCP>, 1085 <&cru HCLK_HDCP>, 1086 <&cru PCLK_HDCP>; 1087 pm_qos = <&qos_hdcp>; 1088 }; 1089 pd_isp0@RK3399_PD_ISP0 { 1090 reg = <RK3399_PD_ISP0>; 1091 clocks = <&cru ACLK_ISP0>, 1092 <&cru HCLK_ISP0>; 1093 pm_qos = <&qos_isp0_m0>, 1094 <&qos_isp0_m1>; 1095 }; 1096 pd_isp1@RK3399_PD_ISP1 { 1097 reg = <RK3399_PD_ISP1>; 1098 clocks = <&cru ACLK_ISP1>, 1099 <&cru HCLK_ISP1>; 1100 pm_qos = <&qos_isp1_m0>, 1101 <&qos_isp1_m1>; 1102 }; 1103 pd_vo@RK3399_PD_VO { 1104 reg = <RK3399_PD_VO>; 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 1108 pd_vopb@RK3399_PD_VOPB { 1109 reg = <RK3399_PD_VOPB>; 1110 clocks = <&cru ACLK_VOP0>, 1111 <&cru HCLK_VOP0>; 1112 pm_qos = <&qos_vop_big_r>, 1113 <&qos_vop_big_w>; 1114 }; 1115 pd_vopl@RK3399_PD_VOPL { 1116 reg = <RK3399_PD_VOPL>; 1117 clocks = <&cru ACLK_VOP1>, 1118 <&cru HCLK_VOP1>; 1119 pm_qos = <&qos_vop_little>; 1120 }; 1121 }; 1122 }; 1123 }; 1124 }; 1125 1126 pmugrf: syscon@ff320000 { 1127 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1128 reg = <0x0 0xff320000 0x0 0x1000>; 1129 1130 pmu_io_domains: io-domains { 1131 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1132 status = "disabled"; 1133 }; 1134 }; 1135 1136 spi3: spi@ff350000 { 1137 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1138 reg = <0x0 0xff350000 0x0 0x1000>; 1139 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1140 clock-names = "spiclk", "apb_pclk"; 1141 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1142 pinctrl-names = "default"; 1143 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 status = "disabled"; 1147 }; 1148 1149 uart4: serial@ff370000 { 1150 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1151 reg = <0x0 0xff370000 0x0 0x100>; 1152 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1153 clock-names = "baudclk", "apb_pclk"; 1154 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1155 reg-shift = <2>; 1156 reg-io-width = <4>; 1157 pinctrl-names = "default"; 1158 pinctrl-0 = <&uart4_xfer>; 1159 status = "disabled"; 1160 }; 1161 1162 i2c0: i2c@ff3c0000 { 1163 compatible = "rockchip,rk3399-i2c"; 1164 reg = <0x0 0xff3c0000 0x0 0x1000>; 1165 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1166 assigned-clock-rates = <200000000>; 1167 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1168 clock-names = "i2c", "pclk"; 1169 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1170 pinctrl-names = "default"; 1171 pinctrl-0 = <&i2c0_xfer>; 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 status = "disabled"; 1175 }; 1176 1177 i2c4: i2c@ff3d0000 { 1178 compatible = "rockchip,rk3399-i2c"; 1179 reg = <0x0 0xff3d0000 0x0 0x1000>; 1180 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1181 assigned-clock-rates = <200000000>; 1182 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1183 clock-names = "i2c", "pclk"; 1184 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1185 pinctrl-names = "default"; 1186 pinctrl-0 = <&i2c4_xfer>; 1187 #address-cells = <1>; 1188 #size-cells = <0>; 1189 status = "disabled"; 1190 }; 1191 1192 i2c8: i2c@ff3e0000 { 1193 compatible = "rockchip,rk3399-i2c"; 1194 reg = <0x0 0xff3e0000 0x0 0x1000>; 1195 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1196 assigned-clock-rates = <200000000>; 1197 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1198 clock-names = "i2c", "pclk"; 1199 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1200 pinctrl-names = "default"; 1201 pinctrl-0 = <&i2c8_xfer>; 1202 #address-cells = <1>; 1203 #size-cells = <0>; 1204 status = "disabled"; 1205 }; 1206 1207 pwm0: pwm@ff420000 { 1208 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1209 reg = <0x0 0xff420000 0x0 0x10>; 1210 #pwm-cells = <3>; 1211 pinctrl-names = "default"; 1212 pinctrl-0 = <&pwm0_pin>; 1213 clocks = <&pmucru PCLK_RKPWM_PMU>; 1214 clock-names = "pwm"; 1215 status = "disabled"; 1216 }; 1217 1218 pwm1: pwm@ff420010 { 1219 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1220 reg = <0x0 0xff420010 0x0 0x10>; 1221 #pwm-cells = <3>; 1222 pinctrl-names = "default"; 1223 pinctrl-0 = <&pwm1_pin>; 1224 clocks = <&pmucru PCLK_RKPWM_PMU>; 1225 clock-names = "pwm"; 1226 status = "disabled"; 1227 }; 1228 1229 pwm2: pwm@ff420020 { 1230 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1231 reg = <0x0 0xff420020 0x0 0x10>; 1232 #pwm-cells = <3>; 1233 pinctrl-names = "default"; 1234 pinctrl-0 = <&pwm2_pin>; 1235 clocks = <&pmucru PCLK_RKPWM_PMU>; 1236 clock-names = "pwm"; 1237 status = "disabled"; 1238 }; 1239 1240 pwm3: pwm@ff420030 { 1241 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1242 reg = <0x0 0xff420030 0x0 0x10>; 1243 #pwm-cells = <3>; 1244 pinctrl-names = "default"; 1245 pinctrl-0 = <&pwm3a_pin>; 1246 clocks = <&pmucru PCLK_RKPWM_PMU>; 1247 clock-names = "pwm"; 1248 status = "disabled"; 1249 }; 1250 1251 vpu: video-codec@ff650000 { 1252 compatible = "rockchip,rk3399-vpu"; 1253 reg = <0x0 0xff650000 0x0 0x800>; 1254 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 1255 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1256 interrupt-names = "vepu", "vdpu"; 1257 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1258 clock-names = "aclk", "hclk"; 1259 iommus = <&vpu_mmu>; 1260 power-domains = <&power RK3399_PD_VCODEC>; 1261 }; 1262 1263 vpu_mmu: iommu@ff650800 { 1264 compatible = "rockchip,iommu"; 1265 reg = <0x0 0xff650800 0x0 0x40>; 1266 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1267 interrupt-names = "vpu_mmu"; 1268 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1269 clock-names = "aclk", "iface"; 1270 #iommu-cells = <0>; 1271 power-domains = <&power RK3399_PD_VCODEC>; 1272 }; 1273 1274 vdec: video-codec@ff660000 { 1275 compatible = "rockchip,rk3399-vdec"; 1276 reg = <0x0 0xff660000 0x0 0x400>; 1277 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1278 interrupt-names = "vdpu"; 1279 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, 1280 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; 1281 clock-names = "axi", "ahb", "cabac", "core"; 1282 iommus = <&vdec_mmu>; 1283 power-domains = <&power RK3399_PD_VDU>; 1284 }; 1285 1286 vdec_mmu: iommu@ff660480 { 1287 compatible = "rockchip,iommu"; 1288 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; 1289 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1290 interrupt-names = "vdec_mmu"; 1291 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; 1292 clock-names = "aclk", "iface"; 1293 power-domains = <&power RK3399_PD_VDU>; 1294 #iommu-cells = <0>; 1295 }; 1296 1297 iep_mmu: iommu@ff670800 { 1298 compatible = "rockchip,iommu"; 1299 reg = <0x0 0xff670800 0x0 0x40>; 1300 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; 1301 interrupt-names = "iep_mmu"; 1302 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1303 clock-names = "aclk", "iface"; 1304 #iommu-cells = <0>; 1305 status = "disabled"; 1306 }; 1307 1308 rga: rga@ff680000 { 1309 compatible = "rockchip,rk3399-rga"; 1310 reg = <0x0 0xff680000 0x0 0x10000>; 1311 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 1312 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 1313 clock-names = "aclk", "hclk", "sclk"; 1314 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 1315 reset-names = "core", "axi", "ahb"; 1316 power-domains = <&power RK3399_PD_RGA>; 1317 }; 1318 1319 efuse0: efuse@ff690000 { 1320 compatible = "rockchip,rk3399-efuse"; 1321 reg = <0x0 0xff690000 0x0 0x80>; 1322 #address-cells = <1>; 1323 #size-cells = <1>; 1324 clocks = <&cru PCLK_EFUSE1024NS>; 1325 clock-names = "pclk_efuse"; 1326 1327 /* Data cells */ 1328 cpu_id: cpu-id@7 { 1329 reg = <0x07 0x10>; 1330 }; 1331 cpub_leakage: cpu-leakage@17 { 1332 reg = <0x17 0x1>; 1333 }; 1334 gpu_leakage: gpu-leakage@18 { 1335 reg = <0x18 0x1>; 1336 }; 1337 center_leakage: center-leakage@19 { 1338 reg = <0x19 0x1>; 1339 }; 1340 cpul_leakage: cpu-leakage@1a { 1341 reg = <0x1a 0x1>; 1342 }; 1343 logic_leakage: logic-leakage@1b { 1344 reg = <0x1b 0x1>; 1345 }; 1346 wafer_info: wafer-info@1c { 1347 reg = <0x1c 0x1>; 1348 }; 1349 }; 1350 1351 pmucru: pmu-clock-controller@ff750000 { 1352 compatible = "rockchip,rk3399-pmucru"; 1353 reg = <0x0 0xff750000 0x0 0x1000>; 1354 rockchip,grf = <&pmugrf>; 1355 #clock-cells = <1>; 1356 #reset-cells = <1>; 1357 assigned-clocks = <&pmucru PLL_PPLL>; 1358 assigned-clock-rates = <676000000>; 1359 }; 1360 1361 cru: clock-controller@ff760000 { 1362 compatible = "rockchip,rk3399-cru"; 1363 reg = <0x0 0xff760000 0x0 0x1000>; 1364 rockchip,grf = <&grf>; 1365 #clock-cells = <1>; 1366 #reset-cells = <1>; 1367 assigned-clocks = 1368 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1369 <&cru PLL_NPLL>, 1370 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1371 <&cru PCLK_PERIHP>, 1372 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1373 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1374 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 1375 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 1376 <&cru ACLK_GIC_PRE>, 1377 <&cru PCLK_DDR>; 1378 assigned-clock-rates = 1379 <594000000>, <800000000>, 1380 <1000000000>, 1381 <150000000>, <75000000>, 1382 <37500000>, 1383 <100000000>, <100000000>, 1384 <50000000>, <600000000>, 1385 <100000000>, <50000000>, 1386 <400000000>, <400000000>, 1387 <200000000>, 1388 <200000000>; 1389 }; 1390 1391 grf: syscon@ff770000 { 1392 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1393 reg = <0x0 0xff770000 0x0 0x10000>; 1394 #address-cells = <1>; 1395 #size-cells = <1>; 1396 1397 io_domains: io-domains { 1398 compatible = "rockchip,rk3399-io-voltage-domain"; 1399 status = "disabled"; 1400 }; 1401 1402 mipi_dphy_rx0: mipi-dphy-rx0 { 1403 compatible = "rockchip,rk3399-mipi-dphy-rx0"; 1404 clocks = <&cru SCLK_MIPIDPHY_REF>, 1405 <&cru SCLK_DPHY_RX0_CFG>, 1406 <&cru PCLK_VIO_GRF>; 1407 clock-names = "dphy-ref", "dphy-cfg", "grf"; 1408 power-domains = <&power RK3399_PD_VIO>; 1409 #phy-cells = <0>; 1410 status = "disabled"; 1411 }; 1412 1413 u2phy0: usb2-phy@e450 { 1414 compatible = "rockchip,rk3399-usb2phy"; 1415 reg = <0xe450 0x10>; 1416 clocks = <&cru SCLK_USB2PHY0_REF>; 1417 clock-names = "phyclk"; 1418 #clock-cells = <0>; 1419 clock-output-names = "clk_usbphy0_480m"; 1420 status = "disabled"; 1421 1422 u2phy0_host: host-port { 1423 #phy-cells = <0>; 1424 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1425 interrupt-names = "linestate"; 1426 status = "disabled"; 1427 }; 1428 1429 u2phy0_otg: otg-port { 1430 #phy-cells = <0>; 1431 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1432 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1433 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1434 interrupt-names = "otg-bvalid", "otg-id", 1435 "linestate"; 1436 status = "disabled"; 1437 }; 1438 }; 1439 1440 u2phy1: usb2-phy@e460 { 1441 compatible = "rockchip,rk3399-usb2phy"; 1442 reg = <0xe460 0x10>; 1443 clocks = <&cru SCLK_USB2PHY1_REF>; 1444 clock-names = "phyclk"; 1445 #clock-cells = <0>; 1446 clock-output-names = "clk_usbphy1_480m"; 1447 status = "disabled"; 1448 1449 u2phy1_host: host-port { 1450 #phy-cells = <0>; 1451 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1452 interrupt-names = "linestate"; 1453 status = "disabled"; 1454 }; 1455 1456 u2phy1_otg: otg-port { 1457 #phy-cells = <0>; 1458 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1459 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1460 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1461 interrupt-names = "otg-bvalid", "otg-id", 1462 "linestate"; 1463 status = "disabled"; 1464 }; 1465 }; 1466 1467 emmc_phy: phy@f780 { 1468 compatible = "rockchip,rk3399-emmc-phy"; 1469 reg = <0xf780 0x24>; 1470 clocks = <&sdhci>; 1471 clock-names = "emmcclk"; 1472 #phy-cells = <0>; 1473 status = "disabled"; 1474 }; 1475 1476 pcie_phy: pcie-phy { 1477 compatible = "rockchip,rk3399-pcie-phy"; 1478 clocks = <&cru SCLK_PCIEPHY_REF>; 1479 clock-names = "refclk"; 1480 #phy-cells = <1>; 1481 resets = <&cru SRST_PCIEPHY>; 1482 drive-impedance-ohm = <50>; 1483 reset-names = "phy"; 1484 status = "disabled"; 1485 }; 1486 }; 1487 1488 tcphy0: phy@ff7c0000 { 1489 compatible = "rockchip,rk3399-typec-phy"; 1490 reg = <0x0 0xff7c0000 0x0 0x40000>; 1491 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1492 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1493 clock-names = "tcpdcore", "tcpdphy-ref"; 1494 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1495 assigned-clock-rates = <50000000>; 1496 power-domains = <&power RK3399_PD_TCPD0>; 1497 resets = <&cru SRST_UPHY0>, 1498 <&cru SRST_UPHY0_PIPE_L00>, 1499 <&cru SRST_P_UPHY0_TCPHY>; 1500 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1501 rockchip,grf = <&grf>; 1502 status = "disabled"; 1503 1504 tcphy0_dp: dp-port { 1505 #phy-cells = <0>; 1506 }; 1507 1508 tcphy0_usb3: usb3-port { 1509 #phy-cells = <0>; 1510 }; 1511 }; 1512 1513 tcphy1: phy@ff800000 { 1514 compatible = "rockchip,rk3399-typec-phy"; 1515 reg = <0x0 0xff800000 0x0 0x40000>; 1516 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1517 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1518 clock-names = "tcpdcore", "tcpdphy-ref"; 1519 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1520 assigned-clock-rates = <50000000>; 1521 power-domains = <&power RK3399_PD_TCPD1>; 1522 resets = <&cru SRST_UPHY1>, 1523 <&cru SRST_UPHY1_PIPE_L00>, 1524 <&cru SRST_P_UPHY1_TCPHY>; 1525 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1526 rockchip,grf = <&grf>; 1527 status = "disabled"; 1528 1529 tcphy1_dp: dp-port { 1530 #phy-cells = <0>; 1531 }; 1532 1533 tcphy1_usb3: usb3-port { 1534 #phy-cells = <0>; 1535 }; 1536 }; 1537 1538 watchdog@ff848000 { 1539 compatible = "snps,dw-wdt"; 1540 reg = <0x0 0xff848000 0x0 0x100>; 1541 clocks = <&cru PCLK_WDT>; 1542 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1543 }; 1544 1545 rktimer: rktimer@ff850000 { 1546 compatible = "rockchip,rk3399-timer"; 1547 reg = <0x0 0xff850000 0x0 0x1000>; 1548 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1549 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1550 clock-names = "pclk", "timer"; 1551 }; 1552 1553 spdif: spdif@ff870000 { 1554 compatible = "rockchip,rk3399-spdif"; 1555 reg = <0x0 0xff870000 0x0 0x1000>; 1556 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1557 dmas = <&dmac_bus 7>; 1558 dma-names = "tx"; 1559 clock-names = "mclk", "hclk"; 1560 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1561 pinctrl-names = "default"; 1562 pinctrl-0 = <&spdif_bus>; 1563 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1564 #sound-dai-cells = <0>; 1565 status = "disabled"; 1566 }; 1567 1568 i2s0: i2s@ff880000 { 1569 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1570 reg = <0x0 0xff880000 0x0 0x1000>; 1571 rockchip,grf = <&grf>; 1572 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1573 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1574 dma-names = "tx", "rx"; 1575 clock-names = "i2s_clk", "i2s_hclk"; 1576 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1577 pinctrl-names = "default"; 1578 pinctrl-0 = <&i2s0_8ch_bus>; 1579 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1580 #sound-dai-cells = <0>; 1581 status = "disabled"; 1582 }; 1583 1584 i2s1: i2s@ff890000 { 1585 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1586 reg = <0x0 0xff890000 0x0 0x1000>; 1587 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1588 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1589 dma-names = "tx", "rx"; 1590 clock-names = "i2s_clk", "i2s_hclk"; 1591 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1592 pinctrl-names = "default"; 1593 pinctrl-0 = <&i2s1_2ch_bus>; 1594 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1595 #sound-dai-cells = <0>; 1596 status = "disabled"; 1597 }; 1598 1599 i2s2: i2s@ff8a0000 { 1600 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1601 reg = <0x0 0xff8a0000 0x0 0x1000>; 1602 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1603 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1604 dma-names = "tx", "rx"; 1605 clock-names = "i2s_clk", "i2s_hclk"; 1606 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1607 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1608 #sound-dai-cells = <0>; 1609 status = "disabled"; 1610 }; 1611 1612 vopl: vop@ff8f0000 { 1613 compatible = "rockchip,rk3399-vop-lit"; 1614 reg = <0x0 0xff8f0000 0x0 0x3efc>; 1615 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1616 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1617 assigned-clock-rates = <400000000>, <100000000>; 1618 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1619 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1620 iommus = <&vopl_mmu>; 1621 power-domains = <&power RK3399_PD_VOPL>; 1622 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1623 reset-names = "axi", "ahb", "dclk"; 1624 status = "disabled"; 1625 1626 vopl_out: port { 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 1630 vopl_out_mipi: endpoint@0 { 1631 reg = <0>; 1632 remote-endpoint = <&mipi_in_vopl>; 1633 }; 1634 1635 vopl_out_edp: endpoint@1 { 1636 reg = <1>; 1637 remote-endpoint = <&edp_in_vopl>; 1638 }; 1639 1640 vopl_out_hdmi: endpoint@2 { 1641 reg = <2>; 1642 remote-endpoint = <&hdmi_in_vopl>; 1643 }; 1644 1645 vopl_out_mipi1: endpoint@3 { 1646 reg = <3>; 1647 remote-endpoint = <&mipi1_in_vopl>; 1648 }; 1649 1650 vopl_out_dp: endpoint@4 { 1651 reg = <4>; 1652 remote-endpoint = <&dp_in_vopl>; 1653 }; 1654 }; 1655 }; 1656 1657 vopl_mmu: iommu@ff8f3f00 { 1658 compatible = "rockchip,iommu"; 1659 reg = <0x0 0xff8f3f00 0x0 0x100>; 1660 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1661 interrupt-names = "vopl_mmu"; 1662 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1663 clock-names = "aclk", "iface"; 1664 power-domains = <&power RK3399_PD_VOPL>; 1665 #iommu-cells = <0>; 1666 status = "disabled"; 1667 }; 1668 1669 vopb: vop@ff900000 { 1670 compatible = "rockchip,rk3399-vop-big"; 1671 reg = <0x0 0xff900000 0x0 0x3efc>; 1672 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1673 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1674 assigned-clock-rates = <400000000>, <100000000>; 1675 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1676 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1677 iommus = <&vopb_mmu>; 1678 power-domains = <&power RK3399_PD_VOPB>; 1679 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1680 reset-names = "axi", "ahb", "dclk"; 1681 status = "disabled"; 1682 1683 vopb_out: port { 1684 #address-cells = <1>; 1685 #size-cells = <0>; 1686 1687 vopb_out_edp: endpoint@0 { 1688 reg = <0>; 1689 remote-endpoint = <&edp_in_vopb>; 1690 }; 1691 1692 vopb_out_mipi: endpoint@1 { 1693 reg = <1>; 1694 remote-endpoint = <&mipi_in_vopb>; 1695 }; 1696 1697 vopb_out_hdmi: endpoint@2 { 1698 reg = <2>; 1699 remote-endpoint = <&hdmi_in_vopb>; 1700 }; 1701 1702 vopb_out_mipi1: endpoint@3 { 1703 reg = <3>; 1704 remote-endpoint = <&mipi1_in_vopb>; 1705 }; 1706 1707 vopb_out_dp: endpoint@4 { 1708 reg = <4>; 1709 remote-endpoint = <&dp_in_vopb>; 1710 }; 1711 }; 1712 }; 1713 1714 vopb_mmu: iommu@ff903f00 { 1715 compatible = "rockchip,iommu"; 1716 reg = <0x0 0xff903f00 0x0 0x100>; 1717 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1718 interrupt-names = "vopb_mmu"; 1719 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1720 clock-names = "aclk", "iface"; 1721 power-domains = <&power RK3399_PD_VOPB>; 1722 #iommu-cells = <0>; 1723 status = "disabled"; 1724 }; 1725 1726 isp0_mmu: iommu@ff914000 { 1727 compatible = "rockchip,iommu"; 1728 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1729 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1730 interrupt-names = "isp0_mmu"; 1731 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; 1732 clock-names = "aclk", "iface"; 1733 #iommu-cells = <0>; 1734 power-domains = <&power RK3399_PD_ISP0>; 1735 rockchip,disable-mmu-reset; 1736 }; 1737 1738 isp1_mmu: iommu@ff924000 { 1739 compatible = "rockchip,iommu"; 1740 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; 1741 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1742 interrupt-names = "isp1_mmu"; 1743 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; 1744 clock-names = "aclk", "iface"; 1745 #iommu-cells = <0>; 1746 power-domains = <&power RK3399_PD_ISP1>; 1747 rockchip,disable-mmu-reset; 1748 }; 1749 1750 hdmi_sound: hdmi-sound { 1751 compatible = "simple-audio-card"; 1752 simple-audio-card,format = "i2s"; 1753 simple-audio-card,mclk-fs = <256>; 1754 simple-audio-card,name = "hdmi-sound"; 1755 status = "disabled"; 1756 1757 simple-audio-card,cpu { 1758 sound-dai = <&i2s2>; 1759 }; 1760 simple-audio-card,codec { 1761 sound-dai = <&hdmi>; 1762 }; 1763 }; 1764 1765 hdmi: hdmi@ff940000 { 1766 compatible = "rockchip,rk3399-dw-hdmi"; 1767 reg = <0x0 0xff940000 0x0 0x20000>; 1768 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1769 clocks = <&cru PCLK_HDMI_CTRL>, 1770 <&cru SCLK_HDMI_SFR>, 1771 <&cru PLL_VPLL>, 1772 <&cru PCLK_VIO_GRF>, 1773 <&cru SCLK_HDMI_CEC>; 1774 clock-names = "iahb", "isfr", "vpll", "grf", "cec"; 1775 power-domains = <&power RK3399_PD_HDCP>; 1776 reg-io-width = <4>; 1777 rockchip,grf = <&grf>; 1778 #sound-dai-cells = <0>; 1779 status = "disabled"; 1780 1781 ports { 1782 hdmi_in: port { 1783 #address-cells = <1>; 1784 #size-cells = <0>; 1785 1786 hdmi_in_vopb: endpoint@0 { 1787 reg = <0>; 1788 remote-endpoint = <&vopb_out_hdmi>; 1789 }; 1790 hdmi_in_vopl: endpoint@1 { 1791 reg = <1>; 1792 remote-endpoint = <&vopl_out_hdmi>; 1793 }; 1794 }; 1795 }; 1796 }; 1797 1798 mipi_dsi: mipi@ff960000 { 1799 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1800 reg = <0x0 0xff960000 0x0 0x8000>; 1801 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1802 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, 1803 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; 1804 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1805 power-domains = <&power RK3399_PD_VIO>; 1806 resets = <&cru SRST_P_MIPI_DSI0>; 1807 reset-names = "apb"; 1808 rockchip,grf = <&grf>; 1809 #address-cells = <1>; 1810 #size-cells = <0>; 1811 status = "disabled"; 1812 1813 ports { 1814 #address-cells = <1>; 1815 #size-cells = <0>; 1816 1817 mipi_in: port@0 { 1818 reg = <0>; 1819 #address-cells = <1>; 1820 #size-cells = <0>; 1821 1822 mipi_in_vopb: endpoint@0 { 1823 reg = <0>; 1824 remote-endpoint = <&vopb_out_mipi>; 1825 }; 1826 mipi_in_vopl: endpoint@1 { 1827 reg = <1>; 1828 remote-endpoint = <&vopl_out_mipi>; 1829 }; 1830 }; 1831 }; 1832 }; 1833 1834 mipi_dsi1: mipi@ff968000 { 1835 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1836 reg = <0x0 0xff968000 0x0 0x8000>; 1837 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; 1838 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, 1839 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; 1840 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1841 power-domains = <&power RK3399_PD_VIO>; 1842 resets = <&cru SRST_P_MIPI_DSI1>; 1843 reset-names = "apb"; 1844 rockchip,grf = <&grf>; 1845 #address-cells = <1>; 1846 #size-cells = <0>; 1847 status = "disabled"; 1848 1849 ports { 1850 #address-cells = <1>; 1851 #size-cells = <0>; 1852 1853 mipi1_in: port@0 { 1854 reg = <0>; 1855 #address-cells = <1>; 1856 #size-cells = <0>; 1857 1858 mipi1_in_vopb: endpoint@0 { 1859 reg = <0>; 1860 remote-endpoint = <&vopb_out_mipi1>; 1861 }; 1862 1863 mipi1_in_vopl: endpoint@1 { 1864 reg = <1>; 1865 remote-endpoint = <&vopl_out_mipi1>; 1866 }; 1867 }; 1868 }; 1869 }; 1870 1871 edp: edp@ff970000 { 1872 compatible = "rockchip,rk3399-edp"; 1873 reg = <0x0 0xff970000 0x0 0x8000>; 1874 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 1875 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; 1876 clock-names = "dp", "pclk", "grf"; 1877 pinctrl-names = "default"; 1878 pinctrl-0 = <&edp_hpd>; 1879 power-domains = <&power RK3399_PD_EDP>; 1880 resets = <&cru SRST_P_EDP_CTRL>; 1881 reset-names = "dp"; 1882 rockchip,grf = <&grf>; 1883 status = "disabled"; 1884 1885 ports { 1886 #address-cells = <1>; 1887 #size-cells = <0>; 1888 edp_in: port@0 { 1889 reg = <0>; 1890 #address-cells = <1>; 1891 #size-cells = <0>; 1892 1893 edp_in_vopb: endpoint@0 { 1894 reg = <0>; 1895 remote-endpoint = <&vopb_out_edp>; 1896 }; 1897 1898 edp_in_vopl: endpoint@1 { 1899 reg = <1>; 1900 remote-endpoint = <&vopl_out_edp>; 1901 }; 1902 }; 1903 }; 1904 }; 1905 1906 gpu: gpu@ff9a0000 { 1907 compatible = "rockchip,rk3399-mali", "arm,mali-t860"; 1908 reg = <0x0 0xff9a0000 0x0 0x10000>; 1909 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 1910 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>, 1911 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; 1912 interrupt-names = "job", "mmu", "gpu"; 1913 clocks = <&cru ACLK_GPU>; 1914 #cooling-cells = <2>; 1915 power-domains = <&power RK3399_PD_GPU>; 1916 status = "disabled"; 1917 }; 1918 1919 pinctrl: pinctrl { 1920 compatible = "rockchip,rk3399-pinctrl"; 1921 rockchip,grf = <&grf>; 1922 rockchip,pmu = <&pmugrf>; 1923 #address-cells = <2>; 1924 #size-cells = <2>; 1925 ranges; 1926 1927 gpio0: gpio0@ff720000 { 1928 compatible = "rockchip,gpio-bank"; 1929 reg = <0x0 0xff720000 0x0 0x100>; 1930 clocks = <&pmucru PCLK_GPIO0_PMU>; 1931 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 1932 1933 gpio-controller; 1934 #gpio-cells = <0x2>; 1935 1936 interrupt-controller; 1937 #interrupt-cells = <0x2>; 1938 }; 1939 1940 gpio1: gpio1@ff730000 { 1941 compatible = "rockchip,gpio-bank"; 1942 reg = <0x0 0xff730000 0x0 0x100>; 1943 clocks = <&pmucru PCLK_GPIO1_PMU>; 1944 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 1945 1946 gpio-controller; 1947 #gpio-cells = <0x2>; 1948 1949 interrupt-controller; 1950 #interrupt-cells = <0x2>; 1951 }; 1952 1953 gpio2: gpio2@ff780000 { 1954 compatible = "rockchip,gpio-bank"; 1955 reg = <0x0 0xff780000 0x0 0x100>; 1956 clocks = <&cru PCLK_GPIO2>; 1957 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 1958 1959 gpio-controller; 1960 #gpio-cells = <0x2>; 1961 1962 interrupt-controller; 1963 #interrupt-cells = <0x2>; 1964 }; 1965 1966 gpio3: gpio3@ff788000 { 1967 compatible = "rockchip,gpio-bank"; 1968 reg = <0x0 0xff788000 0x0 0x100>; 1969 clocks = <&cru PCLK_GPIO3>; 1970 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 1971 1972 gpio-controller; 1973 #gpio-cells = <0x2>; 1974 1975 interrupt-controller; 1976 #interrupt-cells = <0x2>; 1977 }; 1978 1979 gpio4: gpio4@ff790000 { 1980 compatible = "rockchip,gpio-bank"; 1981 reg = <0x0 0xff790000 0x0 0x100>; 1982 clocks = <&cru PCLK_GPIO4>; 1983 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 1984 1985 gpio-controller; 1986 #gpio-cells = <0x2>; 1987 1988 interrupt-controller; 1989 #interrupt-cells = <0x2>; 1990 }; 1991 1992 pcfg_pull_up: pcfg-pull-up { 1993 bias-pull-up; 1994 }; 1995 1996 pcfg_pull_down: pcfg-pull-down { 1997 bias-pull-down; 1998 }; 1999 2000 pcfg_pull_none: pcfg-pull-none { 2001 bias-disable; 2002 }; 2003 2004 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 2005 bias-disable; 2006 drive-strength = <12>; 2007 }; 2008 2009 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 2010 bias-disable; 2011 drive-strength = <13>; 2012 }; 2013 2014 pcfg_pull_none_18ma: pcfg-pull-none-18ma { 2015 bias-disable; 2016 drive-strength = <18>; 2017 }; 2018 2019 pcfg_pull_none_20ma: pcfg-pull-none-20ma { 2020 bias-disable; 2021 drive-strength = <20>; 2022 }; 2023 2024 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 2025 bias-pull-up; 2026 drive-strength = <2>; 2027 }; 2028 2029 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 2030 bias-pull-up; 2031 drive-strength = <8>; 2032 }; 2033 2034 pcfg_pull_up_18ma: pcfg-pull-up-18ma { 2035 bias-pull-up; 2036 drive-strength = <18>; 2037 }; 2038 2039 pcfg_pull_up_20ma: pcfg-pull-up-20ma { 2040 bias-pull-up; 2041 drive-strength = <20>; 2042 }; 2043 2044 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 2045 bias-pull-down; 2046 drive-strength = <4>; 2047 }; 2048 2049 pcfg_pull_down_8ma: pcfg-pull-down-8ma { 2050 bias-pull-down; 2051 drive-strength = <8>; 2052 }; 2053 2054 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 2055 bias-pull-down; 2056 drive-strength = <12>; 2057 }; 2058 2059 pcfg_pull_down_18ma: pcfg-pull-down-18ma { 2060 bias-pull-down; 2061 drive-strength = <18>; 2062 }; 2063 2064 pcfg_pull_down_20ma: pcfg-pull-down-20ma { 2065 bias-pull-down; 2066 drive-strength = <20>; 2067 }; 2068 2069 pcfg_output_high: pcfg-output-high { 2070 output-high; 2071 }; 2072 2073 pcfg_output_low: pcfg-output-low { 2074 output-low; 2075 }; 2076 2077 clock { 2078 clk_32k: clk-32k { 2079 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; 2080 }; 2081 }; 2082 2083 edp { 2084 edp_hpd: edp-hpd { 2085 rockchip,pins = 2086 <4 RK_PC7 2 &pcfg_pull_none>; 2087 }; 2088 }; 2089 2090 gmac { 2091 rgmii_pins: rgmii-pins { 2092 rockchip,pins = 2093 /* mac_txclk */ 2094 <3 RK_PC1 1 &pcfg_pull_none_13ma>, 2095 /* mac_rxclk */ 2096 <3 RK_PB6 1 &pcfg_pull_none>, 2097 /* mac_mdio */ 2098 <3 RK_PB5 1 &pcfg_pull_none>, 2099 /* mac_txen */ 2100 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2101 /* mac_clk */ 2102 <3 RK_PB3 1 &pcfg_pull_none>, 2103 /* mac_rxdv */ 2104 <3 RK_PB1 1 &pcfg_pull_none>, 2105 /* mac_mdc */ 2106 <3 RK_PB0 1 &pcfg_pull_none>, 2107 /* mac_rxd1 */ 2108 <3 RK_PA7 1 &pcfg_pull_none>, 2109 /* mac_rxd0 */ 2110 <3 RK_PA6 1 &pcfg_pull_none>, 2111 /* mac_txd1 */ 2112 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2113 /* mac_txd0 */ 2114 <3 RK_PA4 1 &pcfg_pull_none_13ma>, 2115 /* mac_rxd3 */ 2116 <3 RK_PA3 1 &pcfg_pull_none>, 2117 /* mac_rxd2 */ 2118 <3 RK_PA2 1 &pcfg_pull_none>, 2119 /* mac_txd3 */ 2120 <3 RK_PA1 1 &pcfg_pull_none_13ma>, 2121 /* mac_txd2 */ 2122 <3 RK_PA0 1 &pcfg_pull_none_13ma>; 2123 }; 2124 2125 rmii_pins: rmii-pins { 2126 rockchip,pins = 2127 /* mac_mdio */ 2128 <3 RK_PB5 1 &pcfg_pull_none>, 2129 /* mac_txen */ 2130 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2131 /* mac_clk */ 2132 <3 RK_PB3 1 &pcfg_pull_none>, 2133 /* mac_rxer */ 2134 <3 RK_PB2 1 &pcfg_pull_none>, 2135 /* mac_rxdv */ 2136 <3 RK_PB1 1 &pcfg_pull_none>, 2137 /* mac_mdc */ 2138 <3 RK_PB0 1 &pcfg_pull_none>, 2139 /* mac_rxd1 */ 2140 <3 RK_PA7 1 &pcfg_pull_none>, 2141 /* mac_rxd0 */ 2142 <3 RK_PA6 1 &pcfg_pull_none>, 2143 /* mac_txd1 */ 2144 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2145 /* mac_txd0 */ 2146 <3 RK_PA4 1 &pcfg_pull_none_13ma>; 2147 }; 2148 }; 2149 2150 i2c0 { 2151 i2c0_xfer: i2c0-xfer { 2152 rockchip,pins = 2153 <1 RK_PB7 2 &pcfg_pull_none>, 2154 <1 RK_PC0 2 &pcfg_pull_none>; 2155 }; 2156 }; 2157 2158 i2c1 { 2159 i2c1_xfer: i2c1-xfer { 2160 rockchip,pins = 2161 <4 RK_PA2 1 &pcfg_pull_none>, 2162 <4 RK_PA1 1 &pcfg_pull_none>; 2163 }; 2164 }; 2165 2166 i2c2 { 2167 i2c2_xfer: i2c2-xfer { 2168 rockchip,pins = 2169 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 2170 <2 RK_PA0 2 &pcfg_pull_none_12ma>; 2171 }; 2172 }; 2173 2174 i2c3 { 2175 i2c3_xfer: i2c3-xfer { 2176 rockchip,pins = 2177 <4 RK_PC1 1 &pcfg_pull_none>, 2178 <4 RK_PC0 1 &pcfg_pull_none>; 2179 }; 2180 }; 2181 2182 i2c4 { 2183 i2c4_xfer: i2c4-xfer { 2184 rockchip,pins = 2185 <1 RK_PB4 1 &pcfg_pull_none>, 2186 <1 RK_PB3 1 &pcfg_pull_none>; 2187 }; 2188 }; 2189 2190 i2c5 { 2191 i2c5_xfer: i2c5-xfer { 2192 rockchip,pins = 2193 <3 RK_PB3 2 &pcfg_pull_none>, 2194 <3 RK_PB2 2 &pcfg_pull_none>; 2195 }; 2196 }; 2197 2198 i2c6 { 2199 i2c6_xfer: i2c6-xfer { 2200 rockchip,pins = 2201 <2 RK_PB2 2 &pcfg_pull_none>, 2202 <2 RK_PB1 2 &pcfg_pull_none>; 2203 }; 2204 }; 2205 2206 i2c7 { 2207 i2c7_xfer: i2c7-xfer { 2208 rockchip,pins = 2209 <2 RK_PB0 2 &pcfg_pull_none>, 2210 <2 RK_PA7 2 &pcfg_pull_none>; 2211 }; 2212 }; 2213 2214 i2c8 { 2215 i2c8_xfer: i2c8-xfer { 2216 rockchip,pins = 2217 <1 RK_PC5 1 &pcfg_pull_none>, 2218 <1 RK_PC4 1 &pcfg_pull_none>; 2219 }; 2220 }; 2221 2222 i2s0 { 2223 i2s0_2ch_bus: i2s0-2ch-bus { 2224 rockchip,pins = 2225 <3 RK_PD0 1 &pcfg_pull_none>, 2226 <3 RK_PD1 1 &pcfg_pull_none>, 2227 <3 RK_PD2 1 &pcfg_pull_none>, 2228 <3 RK_PD3 1 &pcfg_pull_none>, 2229 <3 RK_PD7 1 &pcfg_pull_none>, 2230 <4 RK_PA0 1 &pcfg_pull_none>; 2231 }; 2232 2233 i2s0_8ch_bus: i2s0-8ch-bus { 2234 rockchip,pins = 2235 <3 RK_PD0 1 &pcfg_pull_none>, 2236 <3 RK_PD1 1 &pcfg_pull_none>, 2237 <3 RK_PD2 1 &pcfg_pull_none>, 2238 <3 RK_PD3 1 &pcfg_pull_none>, 2239 <3 RK_PD4 1 &pcfg_pull_none>, 2240 <3 RK_PD5 1 &pcfg_pull_none>, 2241 <3 RK_PD6 1 &pcfg_pull_none>, 2242 <3 RK_PD7 1 &pcfg_pull_none>, 2243 <4 RK_PA0 1 &pcfg_pull_none>; 2244 }; 2245 }; 2246 2247 i2s1 { 2248 i2s1_2ch_bus: i2s1-2ch-bus { 2249 rockchip,pins = 2250 <4 RK_PA3 1 &pcfg_pull_none>, 2251 <4 RK_PA4 1 &pcfg_pull_none>, 2252 <4 RK_PA5 1 &pcfg_pull_none>, 2253 <4 RK_PA6 1 &pcfg_pull_none>, 2254 <4 RK_PA7 1 &pcfg_pull_none>; 2255 }; 2256 }; 2257 2258 sdio0 { 2259 sdio0_bus1: sdio0-bus1 { 2260 rockchip,pins = 2261 <2 RK_PC4 1 &pcfg_pull_up>; 2262 }; 2263 2264 sdio0_bus4: sdio0-bus4 { 2265 rockchip,pins = 2266 <2 RK_PC4 1 &pcfg_pull_up>, 2267 <2 RK_PC5 1 &pcfg_pull_up>, 2268 <2 RK_PC6 1 &pcfg_pull_up>, 2269 <2 RK_PC7 1 &pcfg_pull_up>; 2270 }; 2271 2272 sdio0_cmd: sdio0-cmd { 2273 rockchip,pins = 2274 <2 RK_PD0 1 &pcfg_pull_up>; 2275 }; 2276 2277 sdio0_clk: sdio0-clk { 2278 rockchip,pins = 2279 <2 RK_PD1 1 &pcfg_pull_none>; 2280 }; 2281 2282 sdio0_cd: sdio0-cd { 2283 rockchip,pins = 2284 <2 RK_PD2 1 &pcfg_pull_up>; 2285 }; 2286 2287 sdio0_pwr: sdio0-pwr { 2288 rockchip,pins = 2289 <2 RK_PD3 1 &pcfg_pull_up>; 2290 }; 2291 2292 sdio0_bkpwr: sdio0-bkpwr { 2293 rockchip,pins = 2294 <2 RK_PD4 1 &pcfg_pull_up>; 2295 }; 2296 2297 sdio0_wp: sdio0-wp { 2298 rockchip,pins = 2299 <0 RK_PA3 1 &pcfg_pull_up>; 2300 }; 2301 2302 sdio0_int: sdio0-int { 2303 rockchip,pins = 2304 <0 RK_PA4 1 &pcfg_pull_up>; 2305 }; 2306 }; 2307 2308 sdmmc { 2309 sdmmc_bus1: sdmmc-bus1 { 2310 rockchip,pins = 2311 <4 RK_PB0 1 &pcfg_pull_up>; 2312 }; 2313 2314 sdmmc_bus4: sdmmc-bus4 { 2315 rockchip,pins = 2316 <4 RK_PB0 1 &pcfg_pull_up>, 2317 <4 RK_PB1 1 &pcfg_pull_up>, 2318 <4 RK_PB2 1 &pcfg_pull_up>, 2319 <4 RK_PB3 1 &pcfg_pull_up>; 2320 }; 2321 2322 sdmmc_clk: sdmmc-clk { 2323 rockchip,pins = 2324 <4 RK_PB4 1 &pcfg_pull_none>; 2325 }; 2326 2327 sdmmc_cmd: sdmmc-cmd { 2328 rockchip,pins = 2329 <4 RK_PB5 1 &pcfg_pull_up>; 2330 }; 2331 2332 sdmmc_cd: sdmmc-cd { 2333 rockchip,pins = 2334 <0 RK_PA7 1 &pcfg_pull_up>; 2335 }; 2336 2337 sdmmc_wp: sdmmc-wp { 2338 rockchip,pins = 2339 <0 RK_PB0 1 &pcfg_pull_up>; 2340 }; 2341 }; 2342 2343 sleep { 2344 ap_pwroff: ap-pwroff { 2345 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; 2346 }; 2347 2348 ddrio_pwroff: ddrio-pwroff { 2349 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; 2350 }; 2351 }; 2352 2353 spdif { 2354 spdif_bus: spdif-bus { 2355 rockchip,pins = 2356 <4 RK_PC5 1 &pcfg_pull_none>; 2357 }; 2358 2359 spdif_bus_1: spdif-bus-1 { 2360 rockchip,pins = 2361 <3 RK_PC0 3 &pcfg_pull_none>; 2362 }; 2363 }; 2364 2365 spi0 { 2366 spi0_clk: spi0-clk { 2367 rockchip,pins = 2368 <3 RK_PA6 2 &pcfg_pull_up>; 2369 }; 2370 spi0_cs0: spi0-cs0 { 2371 rockchip,pins = 2372 <3 RK_PA7 2 &pcfg_pull_up>; 2373 }; 2374 spi0_cs1: spi0-cs1 { 2375 rockchip,pins = 2376 <3 RK_PB0 2 &pcfg_pull_up>; 2377 }; 2378 spi0_tx: spi0-tx { 2379 rockchip,pins = 2380 <3 RK_PA5 2 &pcfg_pull_up>; 2381 }; 2382 spi0_rx: spi0-rx { 2383 rockchip,pins = 2384 <3 RK_PA4 2 &pcfg_pull_up>; 2385 }; 2386 }; 2387 2388 spi1 { 2389 spi1_clk: spi1-clk { 2390 rockchip,pins = 2391 <1 RK_PB1 2 &pcfg_pull_up>; 2392 }; 2393 spi1_cs0: spi1-cs0 { 2394 rockchip,pins = 2395 <1 RK_PB2 2 &pcfg_pull_up>; 2396 }; 2397 spi1_rx: spi1-rx { 2398 rockchip,pins = 2399 <1 RK_PA7 2 &pcfg_pull_up>; 2400 }; 2401 spi1_tx: spi1-tx { 2402 rockchip,pins = 2403 <1 RK_PB0 2 &pcfg_pull_up>; 2404 }; 2405 }; 2406 2407 spi2 { 2408 spi2_clk: spi2-clk { 2409 rockchip,pins = 2410 <2 RK_PB3 1 &pcfg_pull_up>; 2411 }; 2412 spi2_cs0: spi2-cs0 { 2413 rockchip,pins = 2414 <2 RK_PB4 1 &pcfg_pull_up>; 2415 }; 2416 spi2_rx: spi2-rx { 2417 rockchip,pins = 2418 <2 RK_PB1 1 &pcfg_pull_up>; 2419 }; 2420 spi2_tx: spi2-tx { 2421 rockchip,pins = 2422 <2 RK_PB2 1 &pcfg_pull_up>; 2423 }; 2424 }; 2425 2426 spi3 { 2427 spi3_clk: spi3-clk { 2428 rockchip,pins = 2429 <1 RK_PC1 1 &pcfg_pull_up>; 2430 }; 2431 spi3_cs0: spi3-cs0 { 2432 rockchip,pins = 2433 <1 RK_PC2 1 &pcfg_pull_up>; 2434 }; 2435 spi3_rx: spi3-rx { 2436 rockchip,pins = 2437 <1 RK_PB7 1 &pcfg_pull_up>; 2438 }; 2439 spi3_tx: spi3-tx { 2440 rockchip,pins = 2441 <1 RK_PC0 1 &pcfg_pull_up>; 2442 }; 2443 }; 2444 2445 spi4 { 2446 spi4_clk: spi4-clk { 2447 rockchip,pins = 2448 <3 RK_PA2 2 &pcfg_pull_up>; 2449 }; 2450 spi4_cs0: spi4-cs0 { 2451 rockchip,pins = 2452 <3 RK_PA3 2 &pcfg_pull_up>; 2453 }; 2454 spi4_rx: spi4-rx { 2455 rockchip,pins = 2456 <3 RK_PA0 2 &pcfg_pull_up>; 2457 }; 2458 spi4_tx: spi4-tx { 2459 rockchip,pins = 2460 <3 RK_PA1 2 &pcfg_pull_up>; 2461 }; 2462 }; 2463 2464 spi5 { 2465 spi5_clk: spi5-clk { 2466 rockchip,pins = 2467 <2 RK_PC6 2 &pcfg_pull_up>; 2468 }; 2469 spi5_cs0: spi5-cs0 { 2470 rockchip,pins = 2471 <2 RK_PC7 2 &pcfg_pull_up>; 2472 }; 2473 spi5_rx: spi5-rx { 2474 rockchip,pins = 2475 <2 RK_PC4 2 &pcfg_pull_up>; 2476 }; 2477 spi5_tx: spi5-tx { 2478 rockchip,pins = 2479 <2 RK_PC5 2 &pcfg_pull_up>; 2480 }; 2481 }; 2482 2483 testclk { 2484 test_clkout0: test-clkout0 { 2485 rockchip,pins = 2486 <0 RK_PA0 1 &pcfg_pull_none>; 2487 }; 2488 2489 test_clkout1: test-clkout1 { 2490 rockchip,pins = 2491 <2 RK_PD1 2 &pcfg_pull_none>; 2492 }; 2493 2494 test_clkout2: test-clkout2 { 2495 rockchip,pins = 2496 <0 RK_PB0 3 &pcfg_pull_none>; 2497 }; 2498 }; 2499 2500 tsadc { 2501 otp_pin: otp-pin { 2502 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2503 }; 2504 2505 otp_out: otp-out { 2506 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; 2507 }; 2508 }; 2509 2510 uart0 { 2511 uart0_xfer: uart0-xfer { 2512 rockchip,pins = 2513 <2 RK_PC0 1 &pcfg_pull_up>, 2514 <2 RK_PC1 1 &pcfg_pull_none>; 2515 }; 2516 2517 uart0_cts: uart0-cts { 2518 rockchip,pins = 2519 <2 RK_PC2 1 &pcfg_pull_none>; 2520 }; 2521 2522 uart0_rts: uart0-rts { 2523 rockchip,pins = 2524 <2 RK_PC3 1 &pcfg_pull_none>; 2525 }; 2526 }; 2527 2528 uart1 { 2529 uart1_xfer: uart1-xfer { 2530 rockchip,pins = 2531 <3 RK_PB4 2 &pcfg_pull_up>, 2532 <3 RK_PB5 2 &pcfg_pull_none>; 2533 }; 2534 }; 2535 2536 uart2a { 2537 uart2a_xfer: uart2a-xfer { 2538 rockchip,pins = 2539 <4 RK_PB0 2 &pcfg_pull_up>, 2540 <4 RK_PB1 2 &pcfg_pull_none>; 2541 }; 2542 }; 2543 2544 uart2b { 2545 uart2b_xfer: uart2b-xfer { 2546 rockchip,pins = 2547 <4 RK_PC0 2 &pcfg_pull_up>, 2548 <4 RK_PC1 2 &pcfg_pull_none>; 2549 }; 2550 }; 2551 2552 uart2c { 2553 uart2c_xfer: uart2c-xfer { 2554 rockchip,pins = 2555 <4 RK_PC3 1 &pcfg_pull_up>, 2556 <4 RK_PC4 1 &pcfg_pull_none>; 2557 }; 2558 }; 2559 2560 uart3 { 2561 uart3_xfer: uart3-xfer { 2562 rockchip,pins = 2563 <3 RK_PB6 2 &pcfg_pull_up>, 2564 <3 RK_PB7 2 &pcfg_pull_none>; 2565 }; 2566 2567 uart3_cts: uart3-cts { 2568 rockchip,pins = 2569 <3 RK_PC0 2 &pcfg_pull_none>; 2570 }; 2571 2572 uart3_rts: uart3-rts { 2573 rockchip,pins = 2574 <3 RK_PC1 2 &pcfg_pull_none>; 2575 }; 2576 }; 2577 2578 uart4 { 2579 uart4_xfer: uart4-xfer { 2580 rockchip,pins = 2581 <1 RK_PA7 1 &pcfg_pull_up>, 2582 <1 RK_PB0 1 &pcfg_pull_none>; 2583 }; 2584 }; 2585 2586 uarthdcp { 2587 uarthdcp_xfer: uarthdcp-xfer { 2588 rockchip,pins = 2589 <4 RK_PC5 2 &pcfg_pull_up>, 2590 <4 RK_PC6 2 &pcfg_pull_none>; 2591 }; 2592 }; 2593 2594 pwm0 { 2595 pwm0_pin: pwm0-pin { 2596 rockchip,pins = 2597 <4 RK_PC2 1 &pcfg_pull_none>; 2598 }; 2599 2600 pwm0_pin_pull_down: pwm0-pin-pull-down { 2601 rockchip,pins = 2602 <4 RK_PC2 1 &pcfg_pull_down>; 2603 }; 2604 2605 vop0_pwm_pin: vop0-pwm-pin { 2606 rockchip,pins = 2607 <4 RK_PC2 2 &pcfg_pull_none>; 2608 }; 2609 2610 vop1_pwm_pin: vop1-pwm-pin { 2611 rockchip,pins = 2612 <4 RK_PC2 3 &pcfg_pull_none>; 2613 }; 2614 }; 2615 2616 pwm1 { 2617 pwm1_pin: pwm1-pin { 2618 rockchip,pins = 2619 <4 RK_PC6 1 &pcfg_pull_none>; 2620 }; 2621 2622 pwm1_pin_pull_down: pwm1-pin-pull-down { 2623 rockchip,pins = 2624 <4 RK_PC6 1 &pcfg_pull_down>; 2625 }; 2626 }; 2627 2628 pwm2 { 2629 pwm2_pin: pwm2-pin { 2630 rockchip,pins = 2631 <1 RK_PC3 1 &pcfg_pull_none>; 2632 }; 2633 2634 pwm2_pin_pull_down: pwm2-pin-pull-down { 2635 rockchip,pins = 2636 <1 RK_PC3 1 &pcfg_pull_down>; 2637 }; 2638 }; 2639 2640 pwm3a { 2641 pwm3a_pin: pwm3a-pin { 2642 rockchip,pins = 2643 <0 RK_PA6 1 &pcfg_pull_none>; 2644 }; 2645 }; 2646 2647 pwm3b { 2648 pwm3b_pin: pwm3b-pin { 2649 rockchip,pins = 2650 <1 RK_PB6 1 &pcfg_pull_none>; 2651 }; 2652 }; 2653 2654 hdmi { 2655 hdmi_i2c_xfer: hdmi-i2c-xfer { 2656 rockchip,pins = 2657 <4 RK_PC1 3 &pcfg_pull_none>, 2658 <4 RK_PC0 3 &pcfg_pull_none>; 2659 }; 2660 2661 hdmi_cec: hdmi-cec { 2662 rockchip,pins = 2663 <4 RK_PC7 1 &pcfg_pull_none>; 2664 }; 2665 }; 2666 2667 pcie { 2668 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2669 rockchip,pins = 2670 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2671 }; 2672 2673 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2674 rockchip,pins = 2675 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2676 }; 2677 }; 2678 2679 }; 2680}; 2681