1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/rk3399-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rk3399-power.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "rockchip,rk3399"; 16 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 aliases { 22 gpio0 = &gpio0; 23 gpio1 = &gpio1; 24 gpio2 = &gpio2; 25 gpio3 = &gpio3; 26 gpio4 = &gpio4; 27 i2c0 = &i2c0; 28 i2c1 = &i2c1; 29 i2c2 = &i2c2; 30 i2c3 = &i2c3; 31 i2c4 = &i2c4; 32 i2c5 = &i2c5; 33 i2c6 = &i2c6; 34 i2c7 = &i2c7; 35 i2c8 = &i2c8; 36 serial0 = &uart0; 37 serial1 = &uart1; 38 serial2 = &uart2; 39 serial3 = &uart3; 40 serial4 = &uart4; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 cpu-map { 48 cluster0 { 49 core0 { 50 cpu = <&cpu_l0>; 51 }; 52 core1 { 53 cpu = <&cpu_l1>; 54 }; 55 core2 { 56 cpu = <&cpu_l2>; 57 }; 58 core3 { 59 cpu = <&cpu_l3>; 60 }; 61 }; 62 63 cluster1 { 64 core0 { 65 cpu = <&cpu_b0>; 66 }; 67 core1 { 68 cpu = <&cpu_b1>; 69 }; 70 }; 71 }; 72 73 cpu_l0: cpu@0 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53"; 76 reg = <0x0 0x0>; 77 enable-method = "psci"; 78 capacity-dmips-mhz = <485>; 79 clocks = <&cru ARMCLKL>; 80 #cooling-cells = <2>; /* min followed by max */ 81 dynamic-power-coefficient = <100>; 82 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 83 }; 84 85 cpu_l1: cpu@1 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a53"; 88 reg = <0x0 0x1>; 89 enable-method = "psci"; 90 capacity-dmips-mhz = <485>; 91 clocks = <&cru ARMCLKL>; 92 #cooling-cells = <2>; /* min followed by max */ 93 dynamic-power-coefficient = <100>; 94 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 95 }; 96 97 cpu_l2: cpu@2 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a53"; 100 reg = <0x0 0x2>; 101 enable-method = "psci"; 102 capacity-dmips-mhz = <485>; 103 clocks = <&cru ARMCLKL>; 104 #cooling-cells = <2>; /* min followed by max */ 105 dynamic-power-coefficient = <100>; 106 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 107 }; 108 109 cpu_l3: cpu@3 { 110 device_type = "cpu"; 111 compatible = "arm,cortex-a53"; 112 reg = <0x0 0x3>; 113 enable-method = "psci"; 114 capacity-dmips-mhz = <485>; 115 clocks = <&cru ARMCLKL>; 116 #cooling-cells = <2>; /* min followed by max */ 117 dynamic-power-coefficient = <100>; 118 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 119 }; 120 121 cpu_b0: cpu@100 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a72"; 124 reg = <0x0 0x100>; 125 enable-method = "psci"; 126 capacity-dmips-mhz = <1024>; 127 clocks = <&cru ARMCLKB>; 128 #cooling-cells = <2>; /* min followed by max */ 129 dynamic-power-coefficient = <436>; 130 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 131 132 thermal-idle { 133 #cooling-cells = <2>; 134 duration-us = <10000>; 135 exit-latency-us = <500>; 136 }; 137 }; 138 139 cpu_b1: cpu@101 { 140 device_type = "cpu"; 141 compatible = "arm,cortex-a72"; 142 reg = <0x0 0x101>; 143 enable-method = "psci"; 144 capacity-dmips-mhz = <1024>; 145 clocks = <&cru ARMCLKB>; 146 #cooling-cells = <2>; /* min followed by max */ 147 dynamic-power-coefficient = <436>; 148 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 149 150 thermal-idle { 151 #cooling-cells = <2>; 152 duration-us = <10000>; 153 exit-latency-us = <500>; 154 }; 155 }; 156 157 idle-states { 158 entry-method = "psci"; 159 160 CPU_SLEEP: cpu-sleep { 161 compatible = "arm,idle-state"; 162 local-timer-stop; 163 arm,psci-suspend-param = <0x0010000>; 164 entry-latency-us = <120>; 165 exit-latency-us = <250>; 166 min-residency-us = <900>; 167 }; 168 169 CLUSTER_SLEEP: cluster-sleep { 170 compatible = "arm,idle-state"; 171 local-timer-stop; 172 arm,psci-suspend-param = <0x1010000>; 173 entry-latency-us = <400>; 174 exit-latency-us = <500>; 175 min-residency-us = <2000>; 176 }; 177 }; 178 }; 179 180 display-subsystem { 181 compatible = "rockchip,display-subsystem"; 182 ports = <&vopl_out>, <&vopb_out>; 183 }; 184 185 dmc: memory-controller { 186 compatible = "rockchip,rk3399-dmc"; 187 rockchip,pmu = <&pmugrf>; 188 devfreq-events = <&dfi>; 189 clocks = <&cru SCLK_DDRC>; 190 clock-names = "dmc_clk"; 191 status = "disabled"; 192 }; 193 194 pmu_a53 { 195 compatible = "arm,cortex-a53-pmu"; 196 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 197 }; 198 199 pmu_a72 { 200 compatible = "arm,cortex-a72-pmu"; 201 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 202 }; 203 204 psci { 205 compatible = "arm,psci-1.0"; 206 method = "smc"; 207 }; 208 209 timer { 210 compatible = "arm,armv8-timer"; 211 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 212 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 213 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 214 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 215 arm,no-tick-in-suspend; 216 }; 217 218 xin24m: xin24m { 219 compatible = "fixed-clock"; 220 clock-frequency = <24000000>; 221 clock-output-names = "xin24m"; 222 #clock-cells = <0>; 223 }; 224 225 pcie0: pcie@f8000000 { 226 compatible = "rockchip,rk3399-pcie"; 227 reg = <0x0 0xf8000000 0x0 0x2000000>, 228 <0x0 0xfd000000 0x0 0x1000000>; 229 reg-names = "axi-base", "apb-base"; 230 device_type = "pci"; 231 #address-cells = <3>; 232 #size-cells = <2>; 233 #interrupt-cells = <1>; 234 aspm-no-l0s; 235 bus-range = <0x0 0x1f>; 236 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 237 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 238 clock-names = "aclk", "aclk-perf", 239 "hclk", "pm"; 240 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>, 241 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>, 242 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>; 243 interrupt-names = "sys", "legacy", "client"; 244 interrupt-map-mask = <0 0 0 7>; 245 interrupt-map = <0 0 0 1 &pcie0_intc 0>, 246 <0 0 0 2 &pcie0_intc 1>, 247 <0 0 0 3 &pcie0_intc 2>, 248 <0 0 0 4 &pcie0_intc 3>; 249 max-link-speed = <1>; 250 msi-map = <0x0 &its 0x0 0x1000>; 251 phys = <&pcie_phy 0>, <&pcie_phy 1>, 252 <&pcie_phy 2>, <&pcie_phy 3>; 253 phy-names = "pcie-phy-0", "pcie-phy-1", 254 "pcie-phy-2", "pcie-phy-3"; 255 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>, 256 <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>; 257 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 258 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 259 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 260 <&cru SRST_A_PCIE>; 261 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 262 "pm", "pclk", "aclk"; 263 status = "disabled"; 264 265 pcie0_intc: interrupt-controller { 266 interrupt-controller; 267 #address-cells = <0>; 268 #interrupt-cells = <1>; 269 }; 270 }; 271 272 pcie0_ep: pcie-ep@f8000000 { 273 compatible = "rockchip,rk3399-pcie-ep"; 274 reg = <0x0 0xfd000000 0x0 0x1000000>, 275 <0x0 0xfa000000 0x0 0x2000000>; 276 reg-names = "apb-base", "mem-base"; 277 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>, 278 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>; 279 clock-names = "aclk", "aclk-perf", 280 "hclk", "pm"; 281 max-functions = /bits/ 8 <8>; 282 num-lanes = <4>; 283 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>, 284 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>, 285 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, 286 <&cru SRST_A_PCIE>; 287 reset-names = "core", "mgmt", "mgmt-sticky", "pipe", 288 "pm", "pclk", "aclk"; 289 phys = <&pcie_phy 0>, <&pcie_phy 1>, 290 <&pcie_phy 2>, <&pcie_phy 3>; 291 phy-names = "pcie-phy-0", "pcie-phy-1", 292 "pcie-phy-2", "pcie-phy-3"; 293 rockchip,max-outbound-regions = <32>; 294 pinctrl-names = "default"; 295 pinctrl-0 = <&pcie_clkreqnb_cpm>; 296 status = "disabled"; 297 }; 298 299 gmac: ethernet@fe300000 { 300 compatible = "rockchip,rk3399-gmac"; 301 reg = <0x0 0xfe300000 0x0 0x10000>; 302 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>; 303 interrupt-names = "macirq"; 304 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, 305 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>, 306 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>, 307 <&cru PCLK_GMAC>; 308 clock-names = "stmmaceth", "mac_clk_rx", 309 "mac_clk_tx", "clk_mac_ref", 310 "clk_mac_refout", "aclk_mac", 311 "pclk_mac"; 312 power-domains = <&power RK3399_PD_GMAC>; 313 resets = <&cru SRST_A_GMAC>; 314 reset-names = "stmmaceth"; 315 rockchip,grf = <&grf>; 316 snps,txpbl = <0x4>; 317 status = "disabled"; 318 }; 319 320 sdio0: mmc@fe310000 { 321 compatible = "rockchip,rk3399-dw-mshc", 322 "rockchip,rk3288-dw-mshc"; 323 reg = <0x0 0xfe310000 0x0 0x4000>; 324 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>; 325 max-frequency = <150000000>; 326 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 327 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 328 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 329 fifo-depth = <0x100>; 330 power-domains = <&power RK3399_PD_SDIOAUDIO>; 331 resets = <&cru SRST_SDIO0>; 332 reset-names = "reset"; 333 status = "disabled"; 334 }; 335 336 sdmmc: mmc@fe320000 { 337 compatible = "rockchip,rk3399-dw-mshc", 338 "rockchip,rk3288-dw-mshc"; 339 reg = <0x0 0xfe320000 0x0 0x4000>; 340 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>; 341 max-frequency = <150000000>; 342 assigned-clocks = <&cru HCLK_SD>; 343 assigned-clock-rates = <200000000>; 344 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 345 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 346 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 347 fifo-depth = <0x100>; 348 power-domains = <&power RK3399_PD_SD>; 349 resets = <&cru SRST_SDMMC>; 350 reset-names = "reset"; 351 status = "disabled"; 352 }; 353 354 sdhci: mmc@fe330000 { 355 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; 356 reg = <0x0 0xfe330000 0x0 0x10000>; 357 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>; 358 arasan,soc-ctl-syscon = <&grf>; 359 assigned-clocks = <&cru SCLK_EMMC>; 360 assigned-clock-rates = <200000000>; 361 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; 362 clock-names = "clk_xin", "clk_ahb"; 363 clock-output-names = "emmc_cardclock"; 364 #clock-cells = <0>; 365 phys = <&emmc_phy>; 366 phy-names = "phy_arasan"; 367 power-domains = <&power RK3399_PD_EMMC>; 368 disable-cqe-dcmd; 369 status = "disabled"; 370 }; 371 372 usb_host0_ehci: usb@fe380000 { 373 compatible = "generic-ehci"; 374 reg = <0x0 0xfe380000 0x0 0x20000>; 375 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>; 376 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 377 <&u2phy0>; 378 phys = <&u2phy0_host>; 379 phy-names = "usb"; 380 status = "disabled"; 381 }; 382 383 usb_host0_ohci: usb@fe3a0000 { 384 compatible = "generic-ohci"; 385 reg = <0x0 0xfe3a0000 0x0 0x20000>; 386 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>; 387 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>, 388 <&u2phy0>; 389 phys = <&u2phy0_host>; 390 phy-names = "usb"; 391 status = "disabled"; 392 }; 393 394 usb_host1_ehci: usb@fe3c0000 { 395 compatible = "generic-ehci"; 396 reg = <0x0 0xfe3c0000 0x0 0x20000>; 397 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>; 398 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 399 <&u2phy1>; 400 phys = <&u2phy1_host>; 401 phy-names = "usb"; 402 status = "disabled"; 403 }; 404 405 usb_host1_ohci: usb@fe3e0000 { 406 compatible = "generic-ohci"; 407 reg = <0x0 0xfe3e0000 0x0 0x20000>; 408 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>; 409 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>, 410 <&u2phy1>; 411 phys = <&u2phy1_host>; 412 phy-names = "usb"; 413 status = "disabled"; 414 }; 415 416 debug@fe430000 { 417 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 418 reg = <0 0xfe430000 0 0x1000>; 419 clocks = <&cru PCLK_COREDBG_L>; 420 clock-names = "apb_pclk"; 421 cpu = <&cpu_l0>; 422 }; 423 424 debug@fe432000 { 425 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 426 reg = <0 0xfe432000 0 0x1000>; 427 clocks = <&cru PCLK_COREDBG_L>; 428 clock-names = "apb_pclk"; 429 cpu = <&cpu_l1>; 430 }; 431 432 debug@fe434000 { 433 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 434 reg = <0 0xfe434000 0 0x1000>; 435 clocks = <&cru PCLK_COREDBG_L>; 436 clock-names = "apb_pclk"; 437 cpu = <&cpu_l2>; 438 }; 439 440 debug@fe436000 { 441 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 442 reg = <0 0xfe436000 0 0x1000>; 443 clocks = <&cru PCLK_COREDBG_L>; 444 clock-names = "apb_pclk"; 445 cpu = <&cpu_l3>; 446 }; 447 448 debug@fe610000 { 449 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 450 reg = <0 0xfe610000 0 0x1000>; 451 clocks = <&cru PCLK_COREDBG_B>; 452 clock-names = "apb_pclk"; 453 cpu = <&cpu_b0>; 454 }; 455 456 debug@fe710000 { 457 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 458 reg = <0 0xfe710000 0 0x1000>; 459 clocks = <&cru PCLK_COREDBG_B>; 460 clock-names = "apb_pclk"; 461 cpu = <&cpu_b1>; 462 }; 463 464 usbdrd3_0: usb@fe800000 { 465 compatible = "rockchip,rk3399-dwc3"; 466 #address-cells = <2>; 467 #size-cells = <2>; 468 ranges; 469 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>, 470 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 471 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 472 clock-names = "ref_clk", "suspend_clk", 473 "bus_clk", "aclk_usb3_rksoc_axi_perf", 474 "aclk_usb3", "grf_clk"; 475 resets = <&cru SRST_A_USB3_OTG0>; 476 reset-names = "usb3-otg"; 477 status = "disabled"; 478 479 usbdrd_dwc3_0: usb@fe800000 { 480 compatible = "snps,dwc3"; 481 reg = <0x0 0xfe800000 0x0 0x100000>; 482 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>; 483 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>, 484 <&cru SCLK_USB3OTG0_SUSPEND>; 485 clock-names = "ref", "bus_early", "suspend"; 486 dr_mode = "otg"; 487 phys = <&u2phy0_otg>, <&tcphy0_usb3>; 488 phy-names = "usb2-phy", "usb3-phy"; 489 phy_type = "utmi_wide"; 490 snps,dis_enblslpm_quirk; 491 snps,dis-u2-freeclk-exists-quirk; 492 snps,dis_u2_susphy_quirk; 493 snps,dis-del-phy-power-chg-quirk; 494 snps,dis-tx-ipgap-linecheck-quirk; 495 power-domains = <&power RK3399_PD_USB3>; 496 status = "disabled"; 497 }; 498 }; 499 500 usbdrd3_1: usb@fe900000 { 501 compatible = "rockchip,rk3399-dwc3"; 502 #address-cells = <2>; 503 #size-cells = <2>; 504 ranges; 505 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>, 506 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>, 507 <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>; 508 clock-names = "ref_clk", "suspend_clk", 509 "bus_clk", "aclk_usb3_rksoc_axi_perf", 510 "aclk_usb3", "grf_clk"; 511 resets = <&cru SRST_A_USB3_OTG1>; 512 reset-names = "usb3-otg"; 513 status = "disabled"; 514 515 usbdrd_dwc3_1: usb@fe900000 { 516 compatible = "snps,dwc3"; 517 reg = <0x0 0xfe900000 0x0 0x100000>; 518 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; 519 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>, 520 <&cru SCLK_USB3OTG1_SUSPEND>; 521 clock-names = "ref", "bus_early", "suspend"; 522 dr_mode = "otg"; 523 phys = <&u2phy1_otg>, <&tcphy1_usb3>; 524 phy-names = "usb2-phy", "usb3-phy"; 525 phy_type = "utmi_wide"; 526 snps,dis_enblslpm_quirk; 527 snps,dis-u2-freeclk-exists-quirk; 528 snps,dis_u2_susphy_quirk; 529 snps,dis-del-phy-power-chg-quirk; 530 snps,dis-tx-ipgap-linecheck-quirk; 531 power-domains = <&power RK3399_PD_USB3>; 532 status = "disabled"; 533 }; 534 }; 535 536 cdn_dp: dp@fec00000 { 537 compatible = "rockchip,rk3399-cdn-dp"; 538 reg = <0x0 0xfec00000 0x0 0x100000>; 539 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 540 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>; 541 assigned-clock-rates = <100000000>, <200000000>; 542 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>, 543 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>; 544 clock-names = "core-clk", "pclk", "spdif", "grf"; 545 phys = <&tcphy0_dp>, <&tcphy1_dp>; 546 power-domains = <&power RK3399_PD_HDCP>; 547 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>, 548 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>; 549 reset-names = "spdif", "dptx", "apb", "core"; 550 rockchip,grf = <&grf>; 551 #sound-dai-cells = <1>; 552 status = "disabled"; 553 554 ports { 555 dp_in: port { 556 #address-cells = <1>; 557 #size-cells = <0>; 558 559 dp_in_vopb: endpoint@0 { 560 reg = <0>; 561 remote-endpoint = <&vopb_out_dp>; 562 }; 563 564 dp_in_vopl: endpoint@1 { 565 reg = <1>; 566 remote-endpoint = <&vopl_out_dp>; 567 }; 568 }; 569 }; 570 }; 571 572 gic: interrupt-controller@fee00000 { 573 compatible = "arm,gic-v3"; 574 #interrupt-cells = <4>; 575 #address-cells = <2>; 576 #size-cells = <2>; 577 ranges; 578 interrupt-controller; 579 580 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */ 581 <0x0 0xfef00000 0 0xc0000>, /* GICR */ 582 <0x0 0xfff00000 0 0x10000>, /* GICC */ 583 <0x0 0xfff10000 0 0x10000>, /* GICH */ 584 <0x0 0xfff20000 0 0x10000>; /* GICV */ 585 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 586 its: msi-controller@fee20000 { 587 compatible = "arm,gic-v3-its"; 588 msi-controller; 589 #msi-cells = <1>; 590 reg = <0x0 0xfee20000 0x0 0x20000>; 591 }; 592 593 ppi-partitions { 594 ppi_cluster0: interrupt-partition-0 { 595 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>; 596 }; 597 598 ppi_cluster1: interrupt-partition-1 { 599 affinity = <&cpu_b0 &cpu_b1>; 600 }; 601 }; 602 }; 603 604 saradc: saradc@ff100000 { 605 compatible = "rockchip,rk3399-saradc"; 606 reg = <0x0 0xff100000 0x0 0x100>; 607 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>; 608 #io-channel-cells = <1>; 609 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 610 clock-names = "saradc", "apb_pclk"; 611 resets = <&cru SRST_P_SARADC>; 612 reset-names = "saradc-apb"; 613 status = "disabled"; 614 }; 615 616 crypto0: crypto@ff8b0000 { 617 compatible = "rockchip,rk3399-crypto"; 618 reg = <0x0 0xff8b0000 0x0 0x4000>; 619 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH 0>; 620 clocks = <&cru HCLK_M_CRYPTO0>, <&cru HCLK_S_CRYPTO0>, <&cru SCLK_CRYPTO0>; 621 clock-names = "hclk_master", "hclk_slave", "sclk"; 622 resets = <&cru SRST_CRYPTO0>, <&cru SRST_CRYPTO0_S>, <&cru SRST_CRYPTO0_M>; 623 reset-names = "master", "slave", "crypto-rst"; 624 }; 625 626 crypto1: crypto@ff8b8000 { 627 compatible = "rockchip,rk3399-crypto"; 628 reg = <0x0 0xff8b8000 0x0 0x4000>; 629 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 630 clocks = <&cru HCLK_M_CRYPTO1>, <&cru HCLK_S_CRYPTO1>, <&cru SCLK_CRYPTO1>; 631 clock-names = "hclk_master", "hclk_slave", "sclk"; 632 resets = <&cru SRST_CRYPTO1>, <&cru SRST_CRYPTO1_S>, <&cru SRST_CRYPTO1_M>; 633 reset-names = "master", "slave", "crypto-rst"; 634 }; 635 636 i2c1: i2c@ff110000 { 637 compatible = "rockchip,rk3399-i2c"; 638 reg = <0x0 0xff110000 0x0 0x1000>; 639 assigned-clocks = <&cru SCLK_I2C1>; 640 assigned-clock-rates = <200000000>; 641 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 642 clock-names = "i2c", "pclk"; 643 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>; 644 pinctrl-names = "default"; 645 pinctrl-0 = <&i2c1_xfer>; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 status = "disabled"; 649 }; 650 651 i2c2: i2c@ff120000 { 652 compatible = "rockchip,rk3399-i2c"; 653 reg = <0x0 0xff120000 0x0 0x1000>; 654 assigned-clocks = <&cru SCLK_I2C2>; 655 assigned-clock-rates = <200000000>; 656 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 657 clock-names = "i2c", "pclk"; 658 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>; 659 pinctrl-names = "default"; 660 pinctrl-0 = <&i2c2_xfer>; 661 #address-cells = <1>; 662 #size-cells = <0>; 663 status = "disabled"; 664 }; 665 666 i2c3: i2c@ff130000 { 667 compatible = "rockchip,rk3399-i2c"; 668 reg = <0x0 0xff130000 0x0 0x1000>; 669 assigned-clocks = <&cru SCLK_I2C3>; 670 assigned-clock-rates = <200000000>; 671 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 672 clock-names = "i2c", "pclk"; 673 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>; 674 pinctrl-names = "default"; 675 pinctrl-0 = <&i2c3_xfer>; 676 #address-cells = <1>; 677 #size-cells = <0>; 678 status = "disabled"; 679 }; 680 681 i2c5: i2c@ff140000 { 682 compatible = "rockchip,rk3399-i2c"; 683 reg = <0x0 0xff140000 0x0 0x1000>; 684 assigned-clocks = <&cru SCLK_I2C5>; 685 assigned-clock-rates = <200000000>; 686 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>; 687 clock-names = "i2c", "pclk"; 688 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>; 689 pinctrl-names = "default"; 690 pinctrl-0 = <&i2c5_xfer>; 691 #address-cells = <1>; 692 #size-cells = <0>; 693 status = "disabled"; 694 }; 695 696 i2c6: i2c@ff150000 { 697 compatible = "rockchip,rk3399-i2c"; 698 reg = <0x0 0xff150000 0x0 0x1000>; 699 assigned-clocks = <&cru SCLK_I2C6>; 700 assigned-clock-rates = <200000000>; 701 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>; 702 clock-names = "i2c", "pclk"; 703 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>; 704 pinctrl-names = "default"; 705 pinctrl-0 = <&i2c6_xfer>; 706 #address-cells = <1>; 707 #size-cells = <0>; 708 status = "disabled"; 709 }; 710 711 i2c7: i2c@ff160000 { 712 compatible = "rockchip,rk3399-i2c"; 713 reg = <0x0 0xff160000 0x0 0x1000>; 714 assigned-clocks = <&cru SCLK_I2C7>; 715 assigned-clock-rates = <200000000>; 716 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>; 717 clock-names = "i2c", "pclk"; 718 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>; 719 pinctrl-names = "default"; 720 pinctrl-0 = <&i2c7_xfer>; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 status = "disabled"; 724 }; 725 726 uart0: serial@ff180000 { 727 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 728 reg = <0x0 0xff180000 0x0 0x100>; 729 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 730 clock-names = "baudclk", "apb_pclk"; 731 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>; 732 reg-shift = <2>; 733 reg-io-width = <4>; 734 pinctrl-names = "default"; 735 pinctrl-0 = <&uart0_xfer>; 736 status = "disabled"; 737 }; 738 739 uart1: serial@ff190000 { 740 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 741 reg = <0x0 0xff190000 0x0 0x100>; 742 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 743 clock-names = "baudclk", "apb_pclk"; 744 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>; 745 reg-shift = <2>; 746 reg-io-width = <4>; 747 pinctrl-names = "default"; 748 pinctrl-0 = <&uart1_xfer>; 749 status = "disabled"; 750 }; 751 752 uart2: serial@ff1a0000 { 753 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 754 reg = <0x0 0xff1a0000 0x0 0x100>; 755 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 756 clock-names = "baudclk", "apb_pclk"; 757 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>; 758 reg-shift = <2>; 759 reg-io-width = <4>; 760 pinctrl-names = "default"; 761 pinctrl-0 = <&uart2c_xfer>; 762 status = "disabled"; 763 }; 764 765 uart3: serial@ff1b0000 { 766 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 767 reg = <0x0 0xff1b0000 0x0 0x100>; 768 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 769 clock-names = "baudclk", "apb_pclk"; 770 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>; 771 reg-shift = <2>; 772 reg-io-width = <4>; 773 pinctrl-names = "default"; 774 pinctrl-0 = <&uart3_xfer>; 775 status = "disabled"; 776 }; 777 778 spi0: spi@ff1c0000 { 779 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 780 reg = <0x0 0xff1c0000 0x0 0x1000>; 781 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 782 clock-names = "spiclk", "apb_pclk"; 783 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>; 784 dmas = <&dmac_peri 10>, <&dmac_peri 11>; 785 dma-names = "tx", "rx"; 786 pinctrl-names = "default"; 787 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 status = "disabled"; 791 }; 792 793 spi1: spi@ff1d0000 { 794 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 795 reg = <0x0 0xff1d0000 0x0 0x1000>; 796 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 797 clock-names = "spiclk", "apb_pclk"; 798 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>; 799 dmas = <&dmac_peri 12>, <&dmac_peri 13>; 800 dma-names = "tx", "rx"; 801 pinctrl-names = "default"; 802 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 803 #address-cells = <1>; 804 #size-cells = <0>; 805 status = "disabled"; 806 }; 807 808 spi2: spi@ff1e0000 { 809 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 810 reg = <0x0 0xff1e0000 0x0 0x1000>; 811 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 812 clock-names = "spiclk", "apb_pclk"; 813 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>; 814 dmas = <&dmac_peri 14>, <&dmac_peri 15>; 815 dma-names = "tx", "rx"; 816 pinctrl-names = "default"; 817 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 818 #address-cells = <1>; 819 #size-cells = <0>; 820 status = "disabled"; 821 }; 822 823 spi4: spi@ff1f0000 { 824 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 825 reg = <0x0 0xff1f0000 0x0 0x1000>; 826 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>; 827 clock-names = "spiclk", "apb_pclk"; 828 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>; 829 dmas = <&dmac_peri 18>, <&dmac_peri 19>; 830 dma-names = "tx", "rx"; 831 pinctrl-names = "default"; 832 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 status = "disabled"; 836 }; 837 838 spi5: spi@ff200000 { 839 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 840 reg = <0x0 0xff200000 0x0 0x1000>; 841 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>; 842 clock-names = "spiclk", "apb_pclk"; 843 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>; 844 dmas = <&dmac_bus 8>, <&dmac_bus 9>; 845 dma-names = "tx", "rx"; 846 pinctrl-names = "default"; 847 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>; 848 power-domains = <&power RK3399_PD_SDIOAUDIO>; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 status = "disabled"; 852 }; 853 854 thermal_zones: thermal-zones { 855 cpu_thermal: cpu-thermal { 856 polling-delay-passive = <100>; 857 polling-delay = <1000>; 858 859 thermal-sensors = <&tsadc 0>; 860 861 trips { 862 cpu_alert0: cpu_alert0 { 863 temperature = <70000>; 864 hysteresis = <2000>; 865 type = "passive"; 866 }; 867 cpu_alert1: cpu_alert1 { 868 temperature = <75000>; 869 hysteresis = <2000>; 870 type = "passive"; 871 }; 872 cpu_crit: cpu_crit { 873 temperature = <95000>; 874 hysteresis = <2000>; 875 type = "critical"; 876 }; 877 }; 878 879 cooling-maps { 880 map0 { 881 trip = <&cpu_alert0>; 882 cooling-device = 883 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 884 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 885 }; 886 map1 { 887 trip = <&cpu_alert1>; 888 cooling-device = 889 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 890 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 891 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 892 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 893 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 894 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 895 }; 896 }; 897 }; 898 899 gpu_thermal: gpu-thermal { 900 polling-delay-passive = <100>; 901 polling-delay = <1000>; 902 903 thermal-sensors = <&tsadc 1>; 904 905 trips { 906 gpu_alert0: gpu_alert0 { 907 temperature = <75000>; 908 hysteresis = <2000>; 909 type = "passive"; 910 }; 911 gpu_crit: gpu_crit { 912 temperature = <95000>; 913 hysteresis = <2000>; 914 type = "critical"; 915 }; 916 }; 917 918 cooling-maps { 919 map0 { 920 trip = <&gpu_alert0>; 921 cooling-device = 922 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 923 }; 924 }; 925 }; 926 }; 927 928 tsadc: tsadc@ff260000 { 929 compatible = "rockchip,rk3399-tsadc"; 930 reg = <0x0 0xff260000 0x0 0x100>; 931 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>; 932 assigned-clocks = <&cru SCLK_TSADC>; 933 assigned-clock-rates = <750000>; 934 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 935 clock-names = "tsadc", "apb_pclk"; 936 resets = <&cru SRST_TSADC>; 937 reset-names = "tsadc-apb"; 938 rockchip,grf = <&grf>; 939 rockchip,hw-tshut-temp = <95000>; 940 pinctrl-names = "init", "default", "sleep"; 941 pinctrl-0 = <&otp_pin>; 942 pinctrl-1 = <&otp_out>; 943 pinctrl-2 = <&otp_pin>; 944 #thermal-sensor-cells = <1>; 945 status = "disabled"; 946 }; 947 948 qos_emmc: qos@ffa58000 { 949 compatible = "rockchip,rk3399-qos", "syscon"; 950 reg = <0x0 0xffa58000 0x0 0x20>; 951 }; 952 953 qos_gmac: qos@ffa5c000 { 954 compatible = "rockchip,rk3399-qos", "syscon"; 955 reg = <0x0 0xffa5c000 0x0 0x20>; 956 }; 957 958 qos_pcie: qos@ffa60080 { 959 compatible = "rockchip,rk3399-qos", "syscon"; 960 reg = <0x0 0xffa60080 0x0 0x20>; 961 }; 962 963 qos_usb_host0: qos@ffa60100 { 964 compatible = "rockchip,rk3399-qos", "syscon"; 965 reg = <0x0 0xffa60100 0x0 0x20>; 966 }; 967 968 qos_usb_host1: qos@ffa60180 { 969 compatible = "rockchip,rk3399-qos", "syscon"; 970 reg = <0x0 0xffa60180 0x0 0x20>; 971 }; 972 973 qos_usb_otg0: qos@ffa70000 { 974 compatible = "rockchip,rk3399-qos", "syscon"; 975 reg = <0x0 0xffa70000 0x0 0x20>; 976 }; 977 978 qos_usb_otg1: qos@ffa70080 { 979 compatible = "rockchip,rk3399-qos", "syscon"; 980 reg = <0x0 0xffa70080 0x0 0x20>; 981 }; 982 983 qos_sd: qos@ffa74000 { 984 compatible = "rockchip,rk3399-qos", "syscon"; 985 reg = <0x0 0xffa74000 0x0 0x20>; 986 }; 987 988 qos_sdioaudio: qos@ffa76000 { 989 compatible = "rockchip,rk3399-qos", "syscon"; 990 reg = <0x0 0xffa76000 0x0 0x20>; 991 }; 992 993 qos_hdcp: qos@ffa90000 { 994 compatible = "rockchip,rk3399-qos", "syscon"; 995 reg = <0x0 0xffa90000 0x0 0x20>; 996 }; 997 998 qos_iep: qos@ffa98000 { 999 compatible = "rockchip,rk3399-qos", "syscon"; 1000 reg = <0x0 0xffa98000 0x0 0x20>; 1001 }; 1002 1003 qos_isp0_m0: qos@ffaa0000 { 1004 compatible = "rockchip,rk3399-qos", "syscon"; 1005 reg = <0x0 0xffaa0000 0x0 0x20>; 1006 }; 1007 1008 qos_isp0_m1: qos@ffaa0080 { 1009 compatible = "rockchip,rk3399-qos", "syscon"; 1010 reg = <0x0 0xffaa0080 0x0 0x20>; 1011 }; 1012 1013 qos_isp1_m0: qos@ffaa8000 { 1014 compatible = "rockchip,rk3399-qos", "syscon"; 1015 reg = <0x0 0xffaa8000 0x0 0x20>; 1016 }; 1017 1018 qos_isp1_m1: qos@ffaa8080 { 1019 compatible = "rockchip,rk3399-qos", "syscon"; 1020 reg = <0x0 0xffaa8080 0x0 0x20>; 1021 }; 1022 1023 qos_rga_r: qos@ffab0000 { 1024 compatible = "rockchip,rk3399-qos", "syscon"; 1025 reg = <0x0 0xffab0000 0x0 0x20>; 1026 }; 1027 1028 qos_rga_w: qos@ffab0080 { 1029 compatible = "rockchip,rk3399-qos", "syscon"; 1030 reg = <0x0 0xffab0080 0x0 0x20>; 1031 }; 1032 1033 qos_video_m0: qos@ffab8000 { 1034 compatible = "rockchip,rk3399-qos", "syscon"; 1035 reg = <0x0 0xffab8000 0x0 0x20>; 1036 }; 1037 1038 qos_video_m1_r: qos@ffac0000 { 1039 compatible = "rockchip,rk3399-qos", "syscon"; 1040 reg = <0x0 0xffac0000 0x0 0x20>; 1041 }; 1042 1043 qos_video_m1_w: qos@ffac0080 { 1044 compatible = "rockchip,rk3399-qos", "syscon"; 1045 reg = <0x0 0xffac0080 0x0 0x20>; 1046 }; 1047 1048 qos_vop_big_r: qos@ffac8000 { 1049 compatible = "rockchip,rk3399-qos", "syscon"; 1050 reg = <0x0 0xffac8000 0x0 0x20>; 1051 }; 1052 1053 qos_vop_big_w: qos@ffac8080 { 1054 compatible = "rockchip,rk3399-qos", "syscon"; 1055 reg = <0x0 0xffac8080 0x0 0x20>; 1056 }; 1057 1058 qos_vop_little: qos@ffad0000 { 1059 compatible = "rockchip,rk3399-qos", "syscon"; 1060 reg = <0x0 0xffad0000 0x0 0x20>; 1061 }; 1062 1063 qos_perihp: qos@ffad8080 { 1064 compatible = "rockchip,rk3399-qos", "syscon"; 1065 reg = <0x0 0xffad8080 0x0 0x20>; 1066 }; 1067 1068 qos_gpu: qos@ffae0000 { 1069 compatible = "rockchip,rk3399-qos", "syscon"; 1070 reg = <0x0 0xffae0000 0x0 0x20>; 1071 }; 1072 1073 pmu: power-management@ff310000 { 1074 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd"; 1075 reg = <0x0 0xff310000 0x0 0x1000>; 1076 1077 /* 1078 * Note: RK3399 supports 6 voltage domains including VD_CORE_L, 1079 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU. 1080 * Some of the power domains are grouped together for every 1081 * voltage domain. 1082 * The detail contents as below. 1083 */ 1084 power: power-controller { 1085 compatible = "rockchip,rk3399-power-controller"; 1086 #power-domain-cells = <1>; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 1090 /* These power domains are grouped by VD_CENTER */ 1091 power-domain@RK3399_PD_IEP { 1092 reg = <RK3399_PD_IEP>; 1093 clocks = <&cru ACLK_IEP>, 1094 <&cru HCLK_IEP>; 1095 pm_qos = <&qos_iep>; 1096 #power-domain-cells = <0>; 1097 }; 1098 power-domain@RK3399_PD_RGA { 1099 reg = <RK3399_PD_RGA>; 1100 clocks = <&cru ACLK_RGA>, 1101 <&cru HCLK_RGA>; 1102 pm_qos = <&qos_rga_r>, 1103 <&qos_rga_w>; 1104 #power-domain-cells = <0>; 1105 }; 1106 power-domain@RK3399_PD_VCODEC { 1107 reg = <RK3399_PD_VCODEC>; 1108 clocks = <&cru ACLK_VCODEC>, 1109 <&cru HCLK_VCODEC>; 1110 pm_qos = <&qos_video_m0>; 1111 #power-domain-cells = <0>; 1112 }; 1113 power-domain@RK3399_PD_VDU { 1114 reg = <RK3399_PD_VDU>; 1115 clocks = <&cru ACLK_VDU>, 1116 <&cru HCLK_VDU>, 1117 <&cru SCLK_VDU_CA>, 1118 <&cru SCLK_VDU_CORE>; 1119 pm_qos = <&qos_video_m1_r>, 1120 <&qos_video_m1_w>; 1121 #power-domain-cells = <0>; 1122 }; 1123 1124 /* These power domains are grouped by VD_GPU */ 1125 power-domain@RK3399_PD_GPU { 1126 reg = <RK3399_PD_GPU>; 1127 clocks = <&cru ACLK_GPU>; 1128 pm_qos = <&qos_gpu>; 1129 #power-domain-cells = <0>; 1130 }; 1131 1132 /* These power domains are grouped by VD_LOGIC */ 1133 power-domain@RK3399_PD_EDP { 1134 reg = <RK3399_PD_EDP>; 1135 clocks = <&cru PCLK_EDP_CTRL>; 1136 #power-domain-cells = <0>; 1137 }; 1138 power-domain@RK3399_PD_EMMC { 1139 reg = <RK3399_PD_EMMC>; 1140 clocks = <&cru ACLK_EMMC>; 1141 pm_qos = <&qos_emmc>; 1142 #power-domain-cells = <0>; 1143 }; 1144 power-domain@RK3399_PD_GMAC { 1145 reg = <RK3399_PD_GMAC>; 1146 clocks = <&cru ACLK_GMAC>, 1147 <&cru PCLK_GMAC>; 1148 pm_qos = <&qos_gmac>; 1149 #power-domain-cells = <0>; 1150 }; 1151 power-domain@RK3399_PD_SD { 1152 reg = <RK3399_PD_SD>; 1153 clocks = <&cru HCLK_SDMMC>, 1154 <&cru SCLK_SDMMC>; 1155 pm_qos = <&qos_sd>; 1156 #power-domain-cells = <0>; 1157 }; 1158 power-domain@RK3399_PD_SDIOAUDIO { 1159 reg = <RK3399_PD_SDIOAUDIO>; 1160 clocks = <&cru HCLK_SDIO>; 1161 pm_qos = <&qos_sdioaudio>; 1162 #power-domain-cells = <0>; 1163 }; 1164 power-domain@RK3399_PD_TCPD0 { 1165 reg = <RK3399_PD_TCPD0>; 1166 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1167 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1168 #power-domain-cells = <0>; 1169 }; 1170 power-domain@RK3399_PD_TCPD1 { 1171 reg = <RK3399_PD_TCPD1>; 1172 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1173 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1174 #power-domain-cells = <0>; 1175 }; 1176 power-domain@RK3399_PD_USB3 { 1177 reg = <RK3399_PD_USB3>; 1178 clocks = <&cru ACLK_USB3>; 1179 pm_qos = <&qos_usb_otg0>, 1180 <&qos_usb_otg1>; 1181 #power-domain-cells = <0>; 1182 }; 1183 power-domain@RK3399_PD_VIO { 1184 reg = <RK3399_PD_VIO>; 1185 #power-domain-cells = <1>; 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 1189 power-domain@RK3399_PD_HDCP { 1190 reg = <RK3399_PD_HDCP>; 1191 clocks = <&cru ACLK_HDCP>, 1192 <&cru HCLK_HDCP>, 1193 <&cru PCLK_HDCP>; 1194 pm_qos = <&qos_hdcp>; 1195 #power-domain-cells = <0>; 1196 }; 1197 power-domain@RK3399_PD_ISP0 { 1198 reg = <RK3399_PD_ISP0>; 1199 clocks = <&cru ACLK_ISP0>, 1200 <&cru HCLK_ISP0>; 1201 pm_qos = <&qos_isp0_m0>, 1202 <&qos_isp0_m1>; 1203 #power-domain-cells = <0>; 1204 }; 1205 power-domain@RK3399_PD_ISP1 { 1206 reg = <RK3399_PD_ISP1>; 1207 clocks = <&cru ACLK_ISP1>, 1208 <&cru HCLK_ISP1>; 1209 pm_qos = <&qos_isp1_m0>, 1210 <&qos_isp1_m1>; 1211 #power-domain-cells = <0>; 1212 }; 1213 power-domain@RK3399_PD_VO { 1214 reg = <RK3399_PD_VO>; 1215 #power-domain-cells = <1>; 1216 #address-cells = <1>; 1217 #size-cells = <0>; 1218 1219 power-domain@RK3399_PD_VOPB { 1220 reg = <RK3399_PD_VOPB>; 1221 clocks = <&cru ACLK_VOP0>, 1222 <&cru HCLK_VOP0>; 1223 pm_qos = <&qos_vop_big_r>, 1224 <&qos_vop_big_w>; 1225 #power-domain-cells = <0>; 1226 }; 1227 power-domain@RK3399_PD_VOPL { 1228 reg = <RK3399_PD_VOPL>; 1229 clocks = <&cru ACLK_VOP1>, 1230 <&cru HCLK_VOP1>; 1231 pm_qos = <&qos_vop_little>; 1232 #power-domain-cells = <0>; 1233 }; 1234 }; 1235 }; 1236 }; 1237 }; 1238 1239 pmugrf: syscon@ff320000 { 1240 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd"; 1241 reg = <0x0 0xff320000 0x0 0x1000>; 1242 1243 pmu_io_domains: io-domains { 1244 compatible = "rockchip,rk3399-pmu-io-voltage-domain"; 1245 status = "disabled"; 1246 }; 1247 }; 1248 1249 spi3: spi@ff350000 { 1250 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi"; 1251 reg = <0x0 0xff350000 0x0 0x1000>; 1252 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>; 1253 clock-names = "spiclk", "apb_pclk"; 1254 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>; 1255 pinctrl-names = "default"; 1256 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>; 1257 #address-cells = <1>; 1258 #size-cells = <0>; 1259 status = "disabled"; 1260 }; 1261 1262 uart4: serial@ff370000 { 1263 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart"; 1264 reg = <0x0 0xff370000 0x0 0x100>; 1265 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>; 1266 clock-names = "baudclk", "apb_pclk"; 1267 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>; 1268 reg-shift = <2>; 1269 reg-io-width = <4>; 1270 pinctrl-names = "default"; 1271 pinctrl-0 = <&uart4_xfer>; 1272 status = "disabled"; 1273 }; 1274 1275 i2c0: i2c@ff3c0000 { 1276 compatible = "rockchip,rk3399-i2c"; 1277 reg = <0x0 0xff3c0000 0x0 0x1000>; 1278 assigned-clocks = <&pmucru SCLK_I2C0_PMU>; 1279 assigned-clock-rates = <200000000>; 1280 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>; 1281 clock-names = "i2c", "pclk"; 1282 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>; 1283 pinctrl-names = "default"; 1284 pinctrl-0 = <&i2c0_xfer>; 1285 #address-cells = <1>; 1286 #size-cells = <0>; 1287 status = "disabled"; 1288 }; 1289 1290 i2c4: i2c@ff3d0000 { 1291 compatible = "rockchip,rk3399-i2c"; 1292 reg = <0x0 0xff3d0000 0x0 0x1000>; 1293 assigned-clocks = <&pmucru SCLK_I2C4_PMU>; 1294 assigned-clock-rates = <200000000>; 1295 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>; 1296 clock-names = "i2c", "pclk"; 1297 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>; 1298 pinctrl-names = "default"; 1299 pinctrl-0 = <&i2c4_xfer>; 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 status = "disabled"; 1303 }; 1304 1305 i2c8: i2c@ff3e0000 { 1306 compatible = "rockchip,rk3399-i2c"; 1307 reg = <0x0 0xff3e0000 0x0 0x1000>; 1308 assigned-clocks = <&pmucru SCLK_I2C8_PMU>; 1309 assigned-clock-rates = <200000000>; 1310 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>; 1311 clock-names = "i2c", "pclk"; 1312 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>; 1313 pinctrl-names = "default"; 1314 pinctrl-0 = <&i2c8_xfer>; 1315 #address-cells = <1>; 1316 #size-cells = <0>; 1317 status = "disabled"; 1318 }; 1319 1320 pwm0: pwm@ff420000 { 1321 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1322 reg = <0x0 0xff420000 0x0 0x10>; 1323 #pwm-cells = <3>; 1324 pinctrl-names = "default"; 1325 pinctrl-0 = <&pwm0_pin>; 1326 clocks = <&pmucru PCLK_RKPWM_PMU>; 1327 status = "disabled"; 1328 }; 1329 1330 pwm1: pwm@ff420010 { 1331 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1332 reg = <0x0 0xff420010 0x0 0x10>; 1333 #pwm-cells = <3>; 1334 pinctrl-names = "default"; 1335 pinctrl-0 = <&pwm1_pin>; 1336 clocks = <&pmucru PCLK_RKPWM_PMU>; 1337 status = "disabled"; 1338 }; 1339 1340 pwm2: pwm@ff420020 { 1341 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1342 reg = <0x0 0xff420020 0x0 0x10>; 1343 #pwm-cells = <3>; 1344 pinctrl-names = "default"; 1345 pinctrl-0 = <&pwm2_pin>; 1346 clocks = <&pmucru PCLK_RKPWM_PMU>; 1347 status = "disabled"; 1348 }; 1349 1350 pwm3: pwm@ff420030 { 1351 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm"; 1352 reg = <0x0 0xff420030 0x0 0x10>; 1353 #pwm-cells = <3>; 1354 pinctrl-names = "default"; 1355 pinctrl-0 = <&pwm3a_pin>; 1356 clocks = <&pmucru PCLK_RKPWM_PMU>; 1357 status = "disabled"; 1358 }; 1359 1360 dfi: dfi@ff630000 { 1361 reg = <0x00 0xff630000 0x00 0x4000>; 1362 compatible = "rockchip,rk3399-dfi"; 1363 rockchip,pmu = <&pmugrf>; 1364 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1365 clocks = <&cru PCLK_DDR_MON>; 1366 clock-names = "pclk_ddr_mon"; 1367 }; 1368 1369 vpu: video-codec@ff650000 { 1370 compatible = "rockchip,rk3399-vpu"; 1371 reg = <0x0 0xff650000 0x0 0x800>; 1372 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>, 1373 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>; 1374 interrupt-names = "vepu", "vdpu"; 1375 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1376 clock-names = "aclk", "hclk"; 1377 iommus = <&vpu_mmu>; 1378 power-domains = <&power RK3399_PD_VCODEC>; 1379 }; 1380 1381 vpu_mmu: iommu@ff650800 { 1382 compatible = "rockchip,iommu"; 1383 reg = <0x0 0xff650800 0x0 0x40>; 1384 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; 1385 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>; 1386 clock-names = "aclk", "iface"; 1387 #iommu-cells = <0>; 1388 power-domains = <&power RK3399_PD_VCODEC>; 1389 }; 1390 1391 vdec: video-codec@ff660000 { 1392 compatible = "rockchip,rk3399-vdec"; 1393 reg = <0x0 0xff660000 0x0 0x480>; 1394 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>; 1395 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>, 1396 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>; 1397 clock-names = "axi", "ahb", "cabac", "core"; 1398 iommus = <&vdec_mmu>; 1399 power-domains = <&power RK3399_PD_VDU>; 1400 }; 1401 1402 vdec_mmu: iommu@ff660480 { 1403 compatible = "rockchip,iommu"; 1404 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>; 1405 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>; 1406 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>; 1407 clock-names = "aclk", "iface"; 1408 power-domains = <&power RK3399_PD_VDU>; 1409 #iommu-cells = <0>; 1410 }; 1411 1412 iep_mmu: iommu@ff670800 { 1413 compatible = "rockchip,iommu"; 1414 reg = <0x0 0xff670800 0x0 0x40>; 1415 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>; 1416 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 1417 clock-names = "aclk", "iface"; 1418 #iommu-cells = <0>; 1419 status = "disabled"; 1420 }; 1421 1422 rga: rga@ff680000 { 1423 compatible = "rockchip,rk3399-rga"; 1424 reg = <0x0 0xff680000 0x0 0x10000>; 1425 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>; 1426 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>; 1427 clock-names = "aclk", "hclk", "sclk"; 1428 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>; 1429 reset-names = "core", "axi", "ahb"; 1430 power-domains = <&power RK3399_PD_RGA>; 1431 }; 1432 1433 efuse0: efuse@ff690000 { 1434 compatible = "rockchip,rk3399-efuse"; 1435 reg = <0x0 0xff690000 0x0 0x80>; 1436 #address-cells = <1>; 1437 #size-cells = <1>; 1438 clocks = <&cru PCLK_EFUSE1024NS>; 1439 clock-names = "pclk_efuse"; 1440 1441 /* Data cells */ 1442 cpu_id: cpu-id@7 { 1443 reg = <0x07 0x10>; 1444 }; 1445 cpub_leakage: cpu-leakage@17 { 1446 reg = <0x17 0x1>; 1447 }; 1448 gpu_leakage: gpu-leakage@18 { 1449 reg = <0x18 0x1>; 1450 }; 1451 center_leakage: center-leakage@19 { 1452 reg = <0x19 0x1>; 1453 }; 1454 cpul_leakage: cpu-leakage@1a { 1455 reg = <0x1a 0x1>; 1456 }; 1457 logic_leakage: logic-leakage@1b { 1458 reg = <0x1b 0x1>; 1459 }; 1460 wafer_info: wafer-info@1c { 1461 reg = <0x1c 0x1>; 1462 }; 1463 }; 1464 1465 dmac_bus: dma-controller@ff6d0000 { 1466 compatible = "arm,pl330", "arm,primecell"; 1467 reg = <0x0 0xff6d0000 0x0 0x4000>; 1468 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>, 1469 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>; 1470 #dma-cells = <1>; 1471 arm,pl330-periph-burst; 1472 clocks = <&cru ACLK_DMAC0_PERILP>; 1473 clock-names = "apb_pclk"; 1474 }; 1475 1476 dmac_peri: dma-controller@ff6e0000 { 1477 compatible = "arm,pl330", "arm,primecell"; 1478 reg = <0x0 0xff6e0000 0x0 0x4000>; 1479 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>, 1480 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>; 1481 #dma-cells = <1>; 1482 arm,pl330-periph-burst; 1483 clocks = <&cru ACLK_DMAC1_PERILP>; 1484 clock-names = "apb_pclk"; 1485 }; 1486 1487 pmucru: clock-controller@ff750000 { 1488 compatible = "rockchip,rk3399-pmucru"; 1489 reg = <0x0 0xff750000 0x0 0x1000>; 1490 clocks = <&xin24m>; 1491 clock-names = "xin24m"; 1492 rockchip,grf = <&pmugrf>; 1493 #clock-cells = <1>; 1494 #reset-cells = <1>; 1495 assigned-clocks = <&pmucru PLL_PPLL>; 1496 assigned-clock-rates = <676000000>; 1497 }; 1498 1499 cru: clock-controller@ff760000 { 1500 compatible = "rockchip,rk3399-cru"; 1501 reg = <0x0 0xff760000 0x0 0x1000>; 1502 clocks = <&xin24m>; 1503 clock-names = "xin24m"; 1504 rockchip,grf = <&grf>; 1505 #clock-cells = <1>; 1506 #reset-cells = <1>; 1507 assigned-clocks = 1508 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 1509 <&cru PLL_NPLL>, 1510 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 1511 <&cru PCLK_PERIHP>, 1512 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 1513 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 1514 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 1515 <&cru ACLK_VIO>, <&cru ACLK_HDCP>, 1516 <&cru ACLK_GIC_PRE>, 1517 <&cru PCLK_DDR>, 1518 <&cru ACLK_VDU>; 1519 assigned-clock-rates = 1520 <594000000>, <800000000>, 1521 <1000000000>, 1522 <150000000>, <75000000>, 1523 <37500000>, 1524 <100000000>, <100000000>, 1525 <50000000>, <600000000>, 1526 <100000000>, <50000000>, 1527 <400000000>, <400000000>, 1528 <200000000>, 1529 <200000000>, 1530 <400000000>; 1531 }; 1532 1533 grf: syscon@ff770000 { 1534 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd"; 1535 reg = <0x0 0xff770000 0x0 0x10000>; 1536 #address-cells = <1>; 1537 #size-cells = <1>; 1538 1539 io_domains: io-domains { 1540 compatible = "rockchip,rk3399-io-voltage-domain"; 1541 status = "disabled"; 1542 }; 1543 1544 mipi_dphy_rx0: mipi-dphy-rx0 { 1545 compatible = "rockchip,rk3399-mipi-dphy-rx0"; 1546 clocks = <&cru SCLK_MIPIDPHY_REF>, 1547 <&cru SCLK_DPHY_RX0_CFG>, 1548 <&cru PCLK_VIO_GRF>; 1549 clock-names = "dphy-ref", "dphy-cfg", "grf"; 1550 power-domains = <&power RK3399_PD_VIO>; 1551 #phy-cells = <0>; 1552 status = "disabled"; 1553 }; 1554 1555 u2phy0: usb2phy@e450 { 1556 compatible = "rockchip,rk3399-usb2phy"; 1557 reg = <0xe450 0x10>; 1558 clocks = <&cru SCLK_USB2PHY0_REF>; 1559 clock-names = "phyclk"; 1560 #clock-cells = <0>; 1561 clock-output-names = "clk_usbphy0_480m"; 1562 status = "disabled"; 1563 1564 u2phy0_host: host-port { 1565 #phy-cells = <0>; 1566 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>; 1567 interrupt-names = "linestate"; 1568 status = "disabled"; 1569 }; 1570 1571 u2phy0_otg: otg-port { 1572 #phy-cells = <0>; 1573 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>, 1574 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>, 1575 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>; 1576 interrupt-names = "otg-bvalid", "otg-id", 1577 "linestate"; 1578 status = "disabled"; 1579 }; 1580 }; 1581 1582 u2phy1: usb2phy@e460 { 1583 compatible = "rockchip,rk3399-usb2phy"; 1584 reg = <0xe460 0x10>; 1585 clocks = <&cru SCLK_USB2PHY1_REF>; 1586 clock-names = "phyclk"; 1587 #clock-cells = <0>; 1588 clock-output-names = "clk_usbphy1_480m"; 1589 status = "disabled"; 1590 1591 u2phy1_host: host-port { 1592 #phy-cells = <0>; 1593 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>; 1594 interrupt-names = "linestate"; 1595 status = "disabled"; 1596 }; 1597 1598 u2phy1_otg: otg-port { 1599 #phy-cells = <0>; 1600 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>, 1601 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>, 1602 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>; 1603 interrupt-names = "otg-bvalid", "otg-id", 1604 "linestate"; 1605 status = "disabled"; 1606 }; 1607 }; 1608 1609 emmc_phy: phy@f780 { 1610 compatible = "rockchip,rk3399-emmc-phy"; 1611 reg = <0xf780 0x24>; 1612 clocks = <&sdhci>; 1613 clock-names = "emmcclk"; 1614 drive-impedance-ohm = <50>; 1615 #phy-cells = <0>; 1616 status = "disabled"; 1617 }; 1618 1619 pcie_phy: pcie-phy { 1620 compatible = "rockchip,rk3399-pcie-phy"; 1621 clocks = <&cru SCLK_PCIEPHY_REF>; 1622 clock-names = "refclk"; 1623 #phy-cells = <1>; 1624 resets = <&cru SRST_PCIEPHY>; 1625 reset-names = "phy"; 1626 status = "disabled"; 1627 }; 1628 }; 1629 1630 tcphy0: phy@ff7c0000 { 1631 compatible = "rockchip,rk3399-typec-phy"; 1632 reg = <0x0 0xff7c0000 0x0 0x40000>; 1633 clocks = <&cru SCLK_UPHY0_TCPDCORE>, 1634 <&cru SCLK_UPHY0_TCPDPHY_REF>; 1635 clock-names = "tcpdcore", "tcpdphy-ref"; 1636 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>; 1637 assigned-clock-rates = <50000000>; 1638 power-domains = <&power RK3399_PD_TCPD0>; 1639 resets = <&cru SRST_UPHY0>, 1640 <&cru SRST_UPHY0_PIPE_L00>, 1641 <&cru SRST_P_UPHY0_TCPHY>; 1642 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1643 rockchip,grf = <&grf>; 1644 status = "disabled"; 1645 1646 tcphy0_dp: dp-port { 1647 #phy-cells = <0>; 1648 }; 1649 1650 tcphy0_usb3: usb3-port { 1651 #phy-cells = <0>; 1652 }; 1653 }; 1654 1655 tcphy1: phy@ff800000 { 1656 compatible = "rockchip,rk3399-typec-phy"; 1657 reg = <0x0 0xff800000 0x0 0x40000>; 1658 clocks = <&cru SCLK_UPHY1_TCPDCORE>, 1659 <&cru SCLK_UPHY1_TCPDPHY_REF>; 1660 clock-names = "tcpdcore", "tcpdphy-ref"; 1661 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>; 1662 assigned-clock-rates = <50000000>; 1663 power-domains = <&power RK3399_PD_TCPD1>; 1664 resets = <&cru SRST_UPHY1>, 1665 <&cru SRST_UPHY1_PIPE_L00>, 1666 <&cru SRST_P_UPHY1_TCPHY>; 1667 reset-names = "uphy", "uphy-pipe", "uphy-tcphy"; 1668 rockchip,grf = <&grf>; 1669 status = "disabled"; 1670 1671 tcphy1_dp: dp-port { 1672 #phy-cells = <0>; 1673 }; 1674 1675 tcphy1_usb3: usb3-port { 1676 #phy-cells = <0>; 1677 }; 1678 }; 1679 1680 watchdog@ff848000 { 1681 compatible = "rockchip,rk3399-wdt", "snps,dw-wdt"; 1682 reg = <0x0 0xff848000 0x0 0x100>; 1683 clocks = <&cru PCLK_WDT>; 1684 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>; 1685 }; 1686 1687 rktimer: rktimer@ff850000 { 1688 compatible = "rockchip,rk3399-timer"; 1689 reg = <0x0 0xff850000 0x0 0x1000>; 1690 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>; 1691 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>; 1692 clock-names = "pclk", "timer"; 1693 }; 1694 1695 spdif: spdif@ff870000 { 1696 compatible = "rockchip,rk3399-spdif"; 1697 reg = <0x0 0xff870000 0x0 0x1000>; 1698 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>; 1699 dmas = <&dmac_bus 7>; 1700 dma-names = "tx"; 1701 clock-names = "mclk", "hclk"; 1702 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 1703 pinctrl-names = "default"; 1704 pinctrl-0 = <&spdif_bus>; 1705 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1706 #sound-dai-cells = <0>; 1707 status = "disabled"; 1708 }; 1709 1710 i2s0: i2s@ff880000 { 1711 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1712 reg = <0x0 0xff880000 0x0 0x1000>; 1713 rockchip,grf = <&grf>; 1714 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>; 1715 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 1716 dma-names = "tx", "rx"; 1717 clock-names = "i2s_clk", "i2s_hclk"; 1718 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>; 1719 pinctrl-names = "bclk_on", "bclk_off"; 1720 pinctrl-0 = <&i2s0_8ch_bus>; 1721 pinctrl-1 = <&i2s0_8ch_bus_bclk_off>; 1722 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1723 #sound-dai-cells = <0>; 1724 status = "disabled"; 1725 }; 1726 1727 i2s1: i2s@ff890000 { 1728 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1729 reg = <0x0 0xff890000 0x0 0x1000>; 1730 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>; 1731 dmas = <&dmac_bus 2>, <&dmac_bus 3>; 1732 dma-names = "tx", "rx"; 1733 clock-names = "i2s_clk", "i2s_hclk"; 1734 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>; 1735 pinctrl-names = "default"; 1736 pinctrl-0 = <&i2s1_2ch_bus>; 1737 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1738 #sound-dai-cells = <0>; 1739 status = "disabled"; 1740 }; 1741 1742 i2s2: i2s@ff8a0000 { 1743 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s"; 1744 reg = <0x0 0xff8a0000 0x0 0x1000>; 1745 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>; 1746 dmas = <&dmac_bus 4>, <&dmac_bus 5>; 1747 dma-names = "tx", "rx"; 1748 clock-names = "i2s_clk", "i2s_hclk"; 1749 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>; 1750 power-domains = <&power RK3399_PD_SDIOAUDIO>; 1751 #sound-dai-cells = <0>; 1752 status = "disabled"; 1753 }; 1754 1755 vopl: vop@ff8f0000 { 1756 compatible = "rockchip,rk3399-vop-lit"; 1757 reg = <0x0 0xff8f0000 0x0 0x2000>, <0x0 0xff8f2000 0x0 0x400>; 1758 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1759 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1760 assigned-clock-rates = <400000000>, <100000000>; 1761 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>; 1762 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1763 iommus = <&vopl_mmu>; 1764 power-domains = <&power RK3399_PD_VOPL>; 1765 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>; 1766 reset-names = "axi", "ahb", "dclk"; 1767 status = "disabled"; 1768 1769 vopl_out: port { 1770 #address-cells = <1>; 1771 #size-cells = <0>; 1772 1773 vopl_out_mipi: endpoint@0 { 1774 reg = <0>; 1775 remote-endpoint = <&mipi_in_vopl>; 1776 }; 1777 1778 vopl_out_edp: endpoint@1 { 1779 reg = <1>; 1780 remote-endpoint = <&edp_in_vopl>; 1781 }; 1782 1783 vopl_out_hdmi: endpoint@2 { 1784 reg = <2>; 1785 remote-endpoint = <&hdmi_in_vopl>; 1786 }; 1787 1788 vopl_out_mipi1: endpoint@3 { 1789 reg = <3>; 1790 remote-endpoint = <&mipi1_in_vopl>; 1791 }; 1792 1793 vopl_out_dp: endpoint@4 { 1794 reg = <4>; 1795 remote-endpoint = <&dp_in_vopl>; 1796 }; 1797 }; 1798 }; 1799 1800 vopl_mmu: iommu@ff8f3f00 { 1801 compatible = "rockchip,iommu"; 1802 reg = <0x0 0xff8f3f00 0x0 0x100>; 1803 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>; 1804 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>; 1805 clock-names = "aclk", "iface"; 1806 power-domains = <&power RK3399_PD_VOPL>; 1807 #iommu-cells = <0>; 1808 status = "disabled"; 1809 }; 1810 1811 vopb: vop@ff900000 { 1812 compatible = "rockchip,rk3399-vop-big"; 1813 reg = <0x0 0xff900000 0x0 0x2000>, <0x0 0xff902000 0x0 0x1000>; 1814 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1815 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1816 assigned-clock-rates = <400000000>, <100000000>; 1817 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>; 1818 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1819 iommus = <&vopb_mmu>; 1820 power-domains = <&power RK3399_PD_VOPB>; 1821 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>; 1822 reset-names = "axi", "ahb", "dclk"; 1823 status = "disabled"; 1824 1825 vopb_out: port { 1826 #address-cells = <1>; 1827 #size-cells = <0>; 1828 1829 vopb_out_edp: endpoint@0 { 1830 reg = <0>; 1831 remote-endpoint = <&edp_in_vopb>; 1832 }; 1833 1834 vopb_out_mipi: endpoint@1 { 1835 reg = <1>; 1836 remote-endpoint = <&mipi_in_vopb>; 1837 }; 1838 1839 vopb_out_hdmi: endpoint@2 { 1840 reg = <2>; 1841 remote-endpoint = <&hdmi_in_vopb>; 1842 }; 1843 1844 vopb_out_mipi1: endpoint@3 { 1845 reg = <3>; 1846 remote-endpoint = <&mipi1_in_vopb>; 1847 }; 1848 1849 vopb_out_dp: endpoint@4 { 1850 reg = <4>; 1851 remote-endpoint = <&dp_in_vopb>; 1852 }; 1853 }; 1854 }; 1855 1856 vopb_mmu: iommu@ff903f00 { 1857 compatible = "rockchip,iommu"; 1858 reg = <0x0 0xff903f00 0x0 0x100>; 1859 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>; 1860 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>; 1861 clock-names = "aclk", "iface"; 1862 power-domains = <&power RK3399_PD_VOPB>; 1863 #iommu-cells = <0>; 1864 status = "disabled"; 1865 }; 1866 1867 isp0: isp0@ff910000 { 1868 compatible = "rockchip,rk3399-cif-isp"; 1869 reg = <0x0 0xff910000 0x0 0x4000>; 1870 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1871 clocks = <&cru SCLK_ISP0>, 1872 <&cru ACLK_ISP0_WRAPPER>, 1873 <&cru HCLK_ISP0_WRAPPER>; 1874 clock-names = "isp", "aclk", "hclk"; 1875 iommus = <&isp0_mmu>; 1876 phys = <&mipi_dphy_rx0>; 1877 phy-names = "dphy"; 1878 power-domains = <&power RK3399_PD_ISP0>; 1879 status = "disabled"; 1880 1881 ports { 1882 #address-cells = <1>; 1883 #size-cells = <0>; 1884 1885 port@0 { 1886 reg = <0>; 1887 #address-cells = <1>; 1888 #size-cells = <0>; 1889 }; 1890 }; 1891 }; 1892 1893 isp0_mmu: iommu@ff914000 { 1894 compatible = "rockchip,iommu"; 1895 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>; 1896 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>; 1897 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>; 1898 clock-names = "aclk", "iface"; 1899 #iommu-cells = <0>; 1900 power-domains = <&power RK3399_PD_ISP0>; 1901 rockchip,disable-mmu-reset; 1902 }; 1903 1904 isp1: isp1@ff920000 { 1905 compatible = "rockchip,rk3399-cif-isp"; 1906 reg = <0x0 0xff920000 0x0 0x4000>; 1907 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1908 clocks = <&cru SCLK_ISP1>, 1909 <&cru ACLK_ISP1_WRAPPER>, 1910 <&cru HCLK_ISP1_WRAPPER>; 1911 clock-names = "isp", "aclk", "hclk"; 1912 iommus = <&isp1_mmu>; 1913 phys = <&mipi_dsi1>; 1914 phy-names = "dphy"; 1915 power-domains = <&power RK3399_PD_ISP1>; 1916 status = "disabled"; 1917 1918 ports { 1919 #address-cells = <1>; 1920 #size-cells = <0>; 1921 1922 port@0 { 1923 reg = <0>; 1924 #address-cells = <1>; 1925 #size-cells = <0>; 1926 }; 1927 }; 1928 }; 1929 1930 isp1_mmu: iommu@ff924000 { 1931 compatible = "rockchip,iommu"; 1932 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>; 1933 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>; 1934 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>; 1935 clock-names = "aclk", "iface"; 1936 #iommu-cells = <0>; 1937 power-domains = <&power RK3399_PD_ISP1>; 1938 rockchip,disable-mmu-reset; 1939 }; 1940 1941 hdmi_sound: hdmi-sound { 1942 compatible = "simple-audio-card"; 1943 simple-audio-card,format = "i2s"; 1944 simple-audio-card,mclk-fs = <256>; 1945 simple-audio-card,name = "hdmi-sound"; 1946 status = "disabled"; 1947 1948 simple-audio-card,cpu { 1949 sound-dai = <&i2s2>; 1950 }; 1951 simple-audio-card,codec { 1952 sound-dai = <&hdmi>; 1953 }; 1954 }; 1955 1956 hdmi: hdmi@ff940000 { 1957 compatible = "rockchip,rk3399-dw-hdmi"; 1958 reg = <0x0 0xff940000 0x0 0x20000>; 1959 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; 1960 clocks = <&cru PCLK_HDMI_CTRL>, 1961 <&cru SCLK_HDMI_SFR>, 1962 <&cru SCLK_HDMI_CEC>, 1963 <&cru PCLK_VIO_GRF>, 1964 <&cru PLL_VPLL>; 1965 clock-names = "iahb", "isfr", "cec", "grf", "ref"; 1966 power-domains = <&power RK3399_PD_HDCP>; 1967 reg-io-width = <4>; 1968 rockchip,grf = <&grf>; 1969 #sound-dai-cells = <0>; 1970 status = "disabled"; 1971 1972 ports { 1973 hdmi_in: port { 1974 #address-cells = <1>; 1975 #size-cells = <0>; 1976 1977 hdmi_in_vopb: endpoint@0 { 1978 reg = <0>; 1979 remote-endpoint = <&vopb_out_hdmi>; 1980 }; 1981 hdmi_in_vopl: endpoint@1 { 1982 reg = <1>; 1983 remote-endpoint = <&vopl_out_hdmi>; 1984 }; 1985 }; 1986 }; 1987 }; 1988 1989 mipi_dsi: dsi@ff960000 { 1990 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 1991 reg = <0x0 0xff960000 0x0 0x8000>; 1992 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>; 1993 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>, 1994 <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>; 1995 clock-names = "ref", "pclk", "phy_cfg", "grf"; 1996 power-domains = <&power RK3399_PD_VIO>; 1997 resets = <&cru SRST_P_MIPI_DSI0>; 1998 reset-names = "apb"; 1999 rockchip,grf = <&grf>; 2000 #address-cells = <1>; 2001 #size-cells = <0>; 2002 status = "disabled"; 2003 2004 ports { 2005 #address-cells = <1>; 2006 #size-cells = <0>; 2007 2008 mipi_in: port@0 { 2009 reg = <0>; 2010 #address-cells = <1>; 2011 #size-cells = <0>; 2012 2013 mipi_in_vopb: endpoint@0 { 2014 reg = <0>; 2015 remote-endpoint = <&vopb_out_mipi>; 2016 }; 2017 2018 mipi_in_vopl: endpoint@1 { 2019 reg = <1>; 2020 remote-endpoint = <&vopl_out_mipi>; 2021 }; 2022 }; 2023 2024 mipi_out: port@1 { 2025 reg = <1>; 2026 }; 2027 }; 2028 }; 2029 2030 mipi_dsi1: dsi@ff968000 { 2031 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"; 2032 reg = <0x0 0xff968000 0x0 0x8000>; 2033 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>; 2034 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>, 2035 <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>; 2036 clock-names = "ref", "pclk", "phy_cfg", "grf"; 2037 power-domains = <&power RK3399_PD_VIO>; 2038 resets = <&cru SRST_P_MIPI_DSI1>; 2039 reset-names = "apb"; 2040 rockchip,grf = <&grf>; 2041 #address-cells = <1>; 2042 #size-cells = <0>; 2043 #phy-cells = <0>; 2044 status = "disabled"; 2045 2046 ports { 2047 #address-cells = <1>; 2048 #size-cells = <0>; 2049 2050 mipi1_in: port@0 { 2051 reg = <0>; 2052 #address-cells = <1>; 2053 #size-cells = <0>; 2054 2055 mipi1_in_vopb: endpoint@0 { 2056 reg = <0>; 2057 remote-endpoint = <&vopb_out_mipi1>; 2058 }; 2059 2060 mipi1_in_vopl: endpoint@1 { 2061 reg = <1>; 2062 remote-endpoint = <&vopl_out_mipi1>; 2063 }; 2064 }; 2065 2066 mipi1_out: port@1 { 2067 reg = <1>; 2068 }; 2069 }; 2070 }; 2071 2072 edp: dp@ff970000 { 2073 compatible = "rockchip,rk3399-edp"; 2074 reg = <0x0 0xff970000 0x0 0x8000>; 2075 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 2076 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>; 2077 clock-names = "dp", "pclk", "grf"; 2078 pinctrl-names = "default"; 2079 pinctrl-0 = <&edp_hpd>; 2080 power-domains = <&power RK3399_PD_EDP>; 2081 resets = <&cru SRST_P_EDP_CTRL>; 2082 reset-names = "dp"; 2083 rockchip,grf = <&grf>; 2084 status = "disabled"; 2085 2086 ports { 2087 #address-cells = <1>; 2088 #size-cells = <0>; 2089 2090 edp_in: port@0 { 2091 reg = <0>; 2092 #address-cells = <1>; 2093 #size-cells = <0>; 2094 2095 edp_in_vopb: endpoint@0 { 2096 reg = <0>; 2097 remote-endpoint = <&vopb_out_edp>; 2098 }; 2099 2100 edp_in_vopl: endpoint@1 { 2101 reg = <1>; 2102 remote-endpoint = <&vopl_out_edp>; 2103 }; 2104 }; 2105 2106 edp_out: port@1 { 2107 reg = <1>; 2108 }; 2109 }; 2110 }; 2111 2112 gpu: gpu@ff9a0000 { 2113 compatible = "rockchip,rk3399-mali", "arm,mali-t860"; 2114 reg = <0x0 0xff9a0000 0x0 0x10000>; 2115 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>, 2116 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>, 2117 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>; 2118 interrupt-names = "job", "mmu", "gpu"; 2119 clocks = <&cru ACLK_GPU>; 2120 #cooling-cells = <2>; 2121 dynamic-power-coefficient = <2640>; 2122 power-domains = <&power RK3399_PD_GPU>; 2123 status = "disabled"; 2124 }; 2125 2126 pinctrl: pinctrl { 2127 compatible = "rockchip,rk3399-pinctrl"; 2128 rockchip,grf = <&grf>; 2129 rockchip,pmu = <&pmugrf>; 2130 #address-cells = <2>; 2131 #size-cells = <2>; 2132 ranges; 2133 2134 gpio0: gpio@ff720000 { 2135 compatible = "rockchip,gpio-bank"; 2136 reg = <0x0 0xff720000 0x0 0x100>; 2137 clocks = <&pmucru PCLK_GPIO0_PMU>; 2138 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>; 2139 2140 gpio-controller; 2141 #gpio-cells = <0x2>; 2142 2143 interrupt-controller; 2144 #interrupt-cells = <0x2>; 2145 }; 2146 2147 gpio1: gpio@ff730000 { 2148 compatible = "rockchip,gpio-bank"; 2149 reg = <0x0 0xff730000 0x0 0x100>; 2150 clocks = <&pmucru PCLK_GPIO1_PMU>; 2151 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>; 2152 2153 gpio-controller; 2154 #gpio-cells = <0x2>; 2155 2156 interrupt-controller; 2157 #interrupt-cells = <0x2>; 2158 }; 2159 2160 gpio2: gpio@ff780000 { 2161 compatible = "rockchip,gpio-bank"; 2162 reg = <0x0 0xff780000 0x0 0x100>; 2163 clocks = <&cru PCLK_GPIO2>; 2164 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>; 2165 2166 gpio-controller; 2167 #gpio-cells = <0x2>; 2168 2169 interrupt-controller; 2170 #interrupt-cells = <0x2>; 2171 }; 2172 2173 gpio3: gpio@ff788000 { 2174 compatible = "rockchip,gpio-bank"; 2175 reg = <0x0 0xff788000 0x0 0x100>; 2176 clocks = <&cru PCLK_GPIO3>; 2177 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>; 2178 2179 gpio-controller; 2180 #gpio-cells = <0x2>; 2181 2182 interrupt-controller; 2183 #interrupt-cells = <0x2>; 2184 }; 2185 2186 gpio4: gpio@ff790000 { 2187 compatible = "rockchip,gpio-bank"; 2188 reg = <0x0 0xff790000 0x0 0x100>; 2189 clocks = <&cru PCLK_GPIO4>; 2190 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 2191 2192 gpio-controller; 2193 #gpio-cells = <0x2>; 2194 2195 interrupt-controller; 2196 #interrupt-cells = <0x2>; 2197 }; 2198 2199 pcfg_pull_up: pcfg-pull-up { 2200 bias-pull-up; 2201 }; 2202 2203 pcfg_pull_down: pcfg-pull-down { 2204 bias-pull-down; 2205 }; 2206 2207 pcfg_pull_none: pcfg-pull-none { 2208 bias-disable; 2209 }; 2210 2211 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 2212 bias-disable; 2213 drive-strength = <12>; 2214 }; 2215 2216 pcfg_pull_none_13ma: pcfg-pull-none-13ma { 2217 bias-disable; 2218 drive-strength = <13>; 2219 }; 2220 2221 pcfg_pull_none_18ma: pcfg-pull-none-18ma { 2222 bias-disable; 2223 drive-strength = <18>; 2224 }; 2225 2226 pcfg_pull_none_20ma: pcfg-pull-none-20ma { 2227 bias-disable; 2228 drive-strength = <20>; 2229 }; 2230 2231 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 2232 bias-pull-up; 2233 drive-strength = <2>; 2234 }; 2235 2236 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 2237 bias-pull-up; 2238 drive-strength = <8>; 2239 }; 2240 2241 pcfg_pull_up_18ma: pcfg-pull-up-18ma { 2242 bias-pull-up; 2243 drive-strength = <18>; 2244 }; 2245 2246 pcfg_pull_up_20ma: pcfg-pull-up-20ma { 2247 bias-pull-up; 2248 drive-strength = <20>; 2249 }; 2250 2251 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 2252 bias-pull-down; 2253 drive-strength = <4>; 2254 }; 2255 2256 pcfg_pull_down_8ma: pcfg-pull-down-8ma { 2257 bias-pull-down; 2258 drive-strength = <8>; 2259 }; 2260 2261 pcfg_pull_down_12ma: pcfg-pull-down-12ma { 2262 bias-pull-down; 2263 drive-strength = <12>; 2264 }; 2265 2266 pcfg_pull_down_18ma: pcfg-pull-down-18ma { 2267 bias-pull-down; 2268 drive-strength = <18>; 2269 }; 2270 2271 pcfg_pull_down_20ma: pcfg-pull-down-20ma { 2272 bias-pull-down; 2273 drive-strength = <20>; 2274 }; 2275 2276 pcfg_output_high: pcfg-output-high { 2277 output-high; 2278 }; 2279 2280 pcfg_output_low: pcfg-output-low { 2281 output-low; 2282 }; 2283 2284 pcfg_input_enable: pcfg-input-enable { 2285 input-enable; 2286 }; 2287 2288 pcfg_input_pull_up: pcfg-input-pull-up { 2289 input-enable; 2290 bias-pull-up; 2291 }; 2292 2293 pcfg_input_pull_down: pcfg-input-pull-down { 2294 input-enable; 2295 bias-pull-down; 2296 }; 2297 2298 clock { 2299 clk_32k: clk-32k { 2300 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>; 2301 }; 2302 }; 2303 2304 cif { 2305 cif_clkin: cif-clkin { 2306 rockchip,pins = 2307 <2 RK_PB2 3 &pcfg_pull_none>; 2308 }; 2309 2310 cif_clkouta: cif-clkouta { 2311 rockchip,pins = 2312 <2 RK_PB3 3 &pcfg_pull_none>; 2313 }; 2314 }; 2315 2316 edp { 2317 edp_hpd: edp-hpd { 2318 rockchip,pins = 2319 <4 RK_PC7 2 &pcfg_pull_none>; 2320 }; 2321 }; 2322 2323 gmac { 2324 rgmii_pins: rgmii-pins { 2325 rockchip,pins = 2326 /* mac_txclk */ 2327 <3 RK_PC1 1 &pcfg_pull_none_13ma>, 2328 /* mac_rxclk */ 2329 <3 RK_PB6 1 &pcfg_pull_none>, 2330 /* mac_mdio */ 2331 <3 RK_PB5 1 &pcfg_pull_none>, 2332 /* mac_txen */ 2333 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2334 /* mac_clk */ 2335 <3 RK_PB3 1 &pcfg_pull_none>, 2336 /* mac_rxdv */ 2337 <3 RK_PB1 1 &pcfg_pull_none>, 2338 /* mac_mdc */ 2339 <3 RK_PB0 1 &pcfg_pull_none>, 2340 /* mac_rxd1 */ 2341 <3 RK_PA7 1 &pcfg_pull_none>, 2342 /* mac_rxd0 */ 2343 <3 RK_PA6 1 &pcfg_pull_none>, 2344 /* mac_txd1 */ 2345 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2346 /* mac_txd0 */ 2347 <3 RK_PA4 1 &pcfg_pull_none_13ma>, 2348 /* mac_rxd3 */ 2349 <3 RK_PA3 1 &pcfg_pull_none>, 2350 /* mac_rxd2 */ 2351 <3 RK_PA2 1 &pcfg_pull_none>, 2352 /* mac_txd3 */ 2353 <3 RK_PA1 1 &pcfg_pull_none_13ma>, 2354 /* mac_txd2 */ 2355 <3 RK_PA0 1 &pcfg_pull_none_13ma>; 2356 }; 2357 2358 rmii_pins: rmii-pins { 2359 rockchip,pins = 2360 /* mac_mdio */ 2361 <3 RK_PB5 1 &pcfg_pull_none>, 2362 /* mac_txen */ 2363 <3 RK_PB4 1 &pcfg_pull_none_13ma>, 2364 /* mac_clk */ 2365 <3 RK_PB3 1 &pcfg_pull_none>, 2366 /* mac_rxer */ 2367 <3 RK_PB2 1 &pcfg_pull_none>, 2368 /* mac_rxdv */ 2369 <3 RK_PB1 1 &pcfg_pull_none>, 2370 /* mac_mdc */ 2371 <3 RK_PB0 1 &pcfg_pull_none>, 2372 /* mac_rxd1 */ 2373 <3 RK_PA7 1 &pcfg_pull_none>, 2374 /* mac_rxd0 */ 2375 <3 RK_PA6 1 &pcfg_pull_none>, 2376 /* mac_txd1 */ 2377 <3 RK_PA5 1 &pcfg_pull_none_13ma>, 2378 /* mac_txd0 */ 2379 <3 RK_PA4 1 &pcfg_pull_none_13ma>; 2380 }; 2381 }; 2382 2383 i2c0 { 2384 i2c0_xfer: i2c0-xfer { 2385 rockchip,pins = 2386 <1 RK_PB7 2 &pcfg_pull_none>, 2387 <1 RK_PC0 2 &pcfg_pull_none>; 2388 }; 2389 }; 2390 2391 i2c1 { 2392 i2c1_xfer: i2c1-xfer { 2393 rockchip,pins = 2394 <4 RK_PA2 1 &pcfg_pull_none>, 2395 <4 RK_PA1 1 &pcfg_pull_none>; 2396 }; 2397 }; 2398 2399 i2c2 { 2400 i2c2_xfer: i2c2-xfer { 2401 rockchip,pins = 2402 <2 RK_PA1 2 &pcfg_pull_none_12ma>, 2403 <2 RK_PA0 2 &pcfg_pull_none_12ma>; 2404 }; 2405 }; 2406 2407 i2c3 { 2408 i2c3_xfer: i2c3-xfer { 2409 rockchip,pins = 2410 <4 RK_PC1 1 &pcfg_pull_none>, 2411 <4 RK_PC0 1 &pcfg_pull_none>; 2412 }; 2413 }; 2414 2415 i2c4 { 2416 i2c4_xfer: i2c4-xfer { 2417 rockchip,pins = 2418 <1 RK_PB4 1 &pcfg_pull_none>, 2419 <1 RK_PB3 1 &pcfg_pull_none>; 2420 }; 2421 }; 2422 2423 i2c5 { 2424 i2c5_xfer: i2c5-xfer { 2425 rockchip,pins = 2426 <3 RK_PB3 2 &pcfg_pull_none>, 2427 <3 RK_PB2 2 &pcfg_pull_none>; 2428 }; 2429 }; 2430 2431 i2c6 { 2432 i2c6_xfer: i2c6-xfer { 2433 rockchip,pins = 2434 <2 RK_PB2 2 &pcfg_pull_none>, 2435 <2 RK_PB1 2 &pcfg_pull_none>; 2436 }; 2437 }; 2438 2439 i2c7 { 2440 i2c7_xfer: i2c7-xfer { 2441 rockchip,pins = 2442 <2 RK_PB0 2 &pcfg_pull_none>, 2443 <2 RK_PA7 2 &pcfg_pull_none>; 2444 }; 2445 }; 2446 2447 i2c8 { 2448 i2c8_xfer: i2c8-xfer { 2449 rockchip,pins = 2450 <1 RK_PC5 1 &pcfg_pull_none>, 2451 <1 RK_PC4 1 &pcfg_pull_none>; 2452 }; 2453 }; 2454 2455 i2s0 { 2456 i2s0_2ch_bus: i2s0-2ch-bus { 2457 rockchip,pins = 2458 <3 RK_PD0 1 &pcfg_pull_none>, 2459 <3 RK_PD1 1 &pcfg_pull_none>, 2460 <3 RK_PD2 1 &pcfg_pull_none>, 2461 <3 RK_PD3 1 &pcfg_pull_none>, 2462 <3 RK_PD7 1 &pcfg_pull_none>, 2463 <4 RK_PA0 1 &pcfg_pull_none>; 2464 }; 2465 2466 i2s0_2ch_bus_bclk_off: i2s0-2ch-bus-bclk-off { 2467 rockchip,pins = 2468 <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, 2469 <3 RK_PD1 1 &pcfg_pull_none>, 2470 <3 RK_PD2 1 &pcfg_pull_none>, 2471 <3 RK_PD3 1 &pcfg_pull_none>, 2472 <3 RK_PD7 1 &pcfg_pull_none>, 2473 <4 RK_PA0 1 &pcfg_pull_none>; 2474 }; 2475 2476 i2s0_8ch_bus: i2s0-8ch-bus { 2477 rockchip,pins = 2478 <3 RK_PD0 1 &pcfg_pull_none>, 2479 <3 RK_PD1 1 &pcfg_pull_none>, 2480 <3 RK_PD2 1 &pcfg_pull_none>, 2481 <3 RK_PD3 1 &pcfg_pull_none>, 2482 <3 RK_PD4 1 &pcfg_pull_none>, 2483 <3 RK_PD5 1 &pcfg_pull_none>, 2484 <3 RK_PD6 1 &pcfg_pull_none>, 2485 <3 RK_PD7 1 &pcfg_pull_none>, 2486 <4 RK_PA0 1 &pcfg_pull_none>; 2487 }; 2488 2489 i2s0_8ch_bus_bclk_off: i2s0-8ch-bus-bclk-off { 2490 rockchip,pins = 2491 <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>, 2492 <3 RK_PD1 1 &pcfg_pull_none>, 2493 <3 RK_PD2 1 &pcfg_pull_none>, 2494 <3 RK_PD3 1 &pcfg_pull_none>, 2495 <3 RK_PD4 1 &pcfg_pull_none>, 2496 <3 RK_PD5 1 &pcfg_pull_none>, 2497 <3 RK_PD6 1 &pcfg_pull_none>, 2498 <3 RK_PD7 1 &pcfg_pull_none>, 2499 <4 RK_PA0 1 &pcfg_pull_none>; 2500 }; 2501 }; 2502 2503 i2s1 { 2504 i2s1_2ch_bus: i2s1-2ch-bus { 2505 rockchip,pins = 2506 <4 RK_PA3 1 &pcfg_pull_none>, 2507 <4 RK_PA4 1 &pcfg_pull_none>, 2508 <4 RK_PA5 1 &pcfg_pull_none>, 2509 <4 RK_PA6 1 &pcfg_pull_none>, 2510 <4 RK_PA7 1 &pcfg_pull_none>; 2511 }; 2512 2513 i2s1_2ch_bus_bclk_off: i2s1-2ch-bus-bclk-off { 2514 rockchip,pins = 2515 <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>, 2516 <4 RK_PA4 1 &pcfg_pull_none>, 2517 <4 RK_PA5 1 &pcfg_pull_none>, 2518 <4 RK_PA6 1 &pcfg_pull_none>, 2519 <4 RK_PA7 1 &pcfg_pull_none>; 2520 }; 2521 }; 2522 2523 sdio0 { 2524 sdio0_bus1: sdio0-bus1 { 2525 rockchip,pins = 2526 <2 RK_PC4 1 &pcfg_pull_up>; 2527 }; 2528 2529 sdio0_bus4: sdio0-bus4 { 2530 rockchip,pins = 2531 <2 RK_PC4 1 &pcfg_pull_up>, 2532 <2 RK_PC5 1 &pcfg_pull_up>, 2533 <2 RK_PC6 1 &pcfg_pull_up>, 2534 <2 RK_PC7 1 &pcfg_pull_up>; 2535 }; 2536 2537 sdio0_cmd: sdio0-cmd { 2538 rockchip,pins = 2539 <2 RK_PD0 1 &pcfg_pull_up>; 2540 }; 2541 2542 sdio0_clk: sdio0-clk { 2543 rockchip,pins = 2544 <2 RK_PD1 1 &pcfg_pull_none>; 2545 }; 2546 2547 sdio0_cd: sdio0-cd { 2548 rockchip,pins = 2549 <2 RK_PD2 1 &pcfg_pull_up>; 2550 }; 2551 2552 sdio0_pwr: sdio0-pwr { 2553 rockchip,pins = 2554 <2 RK_PD3 1 &pcfg_pull_up>; 2555 }; 2556 2557 sdio0_bkpwr: sdio0-bkpwr { 2558 rockchip,pins = 2559 <2 RK_PD4 1 &pcfg_pull_up>; 2560 }; 2561 2562 sdio0_wp: sdio0-wp { 2563 rockchip,pins = 2564 <0 RK_PA3 1 &pcfg_pull_up>; 2565 }; 2566 2567 sdio0_int: sdio0-int { 2568 rockchip,pins = 2569 <0 RK_PA4 1 &pcfg_pull_up>; 2570 }; 2571 }; 2572 2573 sdmmc { 2574 sdmmc_bus1: sdmmc-bus1 { 2575 rockchip,pins = 2576 <4 RK_PB0 1 &pcfg_pull_up>; 2577 }; 2578 2579 sdmmc_bus4: sdmmc-bus4 { 2580 rockchip,pins = 2581 <4 RK_PB0 1 &pcfg_pull_up>, 2582 <4 RK_PB1 1 &pcfg_pull_up>, 2583 <4 RK_PB2 1 &pcfg_pull_up>, 2584 <4 RK_PB3 1 &pcfg_pull_up>; 2585 }; 2586 2587 sdmmc_clk: sdmmc-clk { 2588 rockchip,pins = 2589 <4 RK_PB4 1 &pcfg_pull_none>; 2590 }; 2591 2592 sdmmc_cmd: sdmmc-cmd { 2593 rockchip,pins = 2594 <4 RK_PB5 1 &pcfg_pull_up>; 2595 }; 2596 2597 sdmmc_cd: sdmmc-cd { 2598 rockchip,pins = 2599 <0 RK_PA7 1 &pcfg_pull_up>; 2600 }; 2601 2602 sdmmc_wp: sdmmc-wp { 2603 rockchip,pins = 2604 <0 RK_PB0 1 &pcfg_pull_up>; 2605 }; 2606 }; 2607 2608 suspend { 2609 ap_pwroff: ap-pwroff { 2610 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; 2611 }; 2612 2613 ddrio_pwroff: ddrio-pwroff { 2614 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>; 2615 }; 2616 }; 2617 2618 spdif { 2619 spdif_bus: spdif-bus { 2620 rockchip,pins = 2621 <4 RK_PC5 1 &pcfg_pull_none>; 2622 }; 2623 2624 spdif_bus_1: spdif-bus-1 { 2625 rockchip,pins = 2626 <3 RK_PC0 3 &pcfg_pull_none>; 2627 }; 2628 }; 2629 2630 spi0 { 2631 spi0_clk: spi0-clk { 2632 rockchip,pins = 2633 <3 RK_PA6 2 &pcfg_pull_up>; 2634 }; 2635 spi0_cs0: spi0-cs0 { 2636 rockchip,pins = 2637 <3 RK_PA7 2 &pcfg_pull_up>; 2638 }; 2639 spi0_cs1: spi0-cs1 { 2640 rockchip,pins = 2641 <3 RK_PB0 2 &pcfg_pull_up>; 2642 }; 2643 spi0_tx: spi0-tx { 2644 rockchip,pins = 2645 <3 RK_PA5 2 &pcfg_pull_up>; 2646 }; 2647 spi0_rx: spi0-rx { 2648 rockchip,pins = 2649 <3 RK_PA4 2 &pcfg_pull_up>; 2650 }; 2651 }; 2652 2653 spi1 { 2654 spi1_clk: spi1-clk { 2655 rockchip,pins = 2656 <1 RK_PB1 2 &pcfg_pull_up>; 2657 }; 2658 spi1_cs0: spi1-cs0 { 2659 rockchip,pins = 2660 <1 RK_PB2 2 &pcfg_pull_up>; 2661 }; 2662 spi1_rx: spi1-rx { 2663 rockchip,pins = 2664 <1 RK_PA7 2 &pcfg_pull_up>; 2665 }; 2666 spi1_tx: spi1-tx { 2667 rockchip,pins = 2668 <1 RK_PB0 2 &pcfg_pull_up>; 2669 }; 2670 }; 2671 2672 spi2 { 2673 spi2_clk: spi2-clk { 2674 rockchip,pins = 2675 <2 RK_PB3 1 &pcfg_pull_up>; 2676 }; 2677 spi2_cs0: spi2-cs0 { 2678 rockchip,pins = 2679 <2 RK_PB4 1 &pcfg_pull_up>; 2680 }; 2681 spi2_rx: spi2-rx { 2682 rockchip,pins = 2683 <2 RK_PB1 1 &pcfg_pull_up>; 2684 }; 2685 spi2_tx: spi2-tx { 2686 rockchip,pins = 2687 <2 RK_PB2 1 &pcfg_pull_up>; 2688 }; 2689 }; 2690 2691 spi3 { 2692 spi3_clk: spi3-clk { 2693 rockchip,pins = 2694 <1 RK_PC1 1 &pcfg_pull_up>; 2695 }; 2696 spi3_cs0: spi3-cs0 { 2697 rockchip,pins = 2698 <1 RK_PC2 1 &pcfg_pull_up>; 2699 }; 2700 spi3_rx: spi3-rx { 2701 rockchip,pins = 2702 <1 RK_PB7 1 &pcfg_pull_up>; 2703 }; 2704 spi3_tx: spi3-tx { 2705 rockchip,pins = 2706 <1 RK_PC0 1 &pcfg_pull_up>; 2707 }; 2708 }; 2709 2710 spi4 { 2711 spi4_clk: spi4-clk { 2712 rockchip,pins = 2713 <3 RK_PA2 2 &pcfg_pull_up>; 2714 }; 2715 spi4_cs0: spi4-cs0 { 2716 rockchip,pins = 2717 <3 RK_PA3 2 &pcfg_pull_up>; 2718 }; 2719 spi4_rx: spi4-rx { 2720 rockchip,pins = 2721 <3 RK_PA0 2 &pcfg_pull_up>; 2722 }; 2723 spi4_tx: spi4-tx { 2724 rockchip,pins = 2725 <3 RK_PA1 2 &pcfg_pull_up>; 2726 }; 2727 }; 2728 2729 spi5 { 2730 spi5_clk: spi5-clk { 2731 rockchip,pins = 2732 <2 RK_PC6 2 &pcfg_pull_up>; 2733 }; 2734 spi5_cs0: spi5-cs0 { 2735 rockchip,pins = 2736 <2 RK_PC7 2 &pcfg_pull_up>; 2737 }; 2738 spi5_rx: spi5-rx { 2739 rockchip,pins = 2740 <2 RK_PC4 2 &pcfg_pull_up>; 2741 }; 2742 spi5_tx: spi5-tx { 2743 rockchip,pins = 2744 <2 RK_PC5 2 &pcfg_pull_up>; 2745 }; 2746 }; 2747 2748 testclk { 2749 test_clkout0: test-clkout0 { 2750 rockchip,pins = 2751 <0 RK_PA0 1 &pcfg_pull_none>; 2752 }; 2753 2754 test_clkout1: test-clkout1 { 2755 rockchip,pins = 2756 <2 RK_PD1 2 &pcfg_pull_none>; 2757 }; 2758 2759 test_clkout2: test-clkout2 { 2760 rockchip,pins = 2761 <0 RK_PB0 3 &pcfg_pull_none>; 2762 }; 2763 }; 2764 2765 tsadc { 2766 otp_pin: otp-pin { 2767 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 2768 }; 2769 2770 otp_out: otp-out { 2771 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>; 2772 }; 2773 }; 2774 2775 uart0 { 2776 uart0_xfer: uart0-xfer { 2777 rockchip,pins = 2778 <2 RK_PC0 1 &pcfg_pull_up>, 2779 <2 RK_PC1 1 &pcfg_pull_none>; 2780 }; 2781 2782 uart0_cts: uart0-cts { 2783 rockchip,pins = 2784 <2 RK_PC2 1 &pcfg_pull_none>; 2785 }; 2786 2787 uart0_rts: uart0-rts { 2788 rockchip,pins = 2789 <2 RK_PC3 1 &pcfg_pull_none>; 2790 }; 2791 }; 2792 2793 uart1 { 2794 uart1_xfer: uart1-xfer { 2795 rockchip,pins = 2796 <3 RK_PB4 2 &pcfg_pull_up>, 2797 <3 RK_PB5 2 &pcfg_pull_none>; 2798 }; 2799 }; 2800 2801 uart2a { 2802 uart2a_xfer: uart2a-xfer { 2803 rockchip,pins = 2804 <4 RK_PB0 2 &pcfg_pull_up>, 2805 <4 RK_PB1 2 &pcfg_pull_none>; 2806 }; 2807 }; 2808 2809 uart2b { 2810 uart2b_xfer: uart2b-xfer { 2811 rockchip,pins = 2812 <4 RK_PC0 2 &pcfg_pull_up>, 2813 <4 RK_PC1 2 &pcfg_pull_none>; 2814 }; 2815 }; 2816 2817 uart2c { 2818 uart2c_xfer: uart2c-xfer { 2819 rockchip,pins = 2820 <4 RK_PC3 1 &pcfg_pull_up>, 2821 <4 RK_PC4 1 &pcfg_pull_none>; 2822 }; 2823 }; 2824 2825 uart3 { 2826 uart3_xfer: uart3-xfer { 2827 rockchip,pins = 2828 <3 RK_PB6 2 &pcfg_pull_up>, 2829 <3 RK_PB7 2 &pcfg_pull_none>; 2830 }; 2831 2832 uart3_cts: uart3-cts { 2833 rockchip,pins = 2834 <3 RK_PC0 2 &pcfg_pull_none>; 2835 }; 2836 2837 uart3_rts: uart3-rts { 2838 rockchip,pins = 2839 <3 RK_PC1 2 &pcfg_pull_none>; 2840 }; 2841 }; 2842 2843 uart4 { 2844 uart4_xfer: uart4-xfer { 2845 rockchip,pins = 2846 <1 RK_PA7 1 &pcfg_pull_up>, 2847 <1 RK_PB0 1 &pcfg_pull_none>; 2848 }; 2849 }; 2850 2851 uarthdcp { 2852 uarthdcp_xfer: uarthdcp-xfer { 2853 rockchip,pins = 2854 <4 RK_PC5 2 &pcfg_pull_up>, 2855 <4 RK_PC6 2 &pcfg_pull_none>; 2856 }; 2857 }; 2858 2859 pwm0 { 2860 pwm0_pin: pwm0-pin { 2861 rockchip,pins = 2862 <4 RK_PC2 1 &pcfg_pull_none>; 2863 }; 2864 2865 pwm0_pin_pull_down: pwm0-pin-pull-down { 2866 rockchip,pins = 2867 <4 RK_PC2 1 &pcfg_pull_down>; 2868 }; 2869 2870 vop0_pwm_pin: vop0-pwm-pin { 2871 rockchip,pins = 2872 <4 RK_PC2 2 &pcfg_pull_none>; 2873 }; 2874 2875 vop1_pwm_pin: vop1-pwm-pin { 2876 rockchip,pins = 2877 <4 RK_PC2 3 &pcfg_pull_none>; 2878 }; 2879 }; 2880 2881 pwm1 { 2882 pwm1_pin: pwm1-pin { 2883 rockchip,pins = 2884 <4 RK_PC6 1 &pcfg_pull_none>; 2885 }; 2886 2887 pwm1_pin_pull_down: pwm1-pin-pull-down { 2888 rockchip,pins = 2889 <4 RK_PC6 1 &pcfg_pull_down>; 2890 }; 2891 }; 2892 2893 pwm2 { 2894 pwm2_pin: pwm2-pin { 2895 rockchip,pins = 2896 <1 RK_PC3 1 &pcfg_pull_none>; 2897 }; 2898 2899 pwm2_pin_pull_down: pwm2-pin-pull-down { 2900 rockchip,pins = 2901 <1 RK_PC3 1 &pcfg_pull_down>; 2902 }; 2903 }; 2904 2905 pwm3a { 2906 pwm3a_pin: pwm3a-pin { 2907 rockchip,pins = 2908 <0 RK_PA6 1 &pcfg_pull_none>; 2909 }; 2910 }; 2911 2912 pwm3b { 2913 pwm3b_pin: pwm3b-pin { 2914 rockchip,pins = 2915 <1 RK_PB6 1 &pcfg_pull_none>; 2916 }; 2917 }; 2918 2919 hdmi { 2920 hdmi_i2c_xfer: hdmi-i2c-xfer { 2921 rockchip,pins = 2922 <4 RK_PC1 3 &pcfg_pull_none>, 2923 <4 RK_PC0 3 &pcfg_pull_none>; 2924 }; 2925 2926 hdmi_cec: hdmi-cec { 2927 rockchip,pins = 2928 <4 RK_PC7 1 &pcfg_pull_none>; 2929 }; 2930 }; 2931 2932 pcie { 2933 pcie_clkreqn_cpm: pci-clkreqn-cpm { 2934 rockchip,pins = 2935 <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 2936 }; 2937 2938 pcie_clkreqnb_cpm: pci-clkreqnb-cpm { 2939 rockchip,pins = 2940 <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 2941 }; 2942 }; 2943 2944 }; 2945}; 2946