1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Google Gru-scarlet board device tree source 4 * 5 * Copyright 2018 Google, Inc 6 */ 7 8#include "rk3399-gru.dtsi" 9 10/{ 11 chassis-type = "tablet"; 12 13 /* Power tree */ 14 15 /* ppvar_sys children, sorted by name */ 16 pp1250_s3: pp1250-s3 { 17 compatible = "regulator-fixed"; 18 regulator-name = "pp1250_s3"; 19 20 /* EC turns on w/ pp1250_s3_en; always on for AP */ 21 regulator-always-on; 22 regulator-boot-on; 23 regulator-min-microvolt = <1250000>; 24 regulator-max-microvolt = <1250000>; 25 26 vin-supply = <&ppvar_sys>; 27 }; 28 29 pp1250_cam: pp1250-dvdd { 30 compatible = "regulator-fixed"; 31 regulator-name = "pp1250_dvdd"; 32 pinctrl-names = "default"; 33 pinctrl-0 = <&pp1250_cam_en>; 34 35 enable-active-high; 36 gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>; 37 38 /* 740us delay from gpio output high to pp1250 stable, 39 * rounding up to 1ms for safety. 40 */ 41 startup-delay-us = <1000>; 42 vin-supply = <&pp1250_s3>; 43 }; 44 45 pp900_s0: pp900-s0 { 46 compatible = "regulator-fixed"; 47 regulator-name = "pp900_s0"; 48 49 /* EC turns on w/ pp900_s0_en; always on for AP */ 50 regulator-always-on; 51 regulator-boot-on; 52 regulator-min-microvolt = <900000>; 53 regulator-max-microvolt = <900000>; 54 55 vin-supply = <&ppvar_sys>; 56 }; 57 58 ppvarn_lcd: ppvarn-lcd { 59 compatible = "regulator-fixed"; 60 regulator-name = "ppvarn_lcd"; 61 pinctrl-names = "default"; 62 pinctrl-0 = <&ppvarn_lcd_en>; 63 64 enable-active-high; 65 gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; 66 vin-supply = <&ppvar_sys>; 67 }; 68 69 ppvarp_lcd: ppvarp-lcd { 70 compatible = "regulator-fixed"; 71 regulator-name = "ppvarp_lcd"; 72 pinctrl-names = "default"; 73 pinctrl-0 = <&ppvarp_lcd_en>; 74 75 enable-active-high; 76 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 77 vin-supply = <&ppvar_sys>; 78 }; 79 80 /* pp1800 children, sorted by name */ 81 pp900_s3: pp900-s3 { 82 compatible = "regulator-fixed"; 83 regulator-name = "pp900_s3"; 84 85 /* EC turns on w/ pp900_s3_en; always on for AP */ 86 regulator-always-on; 87 regulator-boot-on; 88 regulator-min-microvolt = <900000>; 89 regulator-max-microvolt = <900000>; 90 91 vin-supply = <&pp1800>; 92 }; 93 94 /* EC turns on pp1800_s3_en */ 95 pp1800_s3: pp1800 { 96 }; 97 98 /* pp3300 children, sorted by name */ 99 pp2800_cam: pp2800-avdd { 100 compatible = "regulator-fixed"; 101 regulator-name = "pp2800_avdd"; 102 pinctrl-names = "default"; 103 pinctrl-0 = <&pp2800_cam_en>; 104 105 enable-active-high; 106 gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>; 107 startup-delay-us = <100>; 108 vin-supply = <&pp3300>; 109 }; 110 111 /* EC turns on pp3300_s0_en */ 112 pp3300_s0: pp3300 { 113 }; 114 115 /* EC turns on pp3300_s3_en */ 116 pp3300_s3: pp3300 { 117 }; 118 119 /* 120 * See b/66922012 121 * 122 * This is a hack to make sure the Bluetooth part of the QCA6174A 123 * is reset at boot by toggling BT_EN. At boot BT_EN is first set 124 * to low when the bt_3v3 regulator is registered (in disabled 125 * state). The fake regulator is configured as a supply of the 126 * wlan_3v3 regulator below. When wlan_3v3 is enabled early in 127 * the boot process it also enables its supply regulator bt_3v3, 128 * which changes BT_EN to high. 129 */ 130 bt_3v3: bt-3v3 { 131 compatible = "regulator-fixed"; 132 regulator-name = "bt_3v3"; 133 pinctrl-names = "default"; 134 pinctrl-0 = <&bt_en_1v8_l>; 135 136 enable-active-high; 137 gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; 138 vin-supply = <&pp3300_s3>; 139 }; 140 141 wlan_3v3: wlan-3v3 { 142 compatible = "regulator-fixed"; 143 regulator-name = "wlan_3v3"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&wlan_pd_1v8_l>; 146 147 /* 148 * The WL_EN pin is driven low when the regulator is 149 * registered, and transitions to high when the PCIe bus 150 * is powered up. 151 */ 152 enable-active-high; 153 gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; 154 155 /* 156 * Require minimum 10ms from power-on (e.g., PD#) to init PCIe. 157 * TODO (b/64444991): how long to assert PD#? 158 */ 159 regulator-enable-ramp-delay = <10000>; 160 /* See bt_3v3 hack above */ 161 vin-supply = <&bt_3v3>; 162 }; 163 164 backlight: backlight { 165 compatible = "pwm-backlight"; 166 enable-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; 167 pinctrl-names = "default"; 168 pinctrl-0 = <&bl_en>; 169 pwms = <&pwm1 0 1000000 0>; 170 }; 171 172 dmic: dmic { 173 compatible = "dmic-codec"; 174 dmicen-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; 175 pinctrl-names = "default"; 176 pinctrl-0 = <&dmic_en>; 177 wakeup-delay-ms = <250>; 178 }; 179 180 gpio_keys: gpio-keys { 181 compatible = "gpio-keys"; 182 pinctrl-names = "default"; 183 pinctrl-0 = <&pen_eject_odl>; 184 185 switch-pen-insert { 186 label = "Pen Insert"; 187 /* Insert = low, eject = high */ 188 gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 189 linux,code = <SW_PEN_INSERTED>; 190 linux,input-type = <EV_SW>; 191 wakeup-source; 192 }; 193 }; 194}; 195 196/* pp900_s0 aliases */ 197pp900_ddrpll_ap: &pp900_s0 { 198}; 199pp900_pcie: &pp900_s0 { 200}; 201pp900_usb: &pp900_s0 { 202}; 203 204/* pp900_s3 aliases */ 205pp900_emmcpll: &pp900_s3 { 206}; 207 208/* EC turns on; alias for pp1800_s0 */ 209pp1800_pcie: &pp1800_s0 { 210}; 211 212/* On scarlet PPVAR(big_cpu, lit_cpu, gpu) need to adjust voltage ranges */ 213&ppvar_bigcpu { 214 ctrl-voltage-range = <800074 1299226>; 215 regulator-min-microvolt = <800074>; 216 regulator-max-microvolt = <1299226>; 217}; 218 219&ppvar_bigcpu_pwm { 220 /* On scarlet ppvar big cpu use pwm3 */ 221 pwms = <&pwm3 0 3337 0>; 222 regulator-min-microvolt = <800074>; 223 regulator-max-microvolt = <1299226>; 224}; 225 226&ppvar_litcpu { 227 ctrl-voltage-range = <802122 1199620>; 228 regulator-min-microvolt = <802122>; 229 regulator-max-microvolt = <1199620>; 230}; 231 232&ppvar_litcpu_pwm { 233 regulator-min-microvolt = <802122>; 234 regulator-max-microvolt = <1199620>; 235}; 236 237&ppvar_gpu { 238 ctrl-voltage-range = <799600 1099600>; 239 regulator-min-microvolt = <799600>; 240 regulator-max-microvolt = <1099600>; 241}; 242 243&ppvar_gpu_pwm { 244 regulator-min-microvolt = <799600>; 245 regulator-max-microvolt = <1099600>; 246}; 247 248&ppvar_sd_card_io { 249 states = <1800000 0x0>, <3300000 0x1>; 250 regulator-max-microvolt = <3300000>; 251}; 252 253&pp3000_sd_slot { 254 vin-supply = <&pp3300>; 255}; 256 257ap_i2c_dig: &i2c2 { 258 status = "okay"; 259 260 clock-frequency = <400000>; 261 262 /* These are relatively safe rise/fall times. */ 263 i2c-scl-falling-time-ns = <50>; 264 i2c-scl-rising-time-ns = <300>; 265 266 digitizer: digitizer@9 { 267 compatible = "hid-over-i2c"; 268 reg = <0x9>; 269 interrupt-parent = <&gpio1>; 270 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 271 hid-descr-addr = <0x1>; 272 pinctrl-names = "default"; 273 pinctrl-0 = <&pen_int_odl &pen_reset_l>; 274 }; 275}; 276 277&ap_i2c_ts { 278 touchscreen: touchscreen@10 { 279 compatible = "elan,ekth3500"; 280 reg = <0x10>; 281 interrupt-parent = <&gpio1>; 282 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 283 pinctrl-names = "default"; 284 pinctrl-0 = <&touch_int_l &touch_reset_l>; 285 reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; 286 }; 287}; 288 289camera: &i2c7 { 290 status = "okay"; 291 292 clock-frequency = <400000>; 293 294 /* These are relatively safe rise/fall times; TODO: measure */ 295 i2c-scl-falling-time-ns = <50>; 296 i2c-scl-rising-time-ns = <300>; 297 298 /* 24M mclk is shared between world and user cameras */ 299 pinctrl-0 = <&i2c7_xfer &test_clkout1>; 300 301 /* Rear-facing camera */ 302 wcam: camera@36 { 303 compatible = "ovti,ov5695"; 304 reg = <0x36>; 305 pinctrl-names = "default"; 306 pinctrl-0 = <&wcam_rst>; 307 308 clocks = <&cru SCLK_TESTCLKOUT1>; 309 clock-names = "xvclk"; 310 311 avdd-supply = <&pp2800_cam>; 312 dvdd-supply = <&pp1250_cam>; 313 dovdd-supply = <&pp1800_s0>; 314 reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; 315 316 port { 317 wcam_out: endpoint { 318 remote-endpoint = <&mipi_in_wcam>; 319 data-lanes = <1 2>; 320 }; 321 }; 322 }; 323 324 /* Front-facing camera */ 325 ucam: camera@3c { 326 compatible = "ovti,ov2685"; 327 reg = <0x3c>; 328 pinctrl-names = "default"; 329 pinctrl-0 = <&ucam_rst>; 330 331 clocks = <&cru SCLK_TESTCLKOUT1>; 332 clock-names = "xvclk"; 333 334 avdd-supply = <&pp2800_cam>; 335 dovdd-supply = <&pp1800_s0>; 336 dvdd-supply = <&pp1800_s0>; 337 reset-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; 338 339 port { 340 ucam_out: endpoint { 341 remote-endpoint = <&mipi_in_ucam>; 342 data-lanes = <1>; 343 }; 344 }; 345 }; 346}; 347 348&cdn_dp { 349 extcon = <&usbc_extcon0>; 350 phys = <&tcphy0_dp>; 351}; 352 353&cpu_alert0 { 354 temperature = <66000>; 355}; 356 357&cpu_alert1 { 358 temperature = <71000>; 359}; 360 361&cros_ec { 362 interrupt-parent = <&gpio1>; 363 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 364}; 365 366&cru { 367 assigned-clocks = 368 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 369 <&cru PLL_NPLL>, 370 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 371 <&cru PCLK_PERIHP>, 372 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 373 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 374 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 375 <&cru ACLK_VIO>, 376 <&cru ACLK_GIC_PRE>, 377 <&cru PCLK_DDR>, 378 <&cru ACLK_HDCP>, 379 <&cru ACLK_VDU>; 380 assigned-clock-rates = 381 <600000000>, <1600000000>, 382 <1000000000>, 383 <150000000>, <75000000>, 384 <37500000>, 385 <100000000>, <100000000>, 386 <50000000>, <800000000>, 387 <100000000>, <50000000>, 388 <400000000>, 389 <200000000>, 390 <200000000>, 391 <400000000>, 392 <400000000>; 393}; 394 395/* The center supply is fixed to .9V on scarlet */ 396&dmc { 397 center-supply = <&pp900_s0>; 398}; 399 400/* We don't need .925 V for 928 MHz on scarlet */ 401&dmc_opp_table { 402 opp03 { 403 opp-microvolt = <900000>; 404 }; 405}; 406 407&gpio0 { 408 gpio-line-names = /* GPIO0 A 0-7 */ 409 "CLK_32K_AP", 410 "EC_IN_RW_OD", 411 "SPK_PA_EN", 412 "WLAN_PERST_1V8_L", 413 "WLAN_PD_1V8_L", 414 "WLAN_RF_KILL_1V8_L", 415 "BIGCPU_DVS_PWM", 416 "SD_CD_L_JTAG_EN", 417 418 /* GPIO0 B 0-5 */ 419 "BT_EN_BT_RF_KILL_1V8_L", 420 "PMUIO2_33_18_L_PP3300_S0_EN", 421 "TOUCH_RESET_L", 422 "AP_EC_WARM_RESET_REQ", 423 "PEN_RESET_L", 424 /* 425 * AP_FLASH_WP_L is crossystem ABI. Schematics call 426 * it AP_FLASH_WP_R_ODL. 427 */ 428 "AP_FLASH_WP_L"; 429}; 430 431&gpio1 { 432 gpio-line-names = /* GPIO1 A 0-7 */ 433 "PEN_INT_ODL", 434 "PEN_EJECT_ODL", 435 "BT_HOST_WAKE_1V8_L", 436 "WLAN_HOST_WAKE_1V8_L", 437 "TOUCH_INT_ODL", 438 "AP_EC_S3_S0_L", 439 "AP_EC_OVERTEMP", 440 "AP_SPI_FLASH_MISO", 441 442 /* GPIO1 B 0-7 */ 443 "AP_SPI_FLASH_MOSI_R", 444 "AP_SPI_FLASH_CLK_R", 445 "AP_SPI_FLASH_CS_L_R", 446 "SD_CARD_DET_ODL", 447 "", 448 "AP_EXPANSION_IO1", 449 "AP_EXPANSION_IO2", 450 "AP_I2C_DISP_SDA", 451 452 /* GPIO1 C 0-7 */ 453 "AP_I2C_DISP_SCL", 454 "H1_INT_ODL", 455 "EC_AP_INT_ODL", 456 "LITCPU_DVS_PWM", 457 "AP_I2C_AUDIO_SDA", 458 "AP_I2C_AUDIO_SCL", 459 "AP_EXPANSION_IO3", 460 "HEADSET_INT_ODL", 461 462 /* GPIO1 D0 */ 463 "AP_EXPANSION_IO4"; 464}; 465 466&gpio2 { 467 gpio-line-names = /* GPIO2 A 0-7 */ 468 "AP_I2C_PEN_SDA", 469 "AP_I2C_PEN_SCL", 470 "SD_IO_PWR_EN", 471 "UCAM_RST_L", 472 "PP1250_CAM_EN", 473 "WCAM_RST_L", 474 "AP_EXPANSION_IO5", 475 "AP_I2C_CAM_SDA", 476 477 /* GPIO2 B 0-7 */ 478 "AP_I2C_CAM_SCL", 479 "AP_H1_SPI_MISO", 480 "AP_H1_SPI_MOSI", 481 "AP_H1_SPI_CLK", 482 "AP_H1_SPI_CS_L", 483 "", 484 "", 485 "", 486 487 /* GPIO2 C 0-7 */ 488 "UART_EXPANSION_TX_AP_RX", 489 "UART_AP_TX_EXPANSION_RX", 490 "UART_EXPANSION_RTS_AP_CTS", 491 "UART_AP_RTS_EXPANSION_CTS", 492 "AP_SPI_EC_MISO", 493 "AP_SPI_EC_MOSI", 494 "AP_SPI_EC_CLK", 495 "AP_SPI_EC_CS_L", 496 497 /* GPIO2 D 0-4 */ 498 "PP2800_CAM_EN", 499 "CLK_24M_CAM", 500 "WLAN_PCIE_CLKREQ_1V8_L", 501 "", 502 "SD_PWR_3000_1800_L"; 503}; 504 505&gpio3 { 506 gpio-line-names = /* GPIO3 A 0-7 */ 507 "", 508 "", 509 "", 510 "", 511 "", 512 "", 513 "", 514 "", 515 516 /* GPIO3 B 0-7 */ 517 "", 518 "", 519 "", 520 "", 521 "", 522 "", 523 "", 524 "", 525 526 /* GPIO3 C 0-7 */ 527 "", 528 "", 529 "", 530 "", 531 "", 532 "", 533 "", 534 "", 535 536 /* GPIO3 D 0-7 */ 537 "I2S0_SCLK", 538 "I2S0_LRCK_RX", 539 "I2S0_LRCK_TX", 540 "I2S0_SDI_0", 541 "STRAP_LCDBIAS_L", 542 "STRAP_FEATURE_1", 543 "STRAP_FEATURE_2", 544 "I2S0_SDO_0"; 545}; 546 547&gpio4 { 548 gpio-line-names = /* GPIO4 A 0-7 */ 549 "I2S_MCLK", 550 "AP_I2C_EXPANSION_SDA", 551 "AP_I2C_EXPANSION_SCL", 552 "DMIC_EN", 553 "", 554 "", 555 "", 556 "", 557 558 /* GPIO4 B 0-7 */ 559 "", 560 "", 561 "", 562 "", 563 "", 564 "", 565 "", 566 "", 567 568 /* GPIO4 C 0-7 */ 569 "AP_I2C_TS_SDA", 570 "AP_I2C_TS_SCL", 571 "GPU_DVS_PWM", 572 "UART_DBG_TX_AP_RX", 573 "UART_AP_TX_DBG_RX", 574 "BL_EN", 575 "BL_PWM", 576 "", 577 578 /* GPIO4 D 0-5 */ 579 "", 580 "DISPLAY_RST_L", 581 "", 582 "PPVARP_LCD_EN", 583 "PPVARN_LCD_EN", 584 "SD_SLOT_PWR_EN"; 585}; 586 587&i2c_tunnel { 588 google,remote-bus = <0>; 589}; 590 591&io_domains { 592 bt656-supply = <&pp1800_s0>; /* APIO2_VDD; 2a 2b */ 593 audio-supply = <&pp1800_s0>; /* APIO5_VDD; 3d 4a */ 594 gpio1830-supply = <&pp1800_s0>; /* APIO4_VDD; 4c 4d */ 595}; 596 597&isp0 { 598 status = "okay"; 599 600 ports { 601 port@0 { 602 mipi_in_wcam: endpoint@0 { 603 reg = <0>; 604 remote-endpoint = <&wcam_out>; 605 data-lanes = <1 2>; 606 }; 607 608 mipi_in_ucam: endpoint@1 { 609 reg = <1>; 610 remote-endpoint = <&ucam_out>; 611 data-lanes = <1>; 612 }; 613 }; 614 }; 615}; 616 617&isp0_mmu { 618 status = "okay"; 619}; 620 621&max98357a { 622 sdmode-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; 623}; 624 625&mipi_dphy_rx0 { 626 status = "okay"; 627}; 628 629&mipi_dsi { 630 status = "okay"; 631 clock-master; 632 633 ports { 634 mipi_out: port@1 { 635 reg = <1>; 636 637 mipi_out_panel: endpoint { 638 remote-endpoint = <&mipi_in_panel>; 639 }; 640 }; 641 }; 642 643 mipi_panel: panel@0 { 644 /* 2 different panels are used, compatibles are in dts files */ 645 reg = <0>; 646 backlight = <&backlight>; 647 enable-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; 648 pinctrl-names = "default"; 649 pinctrl-0 = <&display_rst_l>; 650 651 ports { 652 #address-cells = <1>; 653 #size-cells = <0>; 654 655 port@0 { 656 reg = <0>; 657 658 mipi_in_panel: endpoint { 659 remote-endpoint = <&mipi_out_panel>; 660 }; 661 }; 662 663 port@1 { 664 reg = <1>; 665 666 mipi1_in_panel: endpoint@1 { 667 remote-endpoint = <&mipi1_out_panel>; 668 }; 669 }; 670 }; 671 }; 672}; 673 674&mipi_dsi1 { 675 status = "okay"; 676 677 ports { 678 mipi1_out: port@1 { 679 reg = <1>; 680 681 mipi1_out_panel: endpoint { 682 remote-endpoint = <&mipi1_in_panel>; 683 }; 684 }; 685 }; 686}; 687 688&pcie0 { 689 ep-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; 690 691 /* PERST# asserted in S3 */ 692 pcie-reset-suspend = <1>; 693 694 vpcie3v3-supply = <&wlan_3v3>; 695 vpcie1v8-supply = <&pp1800_pcie>; 696}; 697 698&sdmmc { 699 cd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 700}; 701 702&sound { 703 rockchip,codec = <&max98357a &dmic &codec &cdn_dp>; 704}; 705 706&spi2 { 707 status = "okay"; 708 709 cr50@0 { 710 compatible = "google,cr50"; 711 reg = <0>; 712 interrupt-parent = <&gpio1>; 713 interrupts = <17 IRQ_TYPE_EDGE_RISING>; 714 pinctrl-names = "default"; 715 pinctrl-0 = <&h1_int_od_l>; 716 spi-max-frequency = <800000>; 717 }; 718}; 719 720&usb_host0_ohci { 721 #address-cells = <1>; 722 #size-cells = <0>; 723 724 qca_bt: bluetooth@1 { 725 compatible = "usbcf3,e300", "usb4ca,301a"; 726 reg = <1>; 727 pinctrl-names = "default"; 728 pinctrl-0 = <&bt_host_wake_l>; 729 interrupt-parent = <&gpio1>; 730 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 731 interrupt-names = "wakeup"; 732 }; 733}; 734 735/* PINCTRL OVERRIDES */ 736&ap_fw_wp { 737 rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 738}; 739 740&bl_en { 741 rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; 742}; 743 744&bt_host_wake_l { 745 rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; 746}; 747 748&ec_ap_int_l { 749 rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; 750}; 751 752&headset_int_l { 753 rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; 754}; 755 756&i2s0_8ch_bus { 757 rockchip,pins = 758 <3 RK_PD0 1 &pcfg_pull_none_6ma>, 759 <3 RK_PD1 1 &pcfg_pull_none_6ma>, 760 <3 RK_PD2 1 &pcfg_pull_none_6ma>, 761 <3 RK_PD3 1 &pcfg_pull_none_6ma>, 762 <3 RK_PD7 1 &pcfg_pull_none_6ma>, 763 <4 RK_PA0 1 &pcfg_pull_none_6ma>; 764}; 765 766&i2s0_8ch_bus_bclk_off { 767 rockchip,pins = 768 <3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none_6ma>, 769 <3 RK_PD1 1 &pcfg_pull_none_6ma>, 770 <3 RK_PD2 1 &pcfg_pull_none_6ma>, 771 <3 RK_PD3 1 &pcfg_pull_none_6ma>, 772 <3 RK_PD7 1 &pcfg_pull_none_6ma>, 773 <4 RK_PA0 1 &pcfg_pull_none_6ma>; 774}; 775 776/* there is no external pull up, so need to set this pin pull up */ 777&sdmmc_cd_pin { 778 rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; 779}; 780 781&sd_pwr_1800_sel { 782 rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; 783}; 784 785&sdmode_en { 786 rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>; 787}; 788 789&touch_reset_l { 790 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; 791}; 792 793&touch_int_l { 794 rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; 795}; 796 797&pinctrl { 798 pinctrl-0 = < 799 &ap_pwroff /* AP will auto-assert this when in S3 */ 800 &clk_32k /* This pin is always 32k on gru boards */ 801 &wlan_rf_kill_1v8_l 802 >; 803 804 pcfg_pull_none_6ma: pcfg-pull-none-6ma { 805 bias-disable; 806 drive-strength = <6>; 807 }; 808 809 camera { 810 pp1250_cam_en: pp1250-dvdd { 811 rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 812 }; 813 814 pp2800_cam_en: pp2800-avdd { 815 rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 816 }; 817 818 ucam_rst: ucam_rst { 819 rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 820 }; 821 822 wcam_rst: wcam_rst { 823 rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 824 }; 825 }; 826 827 digitizer { 828 pen_int_odl: pen-int-odl { 829 rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; 830 }; 831 832 pen_reset_l: pen-reset-l { 833 rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; 834 }; 835 }; 836 837 discrete-regulators { 838 display_rst_l: display-rst-l { 839 rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_down>; 840 }; 841 842 ppvarp_lcd_en: ppvarp-lcd-en { 843 rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 844 }; 845 846 ppvarn_lcd_en: ppvarn-lcd-en { 847 rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; 848 }; 849 }; 850 851 dmic { 852 dmic_en: dmic-en { 853 rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 854 }; 855 }; 856 857 pen { 858 pen_eject_odl: pen-eject-odl { 859 rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; 860 }; 861 }; 862 863 tpm { 864 h1_int_od_l: h1-int-od-l { 865 rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; 866 }; 867 }; 868}; 869 870&wifi { 871 bt_en_1v8_l: bt-en-1v8-l { 872 rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 873 }; 874 875 wlan_pd_1v8_l: wlan-pd-1v8-l { 876 rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 877 }; 878 879 /* Default pull-up, but just to be clear */ 880 wlan_rf_kill_1v8_l: wlan-rf-kill-1v8-l { 881 rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; 882 }; 883 884 wifi_perst_l: wifi-perst-l { 885 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 886 }; 887 888 wlan_host_wake_l: wlan-host-wake-l { 889 rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 890 }; 891}; 892