1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Google Gru-scarlet board device tree source 4 * 5 * Copyright 2018 Google, Inc 6 */ 7 8#include "rk3399-gru.dtsi" 9 10/{ 11 chassis-type = "tablet"; 12 13 /* Power tree */ 14 15 /* ppvar_sys children, sorted by name */ 16 pp1250_s3: pp1250-s3 { 17 compatible = "regulator-fixed"; 18 regulator-name = "pp1250_s3"; 19 20 /* EC turns on w/ pp1250_s3_en; always on for AP */ 21 regulator-always-on; 22 regulator-boot-on; 23 regulator-min-microvolt = <1250000>; 24 regulator-max-microvolt = <1250000>; 25 26 vin-supply = <&ppvar_sys>; 27 }; 28 29 pp1250_cam: pp1250-dvdd { 30 compatible = "regulator-fixed"; 31 regulator-name = "pp1250_dvdd"; 32 pinctrl-names = "default"; 33 pinctrl-0 = <&pp1250_cam_en>; 34 35 enable-active-high; 36 gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>; 37 38 /* 740us delay from gpio output high to pp1250 stable, 39 * rounding up to 1ms for safety. 40 */ 41 startup-delay-us = <1000>; 42 vin-supply = <&pp1250_s3>; 43 }; 44 45 pp900_s0: pp900-s0 { 46 compatible = "regulator-fixed"; 47 regulator-name = "pp900_s0"; 48 49 /* EC turns on w/ pp900_s0_en; always on for AP */ 50 regulator-always-on; 51 regulator-boot-on; 52 regulator-min-microvolt = <900000>; 53 regulator-max-microvolt = <900000>; 54 55 vin-supply = <&ppvar_sys>; 56 }; 57 58 ppvarn_lcd: ppvarn-lcd { 59 compatible = "regulator-fixed"; 60 regulator-name = "ppvarn_lcd"; 61 pinctrl-names = "default"; 62 pinctrl-0 = <&ppvarn_lcd_en>; 63 64 enable-active-high; 65 gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; 66 vin-supply = <&ppvar_sys>; 67 }; 68 69 ppvarp_lcd: ppvarp-lcd { 70 compatible = "regulator-fixed"; 71 regulator-name = "ppvarp_lcd"; 72 pinctrl-names = "default"; 73 pinctrl-0 = <&ppvarp_lcd_en>; 74 75 enable-active-high; 76 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 77 vin-supply = <&ppvar_sys>; 78 }; 79 80 /* pp1800 children, sorted by name */ 81 pp900_s3: pp900-s3 { 82 compatible = "regulator-fixed"; 83 regulator-name = "pp900_s3"; 84 85 /* EC turns on w/ pp900_s3_en; always on for AP */ 86 regulator-always-on; 87 regulator-boot-on; 88 regulator-min-microvolt = <900000>; 89 regulator-max-microvolt = <900000>; 90 91 vin-supply = <&pp1800>; 92 }; 93 94 /* EC turns on pp1800_s3_en */ 95 pp1800_s3: pp1800 { 96 }; 97 98 /* pp3300 children, sorted by name */ 99 pp2800_cam: pp2800-avdd { 100 compatible = "regulator-fixed"; 101 regulator-name = "pp2800_avdd"; 102 pinctrl-names = "default"; 103 pinctrl-0 = <&pp2800_cam_en>; 104 105 enable-active-high; 106 gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>; 107 startup-delay-us = <100>; 108 vin-supply = <&pp3300>; 109 }; 110 111 /* EC turns on pp3300_s0_en */ 112 pp3300_s0: pp3300 { 113 }; 114 115 /* EC turns on pp3300_s3_en */ 116 pp3300_s3: pp3300 { 117 }; 118 119 /* 120 * See b/66922012 121 * 122 * This is a hack to make sure the Bluetooth part of the QCA6174A 123 * is reset at boot by toggling BT_EN. At boot BT_EN is first set 124 * to low when the bt_3v3 regulator is registered (in disabled 125 * state). The fake regulator is configured as a supply of the 126 * wlan_3v3 regulator below. When wlan_3v3 is enabled early in 127 * the boot process it also enables its supply regulator bt_3v3, 128 * which changes BT_EN to high. 129 */ 130 bt_3v3: bt-3v3 { 131 compatible = "regulator-fixed"; 132 regulator-name = "bt_3v3"; 133 pinctrl-names = "default"; 134 pinctrl-0 = <&bt_en_1v8_l>; 135 136 enable-active-high; 137 gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>; 138 vin-supply = <&pp3300_s3>; 139 }; 140 141 wlan_3v3: wlan-3v3 { 142 compatible = "regulator-fixed"; 143 regulator-name = "wlan_3v3"; 144 pinctrl-names = "default"; 145 pinctrl-0 = <&wlan_pd_1v8_l>; 146 147 /* 148 * The WL_EN pin is driven low when the regulator is 149 * registered, and transitions to high when the PCIe bus 150 * is powered up. 151 */ 152 enable-active-high; 153 gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; 154 155 /* 156 * Require minimum 10ms from power-on (e.g., PD#) to init PCIe. 157 * TODO (b/64444991): how long to assert PD#? 158 */ 159 regulator-enable-ramp-delay = <10000>; 160 /* See bt_3v3 hack above */ 161 vin-supply = <&bt_3v3>; 162 }; 163 164 backlight: backlight { 165 compatible = "pwm-backlight"; 166 enable-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; 167 pinctrl-names = "default"; 168 pinctrl-0 = <&bl_en>; 169 pwms = <&pwm1 0 1000000 0>; 170 pwm-delay-us = <10000>; 171 }; 172 173 dmic: dmic { 174 compatible = "dmic-codec"; 175 dmicen-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; 176 pinctrl-names = "default"; 177 pinctrl-0 = <&dmic_en>; 178 wakeup-delay-ms = <250>; 179 }; 180 181 gpio_keys: gpio-keys { 182 compatible = "gpio-keys"; 183 pinctrl-names = "default"; 184 pinctrl-0 = <&pen_eject_odl>; 185 186 pen-insert { 187 label = "Pen Insert"; 188 /* Insert = low, eject = high */ 189 gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; 190 linux,code = <SW_PEN_INSERTED>; 191 linux,input-type = <EV_SW>; 192 wakeup-source; 193 }; 194 }; 195}; 196 197/* pp900_s0 aliases */ 198pp900_ddrpll_ap: &pp900_s0 { 199}; 200pp900_pcie: &pp900_s0 { 201}; 202pp900_usb: &pp900_s0 { 203}; 204 205/* pp900_s3 aliases */ 206pp900_emmcpll: &pp900_s3 { 207}; 208 209/* EC turns on; alias for pp1800_s0 */ 210pp1800_pcie: &pp1800_s0 { 211}; 212 213/* On scarlet PPVAR(big_cpu, lit_cpu, gpu) need to adjust voltage ranges */ 214&ppvar_bigcpu { 215 ctrl-voltage-range = <800074 1299226>; 216 regulator-min-microvolt = <800074>; 217 regulator-max-microvolt = <1299226>; 218}; 219 220&ppvar_bigcpu_pwm { 221 /* On scarlet ppvar big cpu use pwm3 */ 222 pwms = <&pwm3 0 3337 0>; 223 regulator-min-microvolt = <800074>; 224 regulator-max-microvolt = <1299226>; 225}; 226 227&ppvar_litcpu { 228 ctrl-voltage-range = <802122 1199620>; 229 regulator-min-microvolt = <802122>; 230 regulator-max-microvolt = <1199620>; 231}; 232 233&ppvar_litcpu_pwm { 234 regulator-min-microvolt = <802122>; 235 regulator-max-microvolt = <1199620>; 236}; 237 238&ppvar_gpu { 239 ctrl-voltage-range = <799600 1099600>; 240 regulator-min-microvolt = <799600>; 241 regulator-max-microvolt = <1099600>; 242}; 243 244&ppvar_gpu_pwm { 245 regulator-min-microvolt = <799600>; 246 regulator-max-microvolt = <1099600>; 247}; 248 249&ppvar_sd_card_io { 250 states = <1800000 0x0>, <3300000 0x1>; 251 regulator-max-microvolt = <3300000>; 252}; 253 254&pp3000_sd_slot { 255 vin-supply = <&pp3300>; 256}; 257 258ap_i2c_dig: &i2c2 { 259 status = "okay"; 260 261 clock-frequency = <400000>; 262 263 /* These are relatively safe rise/fall times. */ 264 i2c-scl-falling-time-ns = <50>; 265 i2c-scl-rising-time-ns = <300>; 266 267 digitizer: digitizer@9 { 268 compatible = "hid-over-i2c"; 269 reg = <0x9>; 270 interrupt-parent = <&gpio1>; 271 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 272 hid-descr-addr = <0x1>; 273 pinctrl-names = "default"; 274 pinctrl-0 = <&pen_int_odl &pen_reset_l>; 275 }; 276}; 277 278&ap_i2c_ts { 279 touchscreen: touchscreen@10 { 280 compatible = "elan,ekth3500"; 281 reg = <0x10>; 282 interrupt-parent = <&gpio1>; 283 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 284 pinctrl-names = "default"; 285 pinctrl-0 = <&touch_int_l &touch_reset_l>; 286 reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; 287 }; 288}; 289 290camera: &i2c7 { 291 status = "okay"; 292 293 clock-frequency = <400000>; 294 295 /* These are relatively safe rise/fall times; TODO: measure */ 296 i2c-scl-falling-time-ns = <50>; 297 i2c-scl-rising-time-ns = <300>; 298 299 /* 24M mclk is shared between world and user cameras */ 300 pinctrl-0 = <&i2c7_xfer &test_clkout1>; 301 302 /* Rear-facing camera */ 303 wcam: camera@36 { 304 compatible = "ovti,ov5695"; 305 reg = <0x36>; 306 pinctrl-names = "default"; 307 pinctrl-0 = <&wcam_rst>; 308 309 clocks = <&cru SCLK_TESTCLKOUT1>; 310 clock-names = "xvclk"; 311 312 avdd-supply = <&pp2800_cam>; 313 dvdd-supply = <&pp1250_cam>; 314 dovdd-supply = <&pp1800_s0>; 315 reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; 316 317 port { 318 wcam_out: endpoint { 319 remote-endpoint = <&mipi_in_wcam>; 320 data-lanes = <1 2>; 321 }; 322 }; 323 }; 324 325 /* Front-facing camera */ 326 ucam: camera@3c { 327 compatible = "ovti,ov2685"; 328 reg = <0x3c>; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&ucam_rst>; 331 332 clocks = <&cru SCLK_TESTCLKOUT1>; 333 clock-names = "xvclk"; 334 335 avdd-supply = <&pp2800_cam>; 336 dovdd-supply = <&pp1800_s0>; 337 dvdd-supply = <&pp1800_s0>; 338 reset-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; 339 340 port { 341 ucam_out: endpoint { 342 remote-endpoint = <&mipi_in_ucam>; 343 data-lanes = <1>; 344 }; 345 }; 346 }; 347}; 348 349&cdn_dp { 350 extcon = <&usbc_extcon0>; 351 phys = <&tcphy0_dp>; 352}; 353 354&cpu_alert0 { 355 temperature = <66000>; 356}; 357 358&cpu_alert1 { 359 temperature = <71000>; 360}; 361 362&cros_ec { 363 interrupt-parent = <&gpio1>; 364 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 365}; 366 367&cru { 368 assigned-clocks = 369 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 370 <&cru PLL_NPLL>, 371 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>, 372 <&cru PCLK_PERIHP>, 373 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>, 374 <&cru PCLK_PERILP0>, <&cru ACLK_CCI>, 375 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>, 376 <&cru ACLK_VIO>, 377 <&cru ACLK_GIC_PRE>, 378 <&cru PCLK_DDR>, 379 <&cru ACLK_HDCP>; 380 assigned-clock-rates = 381 <600000000>, <1600000000>, 382 <1000000000>, 383 <150000000>, <75000000>, 384 <37500000>, 385 <100000000>, <100000000>, 386 <50000000>, <800000000>, 387 <100000000>, <50000000>, 388 <400000000>, 389 <200000000>, 390 <200000000>, 391 <400000000>; 392}; 393 394&gpio0 { 395 gpio-line-names = /* GPIO0 A 0-7 */ 396 "CLK_32K_AP", 397 "EC_IN_RW_OD", 398 "SPK_PA_EN", 399 "WLAN_PERST_1V8_L", 400 "WLAN_PD_1V8_L", 401 "WLAN_RF_KILL_1V8_L", 402 "BIGCPU_DVS_PWM", 403 "SD_CD_L_JTAG_EN", 404 405 /* GPIO0 B 0-5 */ 406 "BT_EN_BT_RF_KILL_1V8_L", 407 "PMUIO2_33_18_L_PP3300_S0_EN", 408 "TOUCH_RESET_L", 409 "AP_EC_WARM_RESET_REQ", 410 "PEN_RESET_L", 411 /* 412 * AP_FLASH_WP_L is crossystem ABI. Schematics call 413 * it AP_FLASH_WP_R_ODL. 414 */ 415 "AP_FLASH_WP_L"; 416}; 417 418&gpio1 { 419 gpio-line-names = /* GPIO1 A 0-7 */ 420 "PEN_INT_ODL", 421 "PEN_EJECT_ODL", 422 "BT_HOST_WAKE_1V8_L", 423 "WLAN_HOST_WAKE_1V8_L", 424 "TOUCH_INT_ODL", 425 "AP_EC_S3_S0_L", 426 "AP_EC_OVERTEMP", 427 "AP_SPI_FLASH_MISO", 428 429 /* GPIO1 B 0-7 */ 430 "AP_SPI_FLASH_MOSI_R", 431 "AP_SPI_FLASH_CLK_R", 432 "AP_SPI_FLASH_CS_L_R", 433 "SD_CARD_DET_ODL", 434 "", 435 "AP_EXPANSION_IO1", 436 "AP_EXPANSION_IO2", 437 "AP_I2C_DISP_SDA", 438 439 /* GPIO1 C 0-7 */ 440 "AP_I2C_DISP_SCL", 441 "H1_INT_ODL", 442 "EC_AP_INT_ODL", 443 "LITCPU_DVS_PWM", 444 "AP_I2C_AUDIO_SDA", 445 "AP_I2C_AUDIO_SCL", 446 "AP_EXPANSION_IO3", 447 "HEADSET_INT_ODL", 448 449 /* GPIO1 D0 */ 450 "AP_EXPANSION_IO4"; 451}; 452 453&gpio2 { 454 gpio-line-names = /* GPIO2 A 0-7 */ 455 "AP_I2C_PEN_SDA", 456 "AP_I2C_PEN_SCL", 457 "SD_IO_PWR_EN", 458 "UCAM_RST_L", 459 "PP1250_CAM_EN", 460 "WCAM_RST_L", 461 "AP_EXPANSION_IO5", 462 "AP_I2C_CAM_SDA", 463 464 /* GPIO2 B 0-7 */ 465 "AP_I2C_CAM_SCL", 466 "AP_H1_SPI_MISO", 467 "AP_H1_SPI_MOSI", 468 "AP_H1_SPI_CLK", 469 "AP_H1_SPI_CS_L", 470 "", 471 "", 472 "", 473 474 /* GPIO2 C 0-7 */ 475 "UART_EXPANSION_TX_AP_RX", 476 "UART_AP_TX_EXPANSION_RX", 477 "UART_EXPANSION_RTS_AP_CTS", 478 "UART_AP_RTS_EXPANSION_CTS", 479 "AP_SPI_EC_MISO", 480 "AP_SPI_EC_MOSI", 481 "AP_SPI_EC_CLK", 482 "AP_SPI_EC_CS_L", 483 484 /* GPIO2 D 0-4 */ 485 "PP2800_CAM_EN", 486 "CLK_24M_CAM", 487 "WLAN_PCIE_CLKREQ_1V8_L", 488 "", 489 "SD_PWR_3000_1800_L"; 490}; 491 492&gpio3 { 493 gpio-line-names = /* GPIO3 A 0-7 */ 494 "", 495 "", 496 "", 497 "", 498 "", 499 "", 500 "", 501 "", 502 503 /* GPIO3 B 0-7 */ 504 "", 505 "", 506 "", 507 "", 508 "", 509 "", 510 "", 511 "", 512 513 /* GPIO3 C 0-7 */ 514 "", 515 "", 516 "", 517 "", 518 "", 519 "", 520 "", 521 "", 522 523 /* GPIO3 D 0-7 */ 524 "I2S0_SCLK", 525 "I2S0_LRCK_RX", 526 "I2S0_LRCK_TX", 527 "I2S0_SDI_0", 528 "STRAP_LCDBIAS_L", 529 "STRAP_FEATURE_1", 530 "STRAP_FEATURE_2", 531 "I2S0_SDO_0"; 532}; 533 534&gpio4 { 535 gpio-line-names = /* GPIO4 A 0-7 */ 536 "I2S_MCLK", 537 "AP_I2C_EXPANSION_SDA", 538 "AP_I2C_EXPANSION_SCL", 539 "DMIC_EN", 540 "", 541 "", 542 "", 543 "", 544 545 /* GPIO4 B 0-7 */ 546 "", 547 "", 548 "", 549 "", 550 "", 551 "", 552 "", 553 "", 554 555 /* GPIO4 C 0-7 */ 556 "AP_I2C_TS_SDA", 557 "AP_I2C_TS_SCL", 558 "GPU_DVS_PWM", 559 "UART_DBG_TX_AP_RX", 560 "UART_AP_TX_DBG_RX", 561 "BL_EN", 562 "BL_PWM", 563 "", 564 565 /* GPIO4 D 0-5 */ 566 "", 567 "DISPLAY_RST_L", 568 "", 569 "PPVARP_LCD_EN", 570 "PPVARN_LCD_EN", 571 "SD_SLOT_PWR_EN"; 572}; 573 574&i2c_tunnel { 575 google,remote-bus = <0>; 576}; 577 578&io_domains { 579 bt656-supply = <&pp1800_s0>; /* APIO2_VDD; 2a 2b */ 580 audio-supply = <&pp1800_s0>; /* APIO5_VDD; 3d 4a */ 581 gpio1830-supply = <&pp1800_s0>; /* APIO4_VDD; 4c 4d */ 582}; 583 584&isp0 { 585 status = "okay"; 586 587 ports { 588 port@0 { 589 mipi_in_wcam: endpoint@0 { 590 reg = <0>; 591 remote-endpoint = <&wcam_out>; 592 data-lanes = <1 2>; 593 }; 594 595 mipi_in_ucam: endpoint@1 { 596 reg = <1>; 597 remote-endpoint = <&ucam_out>; 598 data-lanes = <1>; 599 }; 600 }; 601 }; 602}; 603 604&isp0_mmu { 605 status = "okay"; 606}; 607 608&max98357a { 609 sdmode-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>; 610}; 611 612&mipi_dphy_rx0 { 613 status = "okay"; 614}; 615 616&mipi_dsi { 617 status = "okay"; 618 clock-master; 619 620 ports { 621 mipi_out: port@1 { 622 reg = <1>; 623 624 mipi_out_panel: endpoint { 625 remote-endpoint = <&mipi_in_panel>; 626 }; 627 }; 628 }; 629 630 mipi_panel: panel@0 { 631 /* 2 different panels are used, compatibles are in dts files */ 632 reg = <0>; 633 backlight = <&backlight>; 634 enable-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; 635 pinctrl-names = "default"; 636 pinctrl-0 = <&display_rst_l>; 637 638 ports { 639 #address-cells = <1>; 640 #size-cells = <0>; 641 642 port@0 { 643 reg = <0>; 644 645 mipi_in_panel: endpoint { 646 remote-endpoint = <&mipi_out_panel>; 647 }; 648 }; 649 650 port@1 { 651 reg = <1>; 652 653 mipi1_in_panel: endpoint@1 { 654 remote-endpoint = <&mipi1_out_panel>; 655 }; 656 }; 657 }; 658 }; 659}; 660 661&mipi_dsi1 { 662 status = "okay"; 663 664 ports { 665 mipi1_out: port@1 { 666 reg = <1>; 667 668 mipi1_out_panel: endpoint { 669 remote-endpoint = <&mipi1_in_panel>; 670 }; 671 }; 672 }; 673}; 674 675&pcie0 { 676 ep-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>; 677 678 /* PERST# asserted in S3 */ 679 pcie-reset-suspend = <1>; 680 681 vpcie3v3-supply = <&wlan_3v3>; 682 vpcie1v8-supply = <&pp1800_pcie>; 683}; 684 685&sdmmc { 686 cd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 687}; 688 689&sound { 690 rockchip,codec = <&max98357a &dmic &codec &cdn_dp>; 691}; 692 693&spi2 { 694 status = "okay"; 695 696 cr50@0 { 697 compatible = "google,cr50"; 698 reg = <0>; 699 interrupt-parent = <&gpio1>; 700 interrupts = <17 IRQ_TYPE_EDGE_RISING>; 701 pinctrl-names = "default"; 702 pinctrl-0 = <&h1_int_od_l>; 703 spi-max-frequency = <800000>; 704 }; 705}; 706 707&usb_host0_ohci { 708 #address-cells = <1>; 709 #size-cells = <0>; 710 711 qca_bt: bluetooth@1 { 712 compatible = "usbcf3,e300", "usb4ca,301a"; 713 reg = <1>; 714 pinctrl-names = "default"; 715 pinctrl-0 = <&bt_host_wake_l>; 716 interrupt-parent = <&gpio1>; 717 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 718 interrupt-names = "wakeup"; 719 }; 720}; 721 722/* PINCTRL OVERRIDES */ 723&ec_ap_int_l { 724 rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; 725}; 726 727&ap_fw_wp { 728 rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 729}; 730 731&bl_en { 732 rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; 733}; 734 735&bt_host_wake_l { 736 rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; 737}; 738 739&ec_ap_int_l { 740 rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>; 741}; 742 743&headset_int_l { 744 rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; 745}; 746 747&i2s0_8ch_bus { 748 rockchip,pins = 749 <3 RK_PD0 1 &pcfg_pull_none_6ma>, 750 <3 RK_PD1 1 &pcfg_pull_none_6ma>, 751 <3 RK_PD2 1 &pcfg_pull_none_6ma>, 752 <3 RK_PD3 1 &pcfg_pull_none_6ma>, 753 <3 RK_PD7 1 &pcfg_pull_none_6ma>, 754 <4 RK_PA0 1 &pcfg_pull_none_6ma>; 755}; 756 757/* there is no external pull up, so need to set this pin pull up */ 758&sdmmc_cd_pin { 759 rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>; 760}; 761 762&sd_pwr_1800_sel { 763 rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; 764}; 765 766&sdmode_en { 767 rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>; 768}; 769 770&touch_reset_l { 771 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; 772}; 773 774&touch_int_l { 775 rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>; 776}; 777 778&pinctrl { 779 pinctrl-0 = < 780 &ap_pwroff /* AP will auto-assert this when in S3 */ 781 &clk_32k /* This pin is always 32k on gru boards */ 782 &wlan_rf_kill_1v8_l 783 >; 784 785 pcfg_pull_none_6ma: pcfg-pull-none-6ma { 786 bias-disable; 787 drive-strength = <6>; 788 }; 789 790 camera { 791 pp1250_cam_en: pp1250-dvdd { 792 rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 793 }; 794 795 pp2800_cam_en: pp2800-avdd { 796 rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 797 }; 798 799 ucam_rst: ucam_rst { 800 rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 801 }; 802 803 wcam_rst: wcam_rst { 804 rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 805 }; 806 }; 807 808 digitizer { 809 pen_int_odl: pen-int-odl { 810 rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; 811 }; 812 813 pen_reset_l: pen-reset-l { 814 rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; 815 }; 816 }; 817 818 discrete-regulators { 819 display_rst_l: display-rst-l { 820 rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_down>; 821 }; 822 823 ppvarp_lcd_en: ppvarp-lcd-en { 824 rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 825 }; 826 827 ppvarn_lcd_en: ppvarn-lcd-en { 828 rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>; 829 }; 830 }; 831 832 dmic { 833 dmic_en: dmic-en { 834 rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 835 }; 836 }; 837 838 pen { 839 pen_eject_odl: pen-eject-odl { 840 rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; 841 }; 842 }; 843 844 tpm { 845 h1_int_od_l: h1-int-od-l { 846 rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; 847 }; 848 }; 849}; 850 851&wifi { 852 bt_en_1v8_l: bt-en-1v8-l { 853 rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 854 }; 855 856 wlan_pd_1v8_l: wlan-pd-1v8-l { 857 rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 858 }; 859 860 /* Default pull-up, but just to be clear */ 861 wlan_rf_kill_1v8_l: wlan-rf-kill-1v8-l { 862 rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; 863 }; 864 865 wifi_perst_l: wifi-perst-l { 866 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 867 }; 868 869 wlan_host_wake_l: wlan-host-wake-l { 870 rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; 871 }; 872}; 873