1*5f62a964SEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2*5f62a964SEmmanuel Vadot/* 3*5f62a964SEmmanuel Vadot * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd. 4*5f62a964SEmmanuel Vadot * (http://www.friendlyarm.com) 5*5f62a964SEmmanuel Vadot * 6*5f62a964SEmmanuel Vadot * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com> 7*5f62a964SEmmanuel Vadot */ 8*5f62a964SEmmanuel Vadot 9*5f62a964SEmmanuel Vadot/dts-v1/; 10*5f62a964SEmmanuel Vadot 11*5f62a964SEmmanuel Vadot#include "rk3328-nanopi-r2.dtsi" 12*5f62a964SEmmanuel Vadot 13*5f62a964SEmmanuel Vadot&gmac2io { 14*5f62a964SEmmanuel Vadot phy-handle = <&yt8521s>; 15*5f62a964SEmmanuel Vadot tx_delay = <0x22>; 16*5f62a964SEmmanuel Vadot rx_delay = <0x12>; 17*5f62a964SEmmanuel Vadot status = "okay"; 18*5f62a964SEmmanuel Vadot 19*5f62a964SEmmanuel Vadot mdio { 20*5f62a964SEmmanuel Vadot yt8521s: ethernet-phy@3 { 21*5f62a964SEmmanuel Vadot compatible = "ethernet-phy-ieee802.3-c22"; 22*5f62a964SEmmanuel Vadot reg = <3>; 23*5f62a964SEmmanuel Vadot 24*5f62a964SEmmanuel Vadot motorcomm,clk-out-frequency-hz = <125000000>; 25*5f62a964SEmmanuel Vadot motorcomm,keep-pll-enabled; 26*5f62a964SEmmanuel Vadot motorcomm,auto-sleep-disabled; 27*5f62a964SEmmanuel Vadot 28*5f62a964SEmmanuel Vadot pinctrl-0 = <ð_phy_reset_pin>; 29*5f62a964SEmmanuel Vadot pinctrl-names = "default"; 30*5f62a964SEmmanuel Vadot reset-assert-us = <10000>; 31*5f62a964SEmmanuel Vadot reset-deassert-us = <50000>; 32*5f62a964SEmmanuel Vadot reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; 33*5f62a964SEmmanuel Vadot }; 34*5f62a964SEmmanuel Vadot }; 35*5f62a964SEmmanuel Vadot}; 36