xref: /freebsd/sys/contrib/device-tree/src/arm64/renesas/rzg3e-smarc-som.dtsi (revision ae5de77ed78ae54d86cead5604869212e8008e6b) 
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the R9A09G047E57 SMARC SoM board.
4 *
5 * Copyright (C) 2024 Renesas Electronics Corp.
6 */
7
8/*
9 * Please set the below switch position on the SoM and the corresponding macro
10 * on the board DTS:
11 *
12 * Switch position SYS.1, Macro SW_SD0_DEV_SEL:
13 *      0 - SD0 is connected to eMMC (default)
14 *      1 - SD0 is connected to uSD0 card
15 *
16 * Switch position SYS.5, Macro SW_LCD_EN:
17 *      0 - Select Misc. Signals routing
18 *      1 - Select LCD
19 *
20 * Switch position BOOT.6, Macro SW_PDM_EN:
21 *      0 - Select CAN routing
22 *      1 - Select PDM
23 */
24
25/ {
26	compatible = "renesas,rzg3e-smarcm", "renesas,r9a09g047e57", "renesas,r9a09g047";
27
28	aliases {
29		i2c2 = &i2c2;
30		mmc0 = &sdhi0;
31		mmc2 = &sdhi2;
32	};
33
34	memory@48000000 {
35		device_type = "memory";
36		/* First 128MB is reserved for secure area. */
37		reg = <0x0 0x48000000 0x0 0xf8000000>;
38	};
39
40	reg_1p8v: regulator-1p8v {
41		compatible = "regulator-fixed";
42		regulator-name = "fixed-1.8V";
43		regulator-min-microvolt = <1800000>;
44		regulator-max-microvolt = <1800000>;
45		regulator-boot-on;
46		regulator-always-on;
47	};
48
49	reg_3p3v: regulator-3p3v {
50		compatible = "regulator-fixed";
51		regulator-name = "fixed-3.3V";
52		regulator-min-microvolt = <3300000>;
53		regulator-max-microvolt = <3300000>;
54		regulator-boot-on;
55		regulator-always-on;
56	};
57
58	reg_vdd0p8v_others: regulator-vdd0p8v-others {
59		compatible = "regulator-fixed";
60
61		regulator-name = "fixed-0.8V";
62		regulator-min-microvolt = <800000>;
63		regulator-max-microvolt = <800000>;
64		regulator-boot-on;
65		regulator-always-on;
66	};
67
68	/* 32.768kHz crystal */
69	x3: x3-clock {
70		compatible = "fixed-clock";
71		#clock-cells = <0>;
72		clock-frequency = <32768>;
73	};
74};
75
76&audio_extal_clk {
77	clock-frequency = <48000000>;
78};
79
80&gpu {
81	status = "okay";
82	mali-supply = <&reg_vdd0p8v_others>;
83};
84
85&i2c2 {
86	pinctrl-0 = <&i2c2_pins>;
87	pinctrl-names = "default";
88	clock-frequency = <400000>;
89	status = "okay";
90
91	raa215300: pmic@12 {
92		compatible = "renesas,raa215300";
93		reg = <0x12>, <0x6f>;
94		reg-names = "main", "rtc";
95		clocks = <&x3>;
96		clock-names = "xin";
97
98		pinctrl-0 = <&rtc_irq_pin>;
99		pinctrl-names = "default";
100
101		interrupts-extended = <&pinctrl RZG3E_GPIO(S, 1) IRQ_TYPE_EDGE_FALLING>;
102	};
103};
104
105&pinctrl {
106	i2c2_pins: i2c {
107		pinmux = <RZG3E_PORT_PINMUX(3, 4, 1)>, /* SCL2 */
108			 <RZG3E_PORT_PINMUX(3, 5, 1)>; /* SDA2 */
109	};
110
111	rtc_irq_pin: rtc-irq {
112		pins = "PS1";
113		bias-pull-up;
114	};
115
116	sdhi0_emmc_pins: sd0-emmc {
117		sd0-ctrl {
118			pins = "SD0CLK", "SD0CMD";
119			renesas,output-impedance = <3>;
120		};
121
122		sd0-data {
123			pins = "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3",
124			       "SD0DAT4", "SD0DAT5", "SD0DAT6", "SD0DAT7";
125			renesas,output-impedance = <3>;
126		};
127
128		sd0-rst {
129			pins = "SD0RSTN";
130			renesas,output-impedance = <3>;
131		};
132	};
133
134	sdhi0_usd_pins: sd0-usd {
135		sd0-cd {
136			pinmux = <RZG3E_PORT_PINMUX(5, 0, 8)>;
137		};
138
139		sd0-ctrl {
140			pins = "SD0CLK", "SD0CMD";
141			renesas,output-impedance = <3>;
142		};
143
144		sd0-data {
145			pins = "SD0DAT0", "SD0DAT1", "SD0DAT2", "SD0DAT3";
146			renesas,output-impedance = <3>;
147		};
148
149		sd0-iovs {
150			pins = "SD0IOVS";
151			renesas,output-impedance = <3>;
152		};
153
154		sd0-pwen {
155			pins = "SD0PWEN";
156			renesas,output-impedance = <3>;
157		};
158	};
159
160	sdhi2_pins: sd2 {
161		sd2-cd {
162			pinmux = <RZG3E_PORT_PINMUX(K, 0, 1)>; /* SD2CD */
163		};
164
165		sd2-ctrl {
166			pinmux = <RZG3E_PORT_PINMUX(H, 0, 1)>, /* SD2CLK */
167				 <RZG3E_PORT_PINMUX(H, 1, 1)>; /* SD2CMD */
168		};
169
170		sd2-data {
171			pinmux = <RZG3E_PORT_PINMUX(H, 2, 1)>, /* SD2DAT0 */
172				 <RZG3E_PORT_PINMUX(H, 3, 1)>, /* SD2DAT1 */
173				 <RZG3E_PORT_PINMUX(H, 4, 1)>, /* SD2DAT2 */
174				 <RZG3E_PORT_PINMUX(H, 5, 1)>; /* SD2DAT3 */
175		};
176
177		sd2-iovs {
178			pinmux = <RZG3E_PORT_PINMUX(K, 1, 1)>; /* SD2IOVS */
179		};
180
181		sd2-pwen {
182			pinmux = <RZG3E_PORT_PINMUX(K, 2, 1)>; /* SD2PWEN */
183		};
184	};
185};
186
187&qextal_clk {
188	clock-frequency = <24000000>;
189};
190
191&rtxin_clk {
192	clock-frequency = <32768>;
193};
194
195#if (SW_SD0_DEV_SEL)
196&sdhi0 {
197	pinctrl-0 = <&sdhi0_usd_pins>;
198	pinctrl-1 = <&sdhi0_usd_pins>;
199	pinctrl-names = "default", "state_uhs";
200
201	vmmc-supply = <&reg_3p3v>;
202	vqmmc-supply = <&sdhi0_vqmmc>;
203	bus-width = <4>;
204	sd-uhs-sdr50;
205	sd-uhs-sdr104;
206	status = "okay";
207};
208
209&sdhi0_vqmmc {
210	status = "okay";
211};
212#else
213&sdhi0 {
214	pinctrl-0 = <&sdhi0_emmc_pins>;
215	pinctrl-1 = <&sdhi0_emmc_pins>;
216	pinctrl-names = "default", "state_uhs";
217
218	vmmc-supply = <&reg_3p3v>;
219	vqmmc-supply = <&reg_1p8v>;
220	bus-width = <8>;
221	mmc-hs200-1_8v;
222	non-removable;
223	fixed-emmc-driver-type = <1>;
224	status = "okay";
225};
226#endif
227
228&sdhi2 {
229	pinctrl-0 = <&sdhi2_pins>;
230	pinctrl-1 = <&sdhi2_pins>;
231	pinctrl-names = "default", "state_uhs";
232
233	vmmc-supply = <&reg_3p3v>;
234	vqmmc-supply = <&sdhi2_vqmmc>;
235	bus-width = <4>;
236	sd-uhs-sdr50;
237	sd-uhs-sdr104;
238	status = "okay";
239};
240
241&sdhi2_vqmmc {
242	status = "okay";
243};
244
245&wdt1 {
246	status = "okay";
247};
248