xref: /freebsd/sys/contrib/device-tree/src/arm64/renesas/rzg2ul-smarc-som.dtsi (revision b97ee269eae3cbaf35c18f51a459aea581c2a7dc) 
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SMARC SOM common parts
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
10
11/ {
12	aliases {
13		ethernet0 = &eth0;
14		ethernet1 = &eth1;
15	};
16
17	chosen {
18		bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
19	};
20
21	memory@48000000 {
22		device_type = "memory";
23		/* first 128MB is reserved for secure area. */
24		reg = <0x0 0x48000000 0x0 0x38000000>;
25	};
26
27	reg_1p8v: regulator-1p8v {
28		compatible = "regulator-fixed";
29		regulator-name = "fixed-1.8V";
30		regulator-min-microvolt = <1800000>;
31		regulator-max-microvolt = <1800000>;
32		regulator-boot-on;
33		regulator-always-on;
34	};
35
36	reg_3p3v: regulator-3p3v {
37		compatible = "regulator-fixed";
38		regulator-name = "fixed-3.3V";
39		regulator-min-microvolt = <3300000>;
40		regulator-max-microvolt = <3300000>;
41		regulator-boot-on;
42		regulator-always-on;
43	};
44
45#if !(SW_SW0_DEV_SEL)
46	vccq_sdhi0: regulator-vccq-sdhi0 {
47		compatible = "regulator-gpio";
48
49		regulator-name = "SDHI0 VccQ";
50		regulator-min-microvolt = <1800000>;
51		regulator-max-microvolt = <3300000>;
52		states = <3300000 1>, <1800000 0>;
53		regulator-boot-on;
54		gpios = <&pinctrl RZG2L_GPIO(6, 2) GPIO_ACTIVE_HIGH>;
55		regulator-always-on;
56	};
57#endif
58};
59
60#if (SW_SW0_DEV_SEL)
61&adc {
62	pinctrl-0 = <&adc_pins>;
63	pinctrl-names = "default";
64	status = "okay";
65};
66#endif
67
68#if (!SW_ET0_EN_N)
69&eth0 {
70	pinctrl-0 = <&eth0_pins>;
71	pinctrl-names = "default";
72	phy-handle = <&phy0>;
73	phy-mode = "rgmii-id";
74	status = "okay";
75
76	phy0: ethernet-phy@7 {
77		compatible = "ethernet-phy-id0022.1640",
78			     "ethernet-phy-ieee802.3-c22";
79		reg = <7>;
80		rxc-skew-psec = <2400>;
81		txc-skew-psec = <2400>;
82		rxdv-skew-psec = <0>;
83		txdv-skew-psec = <0>;
84		rxd0-skew-psec = <0>;
85		rxd1-skew-psec = <0>;
86		rxd2-skew-psec = <0>;
87		rxd3-skew-psec = <0>;
88		txd0-skew-psec = <0>;
89		txd1-skew-psec = <0>;
90		txd2-skew-psec = <0>;
91		txd3-skew-psec = <0>;
92	};
93};
94#endif
95
96&eth1 {
97	pinctrl-0 = <&eth1_pins>;
98	pinctrl-names = "default";
99	phy-handle = <&phy1>;
100	phy-mode = "rgmii-id";
101	status = "okay";
102
103	phy1: ethernet-phy@7 {
104		compatible = "ethernet-phy-id0022.1640",
105			     "ethernet-phy-ieee802.3-c22";
106		reg = <7>;
107		rxc-skew-psec = <2400>;
108		txc-skew-psec = <2400>;
109		rxdv-skew-psec = <0>;
110		txdv-skew-psec = <0>;
111		rxd0-skew-psec = <0>;
112		rxd1-skew-psec = <0>;
113		rxd2-skew-psec = <0>;
114		rxd3-skew-psec = <0>;
115		txd0-skew-psec = <0>;
116		txd1-skew-psec = <0>;
117		txd2-skew-psec = <0>;
118		txd3-skew-psec = <0>;
119	};
120};
121
122&extal_clk {
123	clock-frequency = <24000000>;
124};
125
126&ostm1 {
127	status = "okay";
128};
129
130&ostm2 {
131	status = "okay";
132};
133
134&pinctrl {
135	adc_pins: adc {
136		pinmux = <RZG2L_PORT_PINMUX(6, 2, 1)>; /* ADC_TRG */
137	};
138
139	eth0_pins: eth0 {
140		pinmux = <RZG2L_PORT_PINMUX(4, 5, 1)>, /* ET0_LINKSTA */
141			 <RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */
142			 <RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */
143			 <RZG2L_PORT_PINMUX(1, 0, 1)>, /* ET0_TXC */
144			 <RZG2L_PORT_PINMUX(1, 1, 1)>, /* ET0_TX_CTL */
145			 <RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */
146			 <RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */
147			 <RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */
148			 <RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */
149			 <RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */
150			 <RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */
151			 <RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
152			 <RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
153			 <RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
154			 <RZG2L_PORT_PINMUX(4, 1, 1)>; /* ET0_RXD3 */
155	};
156
157	eth1_pins: eth1 {
158		pinmux = <RZG2L_PORT_PINMUX(10, 4, 1)>, /* ET1_LINKSTA */
159			 <RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */
160			 <RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */
161			 <RZG2L_PORT_PINMUX(7, 0, 1)>, /* ET1_TXC */
162			 <RZG2L_PORT_PINMUX(7, 1, 1)>, /* ET1_TX_CTL */
163			 <RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */
164			 <RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */
165			 <RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */
166			 <RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */
167			 <RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */
168			 <RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */
169			 <RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
170			 <RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
171			 <RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
172			 <RZG2L_PORT_PINMUX(10, 0, 1)>; /* ET1_RXD3 */
173	};
174
175	sdhi0_emmc_pins: sd0emmc {
176		sd0_emmc_data {
177			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
178			       "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
179			power-source = <1800>;
180		};
181
182		sd0_emmc_ctrl {
183			pins = "SD0_CLK", "SD0_CMD";
184			power-source = <1800>;
185		};
186
187		sd0_emmc_rst {
188			pins = "SD0_RST#";
189			power-source = <1800>;
190		};
191	};
192
193	sdhi0_pins: sd0 {
194		sd0_data {
195			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
196			power-source = <3300>;
197		};
198
199		sd0_ctrl {
200			pins = "SD0_CLK", "SD0_CMD";
201			power-source = <3300>;
202		};
203
204		sd0_mux {
205			pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
206		};
207	};
208
209	sdhi0_pins_uhs: sd0_uhs {
210		sd0_data_uhs {
211			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
212			power-source = <1800>;
213		};
214
215		sd0_ctrl_uhs {
216			pins = "SD0_CLK", "SD0_CMD";
217			power-source = <1800>;
218		};
219
220		sd0_mux_uhs {
221			pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
222		};
223	};
224
225	spi1_pins: rspi1 {
226		pinmux = <RZG2L_PORT_PINMUX(4, 0, 2)>, /* CK */
227			 <RZG2L_PORT_PINMUX(4, 1, 2)>, /* MOSI */
228			 <RZG2L_PORT_PINMUX(4, 2, 2)>, /* MISO */
229			 <RZG2L_PORT_PINMUX(4, 3, 2)>; /* SSL */
230	};
231};
232
233#if (SW_SW0_DEV_SEL)
234&sdhi0 {
235	pinctrl-0 = <&sdhi0_emmc_pins>;
236	pinctrl-1 = <&sdhi0_emmc_pins>;
237	pinctrl-names = "default", "state_uhs";
238
239	vmmc-supply = <&reg_3p3v>;
240	vqmmc-supply = <&reg_1p8v>;
241	bus-width = <8>;
242	mmc-hs200-1_8v;
243	non-removable;
244	fixed-emmc-driver-type = <1>;
245	status = "okay";
246};
247#else
248&sdhi0 {
249	pinctrl-0 = <&sdhi0_pins>;
250	pinctrl-1 = <&sdhi0_pins_uhs>;
251	pinctrl-names = "default", "state_uhs";
252
253	vmmc-supply = <&reg_3p3v>;
254	vqmmc-supply = <&vccq_sdhi0>;
255	bus-width = <4>;
256	sd-uhs-sdr50;
257	sd-uhs-sdr104;
258	status = "okay";
259};
260#endif
261
262&wdt0 {
263	status = "okay";
264	timeout-sec = <60>;
265};
266
267&wdt2 {
268	status = "okay";
269	timeout-sec = <60>;
270};
271