xref: /freebsd/sys/contrib/device-tree/src/arm64/renesas/rzg2lc-smarc.dtsi (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c) 
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2LC SMARC EVK parts
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
10
11#include "rzg2lc-smarc-pinfunction.dtsi"
12#include "rz-smarc-common.dtsi"
13
14
15/ {
16	aliases {
17		serial1 = &scif1;
18		i2c2 = &i2c2;
19	};
20
21	osc1: cec-clock {
22		compatible = "fixed-clock";
23		#clock-cells = <0>;
24		clock-frequency = <12000000>;
25	};
26
27	hdmi-out {
28		compatible = "hdmi-connector";
29		type = "d";
30
31		port {
32			hdmi_con_out: endpoint {
33				remote-endpoint = <&adv7535_out>;
34			};
35		};
36	};
37};
38
39#if (SW_SCIF_CAN || SW_RSPI_CAN)
40&canfd {
41	pinctrl-0 = <&can1_pins>;
42	/delete-node/ channel@0;
43};
44#else
45&canfd {
46	/delete-property/ pinctrl-0;
47	/delete-property/ pinctrl-names;
48	status = "disabled";
49};
50#endif
51
52&cpu_dai {
53	sound-dai = <&ssi0>;
54};
55
56&dsi {
57	status = "okay";
58
59	ports {
60		#address-cells = <1>;
61		#size-cells = <0>;
62
63		port@0 {
64			reg = <0>;
65			dsi0_in: endpoint {
66			};
67		};
68
69		port@1 {
70			reg = <1>;
71			dsi0_out: endpoint {
72				data-lanes = <1 2 3 4>;
73				remote-endpoint = <&adv7535_in>;
74			};
75		};
76	};
77};
78
79&i2c1 {
80	adv7535: hdmi@3d {
81		compatible = "adi,adv7535";
82		reg = <0x3d>;
83
84		interrupt-parent = <&pinctrl>;
85		interrupts = <RZG2L_GPIO(43, 1) IRQ_TYPE_EDGE_FALLING>;
86		clocks = <&osc1>;
87		clock-names = "cec";
88		avdd-supply = <&reg_1p8v>;
89		dvdd-supply = <&reg_1p8v>;
90		pvdd-supply = <&reg_1p8v>;
91		a2vdd-supply = <&reg_1p8v>;
92		v3p3-supply = <&reg_3p3v>;
93		v1p2-supply = <&reg_1p8v>;
94
95		adi,dsi-lanes = <4>;
96
97		ports {
98			#address-cells = <1>;
99			#size-cells = <0>;
100
101			port@0 {
102				reg = <0>;
103				adv7535_in: endpoint {
104					remote-endpoint = <&dsi0_out>;
105				};
106			};
107
108			port@1 {
109				reg = <1>;
110				adv7535_out: endpoint {
111					remote-endpoint = <&hdmi_con_out>;
112				};
113			};
114		};
115	};
116};
117
118&i2c2 {
119	pinctrl-0 = <&i2c2_pins>;
120	pinctrl-names = "default";
121	clock-frequency = <400000>;
122
123	status = "okay";
124
125	wm8978: codec@1a {
126		compatible = "wlf,wm8978";
127		#sound-dai-cells = <0>;
128		reg = <0x1a>;
129	};
130};
131
132/*
133 * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
134 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
135 * SW2 should be at position 2->3 so that SER0_TX line is activated
136 * SW3 should be at position 2->3 so that SER0_RX line is activated
137 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
138 */
139#if (!SW_SCIF_CAN && PMOD1_SER0)
140&scif1 {
141	pinctrl-0 = <&scif1_pins>;
142	pinctrl-names = "default";
143
144	uart-has-rtscts;
145	status = "okay";
146};
147#endif
148
149&ssi0 {
150	pinctrl-0 = <&ssi0_pins>;
151	pinctrl-names = "default";
152
153	status = "okay";
154};
155
156#if (SW_RSPI_CAN)
157&spi1 {
158	/delete-property/ pinctrl-0;
159	/delete-property/ pinctrl-names;
160	status = "disabled";
161};
162#endif
163
164&vccq_sdhi1 {
165	gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
166};
167