1c9ccf3a3SEmmanuel Vadot// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2c9ccf3a3SEmmanuel Vadot/* 3c9ccf3a3SEmmanuel Vadot * Device Tree Source for the RZ/G2LC SMARC pincontrol parts 4c9ccf3a3SEmmanuel Vadot * 5c9ccf3a3SEmmanuel Vadot * Copyright (C) 2021 Renesas Electronics Corp. 6c9ccf3a3SEmmanuel Vadot */ 7c9ccf3a3SEmmanuel Vadot 8c9ccf3a3SEmmanuel Vadot#include <dt-bindings/gpio/gpio.h> 9c9ccf3a3SEmmanuel Vadot#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 10c9ccf3a3SEmmanuel Vadot 11c9ccf3a3SEmmanuel Vadot&pinctrl { 12c9ccf3a3SEmmanuel Vadot pinctrl-0 = <&sound_clk_pins>; 13c9ccf3a3SEmmanuel Vadot pinctrl-names = "default"; 14c9ccf3a3SEmmanuel Vadot 15c9ccf3a3SEmmanuel Vadot#if SW_SCIF_CAN 16c9ccf3a3SEmmanuel Vadot /* SW8 should be at position 2->1 */ 17c9ccf3a3SEmmanuel Vadot can1_pins: can1 { 18c9ccf3a3SEmmanuel Vadot pinmux = <RZG2L_PORT_PINMUX(40, 0, 3)>, /* TxD */ 19c9ccf3a3SEmmanuel Vadot <RZG2L_PORT_PINMUX(40, 1, 3)>; /* RxD */ 20c9ccf3a3SEmmanuel Vadot }; 21c9ccf3a3SEmmanuel Vadot#endif 22c9ccf3a3SEmmanuel Vadot 23c9ccf3a3SEmmanuel Vadot#if SW_RSPI_CAN 24c9ccf3a3SEmmanuel Vadot /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */ 25c9ccf3a3SEmmanuel Vadot can1-stb-hog { 26c9ccf3a3SEmmanuel Vadot gpio-hog; 27c9ccf3a3SEmmanuel Vadot gpios = <RZG2L_GPIO(44, 3) GPIO_ACTIVE_HIGH>; 28c9ccf3a3SEmmanuel Vadot output-low; 29c9ccf3a3SEmmanuel Vadot line-name = "can1_stb"; 30c9ccf3a3SEmmanuel Vadot }; 31c9ccf3a3SEmmanuel Vadot 32c9ccf3a3SEmmanuel Vadot can1_pins: can1 { 33c9ccf3a3SEmmanuel Vadot pinmux = <RZG2L_PORT_PINMUX(44, 0, 3)>, /* TxD */ 34c9ccf3a3SEmmanuel Vadot <RZG2L_PORT_PINMUX(44, 1, 3)>; /* RxD */ 35c9ccf3a3SEmmanuel Vadot }; 36c9ccf3a3SEmmanuel Vadot#endif 37c9ccf3a3SEmmanuel Vadot 38*d5b0e70fSEmmanuel Vadot i2c0_pins: i2c0 { 39*d5b0e70fSEmmanuel Vadot pins = "RIIC0_SDA", "RIIC0_SCL"; 40*d5b0e70fSEmmanuel Vadot input-enable; 41*d5b0e70fSEmmanuel Vadot }; 42*d5b0e70fSEmmanuel Vadot 43*d5b0e70fSEmmanuel Vadot i2c1_pins: i2c1 { 44*d5b0e70fSEmmanuel Vadot pins = "RIIC1_SDA", "RIIC1_SCL"; 45*d5b0e70fSEmmanuel Vadot input-enable; 46*d5b0e70fSEmmanuel Vadot }; 47*d5b0e70fSEmmanuel Vadot 48*d5b0e70fSEmmanuel Vadot i2c2_pins: i2c2 { 49*d5b0e70fSEmmanuel Vadot pinmux = <RZG2L_PORT_PINMUX(42, 3, 1)>, /* SDA */ 50*d5b0e70fSEmmanuel Vadot <RZG2L_PORT_PINMUX(42, 4, 1)>; /* SCL */ 51*d5b0e70fSEmmanuel Vadot }; 52*d5b0e70fSEmmanuel Vadot 53*d5b0e70fSEmmanuel Vadot scif0_pins: scif0 { 54*d5b0e70fSEmmanuel Vadot pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */ 55*d5b0e70fSEmmanuel Vadot <RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */ 56*d5b0e70fSEmmanuel Vadot }; 57*d5b0e70fSEmmanuel Vadot 58*d5b0e70fSEmmanuel Vadot scif1_pins: scif1 { 59*d5b0e70fSEmmanuel Vadot pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */ 60*d5b0e70fSEmmanuel Vadot <RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */ 61*d5b0e70fSEmmanuel Vadot <RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */ 62*d5b0e70fSEmmanuel Vadot <RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */ 63*d5b0e70fSEmmanuel Vadot }; 64*d5b0e70fSEmmanuel Vadot 65c9ccf3a3SEmmanuel Vadot sd1-pwr-en-hog { 66c9ccf3a3SEmmanuel Vadot gpio-hog; 67c9ccf3a3SEmmanuel Vadot gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>; 68c9ccf3a3SEmmanuel Vadot output-high; 69c9ccf3a3SEmmanuel Vadot line-name = "sd1_pwr_en"; 70c9ccf3a3SEmmanuel Vadot }; 71c9ccf3a3SEmmanuel Vadot 72c9ccf3a3SEmmanuel Vadot sdhi1_pins: sd1 { 73c9ccf3a3SEmmanuel Vadot sd1_data { 74c9ccf3a3SEmmanuel Vadot pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; 75c9ccf3a3SEmmanuel Vadot power-source = <3300>; 76c9ccf3a3SEmmanuel Vadot }; 77c9ccf3a3SEmmanuel Vadot 78c9ccf3a3SEmmanuel Vadot sd1_ctrl { 79c9ccf3a3SEmmanuel Vadot pins = "SD1_CLK", "SD1_CMD"; 80c9ccf3a3SEmmanuel Vadot power-source = <3300>; 81c9ccf3a3SEmmanuel Vadot }; 82c9ccf3a3SEmmanuel Vadot 83c9ccf3a3SEmmanuel Vadot sd1_mux { 84c9ccf3a3SEmmanuel Vadot pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */ 85c9ccf3a3SEmmanuel Vadot }; 86c9ccf3a3SEmmanuel Vadot }; 87c9ccf3a3SEmmanuel Vadot 88c9ccf3a3SEmmanuel Vadot sdhi1_pins_uhs: sd1_uhs { 89c9ccf3a3SEmmanuel Vadot sd1_data_uhs { 90c9ccf3a3SEmmanuel Vadot pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3"; 91c9ccf3a3SEmmanuel Vadot power-source = <1800>; 92c9ccf3a3SEmmanuel Vadot }; 93c9ccf3a3SEmmanuel Vadot 94c9ccf3a3SEmmanuel Vadot sd1_ctrl_uhs { 95c9ccf3a3SEmmanuel Vadot pins = "SD1_CLK", "SD1_CMD"; 96c9ccf3a3SEmmanuel Vadot power-source = <1800>; 97c9ccf3a3SEmmanuel Vadot }; 98c9ccf3a3SEmmanuel Vadot 99c9ccf3a3SEmmanuel Vadot sd1_mux_uhs { 100c9ccf3a3SEmmanuel Vadot pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */ 101c9ccf3a3SEmmanuel Vadot }; 102c9ccf3a3SEmmanuel Vadot }; 103c9ccf3a3SEmmanuel Vadot 104c9ccf3a3SEmmanuel Vadot sound_clk_pins: sound_clk { 105c9ccf3a3SEmmanuel Vadot pins = "AUDIO_CLK1", "AUDIO_CLK2"; 106c9ccf3a3SEmmanuel Vadot input-enable; 107c9ccf3a3SEmmanuel Vadot }; 108*d5b0e70fSEmmanuel Vadot 109*d5b0e70fSEmmanuel Vadot spi1_pins: spi1 { 110*d5b0e70fSEmmanuel Vadot pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */ 111*d5b0e70fSEmmanuel Vadot <RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */ 112*d5b0e70fSEmmanuel Vadot <RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */ 113*d5b0e70fSEmmanuel Vadot <RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */ 114*d5b0e70fSEmmanuel Vadot }; 115*d5b0e70fSEmmanuel Vadot 116*d5b0e70fSEmmanuel Vadot ssi0_pins: ssi0 { 117*d5b0e70fSEmmanuel Vadot pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */ 118*d5b0e70fSEmmanuel Vadot <RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */ 119*d5b0e70fSEmmanuel Vadot <RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */ 120*d5b0e70fSEmmanuel Vadot <RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */ 121*d5b0e70fSEmmanuel Vadot }; 122*d5b0e70fSEmmanuel Vadot 123*d5b0e70fSEmmanuel Vadot usb0_pins: usb0 { 124*d5b0e70fSEmmanuel Vadot pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */ 125*d5b0e70fSEmmanuel Vadot <RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */ 126*d5b0e70fSEmmanuel Vadot <RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */ 127*d5b0e70fSEmmanuel Vadot }; 128*d5b0e70fSEmmanuel Vadot 129*d5b0e70fSEmmanuel Vadot usb1_pins: usb1 { 130*d5b0e70fSEmmanuel Vadot pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */ 131*d5b0e70fSEmmanuel Vadot <RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */ 132*d5b0e70fSEmmanuel Vadot }; 133c9ccf3a3SEmmanuel Vadot}; 134c9ccf3a3SEmmanuel Vadot 135