xref: /freebsd/sys/contrib/device-tree/src/arm64/renesas/rzg2lc-smarc-pinfunction.dtsi (revision c9ccf3a32da427475985b85d7df023ccfb138c27)
1*c9ccf3a3SEmmanuel Vadot// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*c9ccf3a3SEmmanuel Vadot/*
3*c9ccf3a3SEmmanuel Vadot * Device Tree Source for the RZ/G2LC SMARC pincontrol parts
4*c9ccf3a3SEmmanuel Vadot *
5*c9ccf3a3SEmmanuel Vadot * Copyright (C) 2021 Renesas Electronics Corp.
6*c9ccf3a3SEmmanuel Vadot */
7*c9ccf3a3SEmmanuel Vadot
8*c9ccf3a3SEmmanuel Vadot#include <dt-bindings/gpio/gpio.h>
9*c9ccf3a3SEmmanuel Vadot#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
10*c9ccf3a3SEmmanuel Vadot
11*c9ccf3a3SEmmanuel Vadot&pinctrl {
12*c9ccf3a3SEmmanuel Vadot	pinctrl-0 = <&sound_clk_pins>;
13*c9ccf3a3SEmmanuel Vadot	pinctrl-names = "default";
14*c9ccf3a3SEmmanuel Vadot
15*c9ccf3a3SEmmanuel Vadot	scif0_pins: scif0 {
16*c9ccf3a3SEmmanuel Vadot		pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>,	/* TxD */
17*c9ccf3a3SEmmanuel Vadot			 <RZG2L_PORT_PINMUX(38, 1, 1)>;	/* RxD */
18*c9ccf3a3SEmmanuel Vadot	};
19*c9ccf3a3SEmmanuel Vadot
20*c9ccf3a3SEmmanuel Vadot#if SW_SCIF_CAN
21*c9ccf3a3SEmmanuel Vadot	/* SW8 should be at position 2->1 */
22*c9ccf3a3SEmmanuel Vadot	can1_pins: can1 {
23*c9ccf3a3SEmmanuel Vadot		pinmux = <RZG2L_PORT_PINMUX(40, 0, 3)>, /* TxD */
24*c9ccf3a3SEmmanuel Vadot			 <RZG2L_PORT_PINMUX(40, 1, 3)>; /* RxD */
25*c9ccf3a3SEmmanuel Vadot	};
26*c9ccf3a3SEmmanuel Vadot#endif
27*c9ccf3a3SEmmanuel Vadot
28*c9ccf3a3SEmmanuel Vadot	scif1_pins: scif1 {
29*c9ccf3a3SEmmanuel Vadot		pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
30*c9ccf3a3SEmmanuel Vadot			 <RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */
31*c9ccf3a3SEmmanuel Vadot			 <RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */
32*c9ccf3a3SEmmanuel Vadot			 <RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */
33*c9ccf3a3SEmmanuel Vadot	};
34*c9ccf3a3SEmmanuel Vadot
35*c9ccf3a3SEmmanuel Vadot#if SW_RSPI_CAN
36*c9ccf3a3SEmmanuel Vadot	/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
37*c9ccf3a3SEmmanuel Vadot	can1-stb-hog {
38*c9ccf3a3SEmmanuel Vadot		gpio-hog;
39*c9ccf3a3SEmmanuel Vadot		gpios = <RZG2L_GPIO(44, 3) GPIO_ACTIVE_HIGH>;
40*c9ccf3a3SEmmanuel Vadot		output-low;
41*c9ccf3a3SEmmanuel Vadot		line-name = "can1_stb";
42*c9ccf3a3SEmmanuel Vadot	};
43*c9ccf3a3SEmmanuel Vadot
44*c9ccf3a3SEmmanuel Vadot	can1_pins: can1 {
45*c9ccf3a3SEmmanuel Vadot		pinmux = <RZG2L_PORT_PINMUX(44, 0, 3)>, /* TxD */
46*c9ccf3a3SEmmanuel Vadot			 <RZG2L_PORT_PINMUX(44, 1, 3)>; /* RxD */
47*c9ccf3a3SEmmanuel Vadot	};
48*c9ccf3a3SEmmanuel Vadot#endif
49*c9ccf3a3SEmmanuel Vadot
50*c9ccf3a3SEmmanuel Vadot	sd1-pwr-en-hog {
51*c9ccf3a3SEmmanuel Vadot		gpio-hog;
52*c9ccf3a3SEmmanuel Vadot		gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;
53*c9ccf3a3SEmmanuel Vadot		output-high;
54*c9ccf3a3SEmmanuel Vadot		line-name = "sd1_pwr_en";
55*c9ccf3a3SEmmanuel Vadot	};
56*c9ccf3a3SEmmanuel Vadot
57*c9ccf3a3SEmmanuel Vadot	sdhi1_pins: sd1 {
58*c9ccf3a3SEmmanuel Vadot		sd1_data {
59*c9ccf3a3SEmmanuel Vadot			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
60*c9ccf3a3SEmmanuel Vadot			power-source = <3300>;
61*c9ccf3a3SEmmanuel Vadot		};
62*c9ccf3a3SEmmanuel Vadot
63*c9ccf3a3SEmmanuel Vadot		sd1_ctrl {
64*c9ccf3a3SEmmanuel Vadot			pins = "SD1_CLK", "SD1_CMD";
65*c9ccf3a3SEmmanuel Vadot			power-source = <3300>;
66*c9ccf3a3SEmmanuel Vadot		};
67*c9ccf3a3SEmmanuel Vadot
68*c9ccf3a3SEmmanuel Vadot		sd1_mux {
69*c9ccf3a3SEmmanuel Vadot			pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
70*c9ccf3a3SEmmanuel Vadot		};
71*c9ccf3a3SEmmanuel Vadot	};
72*c9ccf3a3SEmmanuel Vadot
73*c9ccf3a3SEmmanuel Vadot	sdhi1_pins_uhs: sd1_uhs {
74*c9ccf3a3SEmmanuel Vadot		sd1_data_uhs {
75*c9ccf3a3SEmmanuel Vadot			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
76*c9ccf3a3SEmmanuel Vadot			power-source = <1800>;
77*c9ccf3a3SEmmanuel Vadot		};
78*c9ccf3a3SEmmanuel Vadot
79*c9ccf3a3SEmmanuel Vadot		sd1_ctrl_uhs {
80*c9ccf3a3SEmmanuel Vadot			pins = "SD1_CLK", "SD1_CMD";
81*c9ccf3a3SEmmanuel Vadot			power-source = <1800>;
82*c9ccf3a3SEmmanuel Vadot		};
83*c9ccf3a3SEmmanuel Vadot
84*c9ccf3a3SEmmanuel Vadot		sd1_mux_uhs {
85*c9ccf3a3SEmmanuel Vadot			pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>; /* SD1_CD */
86*c9ccf3a3SEmmanuel Vadot		};
87*c9ccf3a3SEmmanuel Vadot	};
88*c9ccf3a3SEmmanuel Vadot
89*c9ccf3a3SEmmanuel Vadot	sound_clk_pins: sound_clk {
90*c9ccf3a3SEmmanuel Vadot		pins = "AUDIO_CLK1", "AUDIO_CLK2";
91*c9ccf3a3SEmmanuel Vadot		input-enable;
92*c9ccf3a3SEmmanuel Vadot	};
93*c9ccf3a3SEmmanuel Vadot};
94*c9ccf3a3SEmmanuel Vadot
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