xref: /freebsd/sys/contrib/device-tree/src/arm64/renesas/rzg2l-smarc.dtsi (revision 2f9966ff63d65bd474478888c9088eeae3f9c669) 
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
10
11/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */
12#define PMOD1_SER0	1
13
14/ {
15	aliases {
16		serial1 = &scif2;
17		i2c3 = &i2c3;
18	};
19
20	osc1: cec-clock {
21		compatible = "fixed-clock";
22		#clock-cells = <0>;
23		clock-frequency = <12000000>;
24	};
25
26	hdmi-out {
27		compatible = "hdmi-connector";
28		type = "d";
29
30		port {
31			hdmi_con_out: endpoint {
32				remote-endpoint = <&adv7535_out>;
33			};
34		};
35	};
36};
37
38&cpu_dai {
39	sound-dai = <&ssi0>;
40};
41
42&dsi {
43	status = "okay";
44
45	ports {
46		#address-cells = <1>;
47		#size-cells = <0>;
48
49		port@0 {
50			reg = <0>;
51			dsi0_in: endpoint {
52			};
53		};
54
55		port@1 {
56			reg = <1>;
57			dsi0_out: endpoint {
58				data-lanes = <1 2 3 4>;
59				remote-endpoint = <&adv7535_in>;
60			};
61		};
62	};
63};
64
65&i2c1 {
66	adv7535: hdmi@3d {
67		compatible = "adi,adv7535";
68		reg = <0x3d>;
69
70		interrupt-parent = <&pinctrl>;
71		interrupts = <RZG2L_GPIO(2, 1) IRQ_TYPE_EDGE_FALLING>;
72		clocks = <&osc1>;
73		clock-names = "cec";
74		avdd-supply = <&reg_1p8v>;
75		dvdd-supply = <&reg_1p8v>;
76		pvdd-supply = <&reg_1p8v>;
77		a2vdd-supply = <&reg_1p8v>;
78		v3p3-supply = <&reg_3p3v>;
79		v1p2-supply = <&reg_1p8v>;
80
81		adi,dsi-lanes = <4>;
82
83		ports {
84			#address-cells = <1>;
85			#size-cells = <0>;
86
87			port@0 {
88				reg = <0>;
89				adv7535_in: endpoint {
90					remote-endpoint = <&dsi0_out>;
91				};
92			};
93
94			port@1 {
95				reg = <1>;
96				adv7535_out: endpoint {
97					remote-endpoint = <&hdmi_con_out>;
98				};
99			};
100		};
101	};
102};
103
104&i2c3 {
105	pinctrl-0 = <&i2c3_pins>;
106	pinctrl-names = "default";
107	clock-frequency = <400000>;
108
109	status = "okay";
110
111	wm8978: codec@1a {
112		compatible = "wlf,wm8978";
113		#sound-dai-cells = <0>;
114		reg = <0x1a>;
115	};
116};
117
118/*
119 * To enable SCIF2 (SER0) on PMOD1 (CN7)
120 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
121 * SW2 should be at position 2->3 so that SER0_TX line is activated
122 * SW3 should be at position 2->3 so that SER0_RX line is activated
123 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
124 */
125#if PMOD1_SER0
126&scif2 {
127	pinctrl-0 = <&scif2_pins>;
128	pinctrl-names = "default";
129
130	uart-has-rtscts;
131	status = "okay";
132};
133#endif
134
135&ssi0 {
136	pinctrl-0 = <&ssi0_pins>;
137	pinctrl-names = "default";
138
139	status = "okay";
140};
141
142&vccq_sdhi1 {
143	gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
144};
145