1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/{G2L,V2L} SMARC EVK common parts 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 10 11/* comment the #define statement to disable SCIF2 (SER0) on PMOD1 (CN7) */ 12#define PMOD1_SER0 1 13 14/ { 15 aliases { 16 serial1 = &scif2; 17 i2c3 = &i2c3; 18 }; 19}; 20 21&cpu_dai { 22 sound-dai = <&ssi0>; 23}; 24 25&i2c3 { 26 pinctrl-0 = <&i2c3_pins>; 27 pinctrl-names = "default"; 28 clock-frequency = <400000>; 29 30 status = "okay"; 31 32 wm8978: codec@1a { 33 compatible = "wlf,wm8978"; 34 #sound-dai-cells = <0>; 35 reg = <0x1a>; 36 }; 37}; 38 39/* 40 * To enable SCIF2 (SER0) on PMOD1 (CN7) 41 * SW1 should be at position 2->3 so that SER0_CTS# line is activated 42 * SW2 should be at position 2->3 so that SER0_TX line is activated 43 * SW3 should be at position 2->3 so that SER0_RX line is activated 44 * SW4 should be at position 2->3 so that SER0_RTS# line is activated 45 */ 46#if PMOD1_SER0 47&scif2 { 48 pinctrl-0 = <&scif2_pins>; 49 pinctrl-names = "default"; 50 51 uart-has-rtscts; 52 status = "okay"; 53}; 54#endif 55 56&ssi0 { 57 pinctrl-0 = <&ssi0_pins>; 58 pinctrl-names = "default"; 59 60 status = "okay"; 61}; 62 63&vccq_sdhi1 { 64 gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; 65}; 66