xref: /freebsd/sys/contrib/device-tree/src/arm64/renesas/r9a09g011.dtsi (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/V2M SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/clock/r9a09g011-cpg.h>
10
11/ {
12	compatible = "renesas,r9a09g011";
13	#address-cells = <2>;
14	#size-cells = <2>;
15
16	/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
17	extal_clk: extal {
18		compatible = "fixed-clock";
19		#clock-cells = <0>;
20		/* This value must be overridden by the board */
21		clock-frequency = <0>;
22	};
23
24	cpus {
25		#address-cells = <1>;
26		#size-cells = <0>;
27
28		cpu-map {
29			cluster0 {
30				core0 {
31					cpu = <&cpu0>;
32				};
33			};
34		};
35
36		cpu0: cpu@0 {
37			compatible = "arm,cortex-a53";
38			reg = <0>;
39			device_type = "cpu";
40			next-level-cache = <&L2_CA53>;
41			clocks = <&cpg CPG_MOD R9A09G011_CA53_CLK>;
42		};
43
44		L2_CA53: cache-controller-0 {
45			compatible = "cache";
46			cache-unified;
47			cache-level = <2>;
48		};
49	};
50
51	soc: soc {
52		compatible = "simple-bus";
53		interrupt-parent = <&gic>;
54		#address-cells = <2>;
55		#size-cells = <2>;
56		ranges;
57
58		gic: interrupt-controller@82010000 {
59			compatible = "arm,gic-400";
60			#interrupt-cells = <3>;
61			#address-cells = <0>;
62			interrupt-controller;
63			reg = <0x0 0x82010000 0 0x1000>,
64			      <0x0 0x82020000 0 0x20000>,
65			      <0x0 0x82040000 0 0x20000>,
66			      <0x0 0x82060000 0 0x20000>;
67			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
68			clocks = <&cpg CPG_MOD R9A09G011_GIC_CLK>;
69			clock-names = "clk";
70		};
71
72		sdhi0: mmc@85000000 {
73			compatible = "renesas,sdhi-r9a09g011",
74				     "renesas,rcar-gen3-sdhi";
75			reg = <0x0 0x85000000 0 0x2000>;
76			interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
77				     <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
78			clocks = <&cpg CPG_MOD R9A09G011_SDI0_IMCLK>,
79				 <&cpg CPG_MOD R9A09G011_SDI0_CLK_HS>,
80				 <&cpg CPG_MOD R9A09G011_SDI0_IMCLK2>,
81				 <&cpg CPG_MOD R9A09G011_SDI0_ACLK>;
82			clock-names = "core", "clkh", "cd", "aclk";
83			resets = <&cpg R9A09G011_SDI0_IXRST>;
84			power-domains = <&cpg>;
85			status = "disabled";
86		};
87
88		sdhi1: mmc@85010000  {
89			compatible = "renesas,sdhi-r9a09g011",
90				     "renesas,rcar-gen3-sdhi";
91			reg = <0x0 0x85010000 0 0x2000>;
92			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
93				     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
94			clocks = <&cpg CPG_MOD R9A09G011_SDI1_IMCLK>,
95				 <&cpg CPG_MOD R9A09G011_SDI1_CLK_HS>,
96				 <&cpg CPG_MOD R9A09G011_SDI1_IMCLK2>,
97				 <&cpg CPG_MOD R9A09G011_SDI1_ACLK>;
98			clock-names = "core", "clkh", "cd", "aclk";
99			resets = <&cpg R9A09G011_SDI1_IXRST>;
100			power-domains = <&cpg>;
101			status = "disabled";
102		};
103
104		emmc: mmc@85020000  {
105			compatible = "renesas,sdhi-r9a09g011",
106				     "renesas,rcar-gen3-sdhi";
107			reg = <0x0 0x85020000 0 0x2000>;
108			interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
109				     <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
110			clocks = <&cpg CPG_MOD R9A09G011_EMM_IMCLK>,
111				 <&cpg CPG_MOD R9A09G011_EMM_CLK_HS>,
112				 <&cpg CPG_MOD R9A09G011_EMM_IMCLK2>,
113				 <&cpg CPG_MOD R9A09G011_EMM_ACLK>;
114			clock-names = "core", "clkh", "cd", "aclk";
115			resets = <&cpg R9A09G011_EMM_IXRST>;
116			power-domains = <&cpg>;
117			status = "disabled";
118		};
119
120		usb3drd: usb3drd@85070400 {
121			compatible = "renesas,r9a09g011-usb3drd",
122				     "renesas,rzv2m-usb3drd";
123			reg = <0x0 0x85070400 0x0 0x100>;
124			interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
125				      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
126				      <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
127			interrupt-names = "drd", "bc", "gpi";
128			clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>,
129				 <&cpg CPG_MOD R9A09G011_USB_PCLK>;
130			clock-names = "axi", "reg";
131			resets = <&cpg R9A09G011_USB_DRD_RESET>;
132			power-domains = <&cpg>;
133			ranges;
134			#address-cells = <2>;
135			#size-cells = <2>;
136			status = "disabled";
137
138			usb3host: usb@85060000 {
139				compatible = "renesas,r9a09g011-xhci",
140					     "renesas,rzv2m-xhci";
141				reg = <0 0x85060000 0 0x2000>;
142				interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
143				clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_H>,
144					 <&cpg CPG_MOD R9A09G011_USB_PCLK>;
145				clock-names = "axi", "reg";
146				resets = <&cpg R9A09G011_USB_ARESETN_H>;
147				power-domains = <&cpg>;
148				status = "disabled";
149			};
150
151			usb3peri: usb3peri@85070000 {
152				compatible = "renesas,r9a09g011-usb3-peri",
153					     "renesas,rzv2m-usb3-peri";
154				reg = <0x0 0x85070000 0x0 0x400>;
155				interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
156				clocks = <&cpg CPG_MOD R9A09G011_USB_ACLK_P>,
157					 <&cpg CPG_MOD R9A09G011_USB_PCLK>;
158				clock-names = "axi", "reg";
159				resets = <&cpg R9A09G011_USB_ARESETN_P>;
160				power-domains = <&cpg>;
161				status = "disabled";
162			};
163		};
164
165		avb: ethernet@a3300000 {
166			compatible = "renesas,etheravb-r9a09g011","renesas,etheravb-rzv2m";
167			reg = <0 0xa3300000 0 0x800>;
168			interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, /* ch0: Rx0 BE */
169				     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, /* ch1: Rx1 NC */
170				     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
171				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
172				     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
173				     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
174				     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
175				     <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
176				     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
177				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
178				     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
179				     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
180				     <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
181				     <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
182				     <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
183				     <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
184				     <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
185				     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
186				     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* ch18: Tx0 BE */
187				     <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* ch19: Tx1 NC */
188				     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
189				     <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
190				     <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, /* DiA */
191				     <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, /* DiB */
192				     <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, /* Line1_A */
193				     <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, /* Line1_B */
194				     <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, /* Line2_A */
195				     <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, /* Line2_B */
196				     <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; /* Line3 MAC */
197			interrupt-names = "ch0", "ch1", "ch2", "ch3",
198					  "ch4", "ch5", "ch6", "ch7",
199					  "ch8", "ch9", "ch10", "ch11",
200					  "ch12", "ch13", "ch14", "ch15",
201					  "ch16", "ch17", "ch18", "ch19",
202					  "ch20", "ch21", "dia", "dib",
203					  "err_a", "err_b", "mgmt_a", "mgmt_b",
204					  "line3";
205			clocks = <&cpg CPG_MOD R9A09G011_ETH0_CLK_AXI>,
206				 <&cpg CPG_MOD R9A09G011_ETH0_CLK_CHI>,
207				 <&cpg CPG_MOD R9A09G011_ETH0_GPTP_EXT>;
208			clock-names = "axi", "chi", "gptp";
209			resets = <&cpg R9A09G011_ETH0_RST_HW_N>;
210			power-domains = <&cpg>;
211			#address-cells = <1>;
212			#size-cells = <0>;
213			status = "disabled";
214		};
215
216		cpg: clock-controller@a3500000 {
217			compatible = "renesas,r9a09g011-cpg";
218			reg = <0 0xa3500000 0 0x1000>;
219			clocks = <&extal_clk>;
220			clock-names = "extal";
221			#clock-cells = <2>;
222			#reset-cells = <1>;
223			#power-domain-cells = <0>;
224		};
225
226		pwc: pwc@a3700000 {
227			compatible = "renesas,r9a09g011-pwc", "renesas,rzv2m-pwc";
228			reg = <0 0xa3700000 0 0x800>;
229			gpio-controller;
230			#gpio-cells = <2>;
231			status = "disabled";
232		};
233
234		sys: system-controller@a3f03000 {
235			compatible = "renesas,r9a09g011-sys";
236			reg = <0 0xa3f03000 0 0x400>;
237		};
238
239		i2c0: i2c@a4030000 {
240			#address-cells = <1>;
241			#size-cells = <0>;
242			compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c";
243			reg = <0 0xa4030000 0 0x80>;
244			interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
245				     <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
246			interrupt-names = "tia", "tis";
247			clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK0>;
248			resets = <&cpg R9A09G011_IIC_GPA_PRESETN>;
249			power-domains = <&cpg>;
250			status = "disabled";
251		};
252
253		i2c2: i2c@a4030100 {
254			#address-cells = <1>;
255			#size-cells = <0>;
256			compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c";
257			reg = <0 0xa4030100 0 0x80>;
258			interrupts = <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
259				     <GIC_SPI 238 IRQ_TYPE_EDGE_RISING>;
260			interrupt-names = "tia", "tis";
261			clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK1>;
262			resets = <&cpg R9A09G011_IIC_GPB_PRESETN>;
263			power-domains = <&cpg>;
264			status = "disabled";
265		};
266
267		uart0: serial@a4040000 {
268			compatible = "renesas,r9a09g011-uart", "renesas,em-uart";
269			reg = <0 0xa4040000 0 0x80>;
270			interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
271			clocks = <&cpg CPG_MOD R9A09G011_URT0_CLK>,
272				 <&cpg CPG_MOD R9A09G011_URT_PCLK>;
273			clock-names = "sclk", "pclk";
274			status = "disabled";
275		};
276
277		wdt0: watchdog@a4050000 {
278			compatible = "renesas,r9a09g011-wdt",
279				     "renesas,rzv2m-wdt";
280			reg = <0 0xa4050000 0 0x80>;
281			clocks = <&cpg CPG_MOD R9A09G011_WDT0_PCLK>,
282				 <&cpg CPG_MOD R9A09G011_WDT0_CLK>;
283			clock-names = "pclk", "oscclk";
284			interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
285			resets = <&cpg R9A09G011_WDT0_PRESETN>;
286			power-domains = <&cpg>;
287			status = "disabled";
288		};
289
290		pinctrl: pinctrl@b6250000 {
291			compatible = "renesas,r9a09g011-pinctrl";
292			reg = <0 0xb6250000 0 0x800>;
293			gpio-controller;
294			#gpio-cells = <2>;
295			gpio-ranges = <&pinctrl 0 0 352>;
296			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
297				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
298				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
299				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
300				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
301				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
302				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
303				     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
304				     <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
305				     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
306				     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
307				     <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
308				     <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
309				     <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
310				     <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
311				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
312				     <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
313				     <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
314				     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
315				     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
316				     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
317				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
318				     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
319				     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
320				     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
321				     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
322				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
323				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
324				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
325				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
326				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
327				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
328				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
329				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
330				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
331				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
332				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
333				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
334				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
335			clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>;
336			power-domains = <&cpg>;
337			resets = <&cpg R9A09G011_PFC_PRESETN>;
338		};
339	};
340
341	timer {
342		compatible = "arm,armv8-timer";
343		interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
344				      <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
345				      <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
346				      <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
347	};
348};
349