1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G3S SoC 4 * 5 * Copyright (C) 2023 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a08g045-cpg.h> 10 11/ { 12 compatible = "renesas,r9a08g045"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 compatible = "arm,cortex-a55"; 22 reg = <0>; 23 device_type = "cpu"; 24 #cooling-cells = <2>; 25 next-level-cache = <&L3_CA55>; 26 enable-method = "psci"; 27 clocks = <&cpg CPG_CORE R9A08G045_CLK_I>; 28 }; 29 30 L3_CA55: cache-controller-0 { 31 compatible = "cache"; 32 cache-level = <3>; 33 cache-unified; 34 cache-size = <0x40000>; 35 }; 36 }; 37 38 extal_clk: extal-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 /* This value must be overridden by the board. */ 42 clock-frequency = <0>; 43 }; 44 45 soc: soc { 46 compatible = "simple-bus"; 47 interrupt-parent = <&gic>; 48 #address-cells = <2>; 49 #size-cells = <2>; 50 ranges; 51 52 scif0: serial@1004b800 { 53 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 54 reg = <0 0x1004b800 0 0x400>; 55 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 56 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 57 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 58 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; 61 interrupt-names = "eri", "rxi", "txi", 62 "bri", "dri", "tei"; 63 clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>; 64 clock-names = "fck"; 65 power-domains = <&cpg>; 66 resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>; 67 status = "disabled"; 68 }; 69 70 cpg: clock-controller@11010000 { 71 compatible = "renesas,r9a08g045-cpg"; 72 reg = <0 0x11010000 0 0x10000>; 73 clocks = <&extal_clk>; 74 clock-names = "extal"; 75 #clock-cells = <2>; 76 #reset-cells = <1>; 77 #power-domain-cells = <0>; 78 }; 79 80 sysc: system-controller@11020000 { 81 compatible = "renesas,r9a08g045-sysc"; 82 reg = <0 0x11020000 0 0x10000>; 83 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 84 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 85 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 86 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 87 interrupt-names = "lpm_int", "ca55stbydone_int", 88 "cm33stbyr_int", "ca55_deny"; 89 status = "disabled"; 90 }; 91 92 pinctrl: pinctrl@11030000 { 93 compatible = "renesas,r9a08g045-pinctrl"; 94 reg = <0 0x11030000 0 0x10000>; 95 gpio-controller; 96 #gpio-cells = <2>; 97 interrupt-controller; 98 #interrupt-cells = <2>; 99 interrupt-parent = <&irqc>; 100 gpio-ranges = <&pinctrl 0 0 152>; 101 clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>; 102 power-domains = <&cpg>; 103 resets = <&cpg R9A08G045_GPIO_RSTN>, 104 <&cpg R9A08G045_GPIO_PORT_RESETN>, 105 <&cpg R9A08G045_GPIO_SPARE_RESETN>; 106 }; 107 108 irqc: interrupt-controller@11050000 { 109 compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc"; 110 #interrupt-cells = <2>; 111 #address-cells = <0>; 112 interrupt-controller; 113 reg = <0 0x11050000 0 0x10000>; 114 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 117 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 135 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 136 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 156 interrupt-names = "nmi", 157 "irq0", "irq1", "irq2", "irq3", 158 "irq4", "irq5", "irq6", "irq7", 159 "tint0", "tint1", "tint2", "tint3", 160 "tint4", "tint5", "tint6", "tint7", 161 "tint8", "tint9", "tint10", "tint11", 162 "tint12", "tint13", "tint14", "tint15", 163 "tint16", "tint17", "tint18", "tint19", 164 "tint20", "tint21", "tint22", "tint23", 165 "tint24", "tint25", "tint26", "tint27", 166 "tint28", "tint29", "tint30", "tint31", 167 "bus-err"; 168 clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>, 169 <&cpg CPG_MOD R9A08G045_IA55_PCLK>; 170 clock-names = "clk", "pclk"; 171 power-domains = <&cpg>; 172 resets = <&cpg R9A08G045_IA55_RESETN>; 173 }; 174 175 sdhi0: mmc@11c00000 { 176 compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; 177 reg = <0x0 0x11c00000 0 0x10000>; 178 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 180 clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>, 181 <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>, 182 <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>, 183 <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>; 184 clock-names = "core", "clkh", "cd", "aclk"; 185 resets = <&cpg R9A08G045_SDHI0_IXRST>; 186 power-domains = <&cpg>; 187 status = "disabled"; 188 }; 189 190 sdhi1: mmc@11c10000 { 191 compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; 192 reg = <0x0 0x11c10000 0 0x10000>; 193 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 195 clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>, 196 <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>, 197 <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>, 198 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>; 199 clock-names = "core", "clkh", "cd", "aclk"; 200 resets = <&cpg R9A08G045_SDHI1_IXRST>; 201 power-domains = <&cpg>; 202 status = "disabled"; 203 }; 204 205 sdhi2: mmc@11c20000 { 206 compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; 207 reg = <0x0 0x11c20000 0 0x10000>; 208 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>, 211 <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>, 212 <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>, 213 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>; 214 clock-names = "core", "clkh", "cd", "aclk"; 215 resets = <&cpg R9A08G045_SDHI2_IXRST>; 216 power-domains = <&cpg>; 217 status = "disabled"; 218 }; 219 220 eth0: ethernet@11c30000 { 221 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; 222 reg = <0 0x11c30000 0 0x10000>; 223 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 226 interrupt-names = "mux", "fil", "arp_ns"; 227 phy-mode = "rgmii"; 228 clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>, 229 <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>, 230 <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>; 231 clock-names = "axi", "chi", "refclk"; 232 resets = <&cpg R9A08G045_ETH0_RST_HW_N>; 233 power-domains = <&cpg>; 234 #address-cells = <1>; 235 #size-cells = <0>; 236 status = "disabled"; 237 }; 238 239 eth1: ethernet@11c40000 { 240 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; 241 reg = <0 0x11c40000 0 0x10000>; 242 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 245 interrupt-names = "mux", "fil", "arp_ns"; 246 phy-mode = "rgmii"; 247 clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>, 248 <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>, 249 <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>; 250 clock-names = "axi", "chi", "refclk"; 251 resets = <&cpg R9A08G045_ETH1_RST_HW_N>; 252 power-domains = <&cpg>; 253 #address-cells = <1>; 254 #size-cells = <0>; 255 status = "disabled"; 256 }; 257 258 gic: interrupt-controller@12400000 { 259 compatible = "arm,gic-v3"; 260 #interrupt-cells = <3>; 261 #address-cells = <0>; 262 interrupt-controller; 263 reg = <0x0 0x12400000 0 0x40000>, 264 <0x0 0x12440000 0 0x60000>; 265 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 266 }; 267 }; 268 269 timer { 270 compatible = "arm,armv8-timer"; 271 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 272 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 273 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 274 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 275 }; 276}; 277