1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a07g044-cpg.h> 10 11/ { 12 compatible = "renesas,r9a07g044"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_clk1: audio1-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by boards that provide it */ 20 clock-frequency = <0>; 21 }; 22 23 audio_clk2: audio2-clk { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 /* This value must be overridden by boards that provide it */ 27 clock-frequency = <0>; 28 }; 29 30 /* External CAN clock - to be overridden by boards that provide it */ 31 can_clk: can-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ 38 extal_clk: extal-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 /* This value must be overridden by the board */ 42 clock-frequency = <0>; 43 }; 44 45 cluster0_opp: opp-table-0 { 46 compatible = "operating-points-v2"; 47 opp-shared; 48 49 opp-150000000 { 50 opp-hz = /bits/ 64 <150000000>; 51 opp-microvolt = <1100000>; 52 clock-latency-ns = <300000>; 53 }; 54 opp-300000000 { 55 opp-hz = /bits/ 64 <300000000>; 56 opp-microvolt = <1100000>; 57 clock-latency-ns = <300000>; 58 }; 59 opp-600000000 { 60 opp-hz = /bits/ 64 <600000000>; 61 opp-microvolt = <1100000>; 62 clock-latency-ns = <300000>; 63 }; 64 opp-1200000000 { 65 opp-hz = /bits/ 64 <1200000000>; 66 opp-microvolt = <1100000>; 67 clock-latency-ns = <300000>; 68 opp-suspend; 69 }; 70 }; 71 72 cpus { 73 #address-cells = <1>; 74 #size-cells = <0>; 75 76 cpu-map { 77 cluster0 { 78 core0 { 79 cpu = <&cpu0>; 80 }; 81 core1 { 82 cpu = <&cpu1>; 83 }; 84 }; 85 }; 86 87 cpu0: cpu@0 { 88 compatible = "arm,cortex-a55"; 89 reg = <0>; 90 device_type = "cpu"; 91 #cooling-cells = <2>; 92 next-level-cache = <&L3_CA55>; 93 enable-method = "psci"; 94 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>; 95 operating-points-v2 = <&cluster0_opp>; 96 }; 97 98 cpu1: cpu@100 { 99 compatible = "arm,cortex-a55"; 100 reg = <0x100>; 101 device_type = "cpu"; 102 next-level-cache = <&L3_CA55>; 103 enable-method = "psci"; 104 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>; 105 operating-points-v2 = <&cluster0_opp>; 106 }; 107 108 L3_CA55: cache-controller-0 { 109 compatible = "cache"; 110 cache-unified; 111 cache-size = <0x40000>; 112 cache-level = <3>; 113 }; 114 }; 115 116 gpu_opp_table: opp-table-1 { 117 compatible = "operating-points-v2"; 118 119 opp-500000000 { 120 opp-hz = /bits/ 64 <500000000>; 121 opp-microvolt = <1100000>; 122 }; 123 124 opp-400000000 { 125 opp-hz = /bits/ 64 <400000000>; 126 opp-microvolt = <1100000>; 127 }; 128 129 opp-250000000 { 130 opp-hz = /bits/ 64 <250000000>; 131 opp-microvolt = <1100000>; 132 }; 133 134 opp-200000000 { 135 opp-hz = /bits/ 64 <200000000>; 136 opp-microvolt = <1100000>; 137 }; 138 139 opp-125000000 { 140 opp-hz = /bits/ 64 <125000000>; 141 opp-microvolt = <1100000>; 142 }; 143 144 opp-100000000 { 145 opp-hz = /bits/ 64 <100000000>; 146 opp-microvolt = <1100000>; 147 }; 148 149 opp-62500000 { 150 opp-hz = /bits/ 64 <62500000>; 151 opp-microvolt = <1100000>; 152 }; 153 154 opp-50000000 { 155 opp-hz = /bits/ 64 <50000000>; 156 opp-microvolt = <1100000>; 157 }; 158 }; 159 160 pmu { 161 compatible = "arm,cortex-a55-pmu"; 162 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 163 }; 164 165 psci { 166 compatible = "arm,psci-1.0", "arm,psci-0.2"; 167 method = "smc"; 168 }; 169 170 soc: soc { 171 compatible = "simple-bus"; 172 interrupt-parent = <&gic>; 173 #address-cells = <2>; 174 #size-cells = <2>; 175 ranges; 176 177 mtu3: timer@10001200 { 178 compatible = "renesas,r9a07g044-mtu3", 179 "renesas,rz-mtu3"; 180 reg = <0 0x10001200 0 0xb00>; 181 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>, 182 <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>, 183 <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>, 184 <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>, 185 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>, 186 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>, 187 <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>, 188 <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>, 189 <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>, 190 <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>, 191 <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>, 192 <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>, 193 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>, 194 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>, 195 <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>, 196 <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>, 197 <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>, 198 <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>, 199 <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>, 200 <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>, 201 <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>, 202 <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>, 203 <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>, 204 <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>, 205 <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>, 206 <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>, 207 <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>, 208 <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>, 209 <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>, 210 <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>, 211 <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>, 212 <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>, 213 <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>, 214 <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>, 215 <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>, 216 <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>, 217 <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>, 218 <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>, 219 <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 220 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 221 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>, 222 <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>, 223 <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>, 224 <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>; 225 interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", 226 "tciv0", "tgie0", "tgif0", 227 "tgia1", "tgib1", "tciv1", "tciu1", 228 "tgia2", "tgib2", "tciv2", "tciu2", 229 "tgia3", "tgib3", "tgic3", "tgid3", 230 "tciv3", 231 "tgia4", "tgib4", "tgic4", "tgid4", 232 "tciv4", 233 "tgiu5", "tgiv5", "tgiw5", 234 "tgia6", "tgib6", "tgic6", "tgid6", 235 "tciv6", 236 "tgia7", "tgib7", "tgic7", "tgid7", 237 "tciv7", 238 "tgia8", "tgib8", "tgic8", "tgid8", 239 "tciv8", "tciu8"; 240 clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; 241 power-domains = <&cpg>; 242 resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; 243 #pwm-cells = <2>; 244 status = "disabled"; 245 }; 246 247 ssi0: ssi@10049c00 { 248 compatible = "renesas,r9a07g044-ssi", 249 "renesas,rz-ssi"; 250 reg = <0 0x10049c00 0 0x400>; 251 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>, 253 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>; 254 interrupt-names = "int_req", "dma_rx", "dma_tx"; 255 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>, 256 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>, 257 <&audio_clk1>, <&audio_clk2>; 258 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 259 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>; 260 dmas = <&dmac 0x2655>, <&dmac 0x2656>; 261 dma-names = "tx", "rx"; 262 power-domains = <&cpg>; 263 #sound-dai-cells = <0>; 264 status = "disabled"; 265 }; 266 267 ssi1: ssi@1004a000 { 268 compatible = "renesas,r9a07g044-ssi", 269 "renesas,rz-ssi"; 270 reg = <0 0x1004a000 0 0x400>; 271 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>, 273 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>; 274 interrupt-names = "int_req", "dma_rx", "dma_tx"; 275 clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>, 276 <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>, 277 <&audio_clk1>, <&audio_clk2>; 278 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 279 resets = <&cpg R9A07G044_SSI1_RST_M2_REG>; 280 dmas = <&dmac 0x2659>, <&dmac 0x265a>; 281 dma-names = "tx", "rx"; 282 power-domains = <&cpg>; 283 #sound-dai-cells = <0>; 284 status = "disabled"; 285 }; 286 287 ssi2: ssi@1004a400 { 288 compatible = "renesas,r9a07g044-ssi", 289 "renesas,rz-ssi"; 290 reg = <0 0x1004a400 0 0x400>; 291 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>; 293 interrupt-names = "int_req", "dma_rt"; 294 clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>, 295 <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>, 296 <&audio_clk1>, <&audio_clk2>; 297 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 298 resets = <&cpg R9A07G044_SSI2_RST_M2_REG>; 299 dmas = <&dmac 0x265f>; 300 dma-names = "rt"; 301 power-domains = <&cpg>; 302 #sound-dai-cells = <0>; 303 status = "disabled"; 304 }; 305 306 ssi3: ssi@1004a800 { 307 compatible = "renesas,r9a07g044-ssi", 308 "renesas,rz-ssi"; 309 reg = <0 0x1004a800 0 0x400>; 310 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>, 312 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 313 interrupt-names = "int_req", "dma_rx", "dma_tx"; 314 clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>, 315 <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>, 316 <&audio_clk1>, <&audio_clk2>; 317 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 318 resets = <&cpg R9A07G044_SSI3_RST_M2_REG>; 319 dmas = <&dmac 0x2661>, <&dmac 0x2662>; 320 dma-names = "tx", "rx"; 321 power-domains = <&cpg>; 322 #sound-dai-cells = <0>; 323 status = "disabled"; 324 }; 325 326 spi0: spi@1004ac00 { 327 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; 328 reg = <0 0x1004ac00 0 0x400>; 329 interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 330 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; 332 interrupt-names = "error", "rx", "tx"; 333 clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>; 334 resets = <&cpg R9A07G044_RSPI0_RST>; 335 dmas = <&dmac 0x2e95>, <&dmac 0x2e96>; 336 dma-names = "tx", "rx"; 337 power-domains = <&cpg>; 338 num-cs = <1>; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 status = "disabled"; 342 }; 343 344 spi1: spi@1004b000 { 345 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; 346 reg = <0 0x1004b000 0 0x400>; 347 interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; 350 interrupt-names = "error", "rx", "tx"; 351 clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>; 352 resets = <&cpg R9A07G044_RSPI1_RST>; 353 dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>; 354 dma-names = "tx", "rx"; 355 power-domains = <&cpg>; 356 num-cs = <1>; 357 #address-cells = <1>; 358 #size-cells = <0>; 359 status = "disabled"; 360 }; 361 362 spi2: spi@1004b400 { 363 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz"; 364 reg = <0 0x1004b400 0 0x400>; 365 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; 368 interrupt-names = "error", "rx", "tx"; 369 clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>; 370 resets = <&cpg R9A07G044_RSPI2_RST>; 371 dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>; 372 dma-names = "tx", "rx"; 373 power-domains = <&cpg>; 374 num-cs = <1>; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 status = "disabled"; 378 }; 379 380 scif0: serial@1004b800 { 381 compatible = "renesas,scif-r9a07g044"; 382 reg = <0 0x1004b800 0 0x400>; 383 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 389 interrupt-names = "eri", "rxi", "txi", 390 "bri", "dri", "tei"; 391 clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>; 392 clock-names = "fck"; 393 power-domains = <&cpg>; 394 resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>; 395 status = "disabled"; 396 }; 397 398 scif1: serial@1004bc00 { 399 compatible = "renesas,scif-r9a07g044"; 400 reg = <0 0x1004bc00 0 0x400>; 401 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 407 interrupt-names = "eri", "rxi", "txi", 408 "bri", "dri", "tei"; 409 clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>; 410 clock-names = "fck"; 411 power-domains = <&cpg>; 412 resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>; 413 status = "disabled"; 414 }; 415 416 scif2: serial@1004c000 { 417 compatible = "renesas,scif-r9a07g044"; 418 reg = <0 0x1004c000 0 0x400>; 419 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; 425 interrupt-names = "eri", "rxi", "txi", 426 "bri", "dri", "tei"; 427 clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>; 428 clock-names = "fck"; 429 power-domains = <&cpg>; 430 resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>; 431 status = "disabled"; 432 }; 433 434 scif3: serial@1004c400 { 435 compatible = "renesas,scif-r9a07g044"; 436 reg = <0 0x1004c400 0 0x400>; 437 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; 443 interrupt-names = "eri", "rxi", "txi", 444 "bri", "dri", "tei"; 445 clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>; 446 clock-names = "fck"; 447 power-domains = <&cpg>; 448 resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>; 449 status = "disabled"; 450 }; 451 452 scif4: serial@1004c800 { 453 compatible = "renesas,scif-r9a07g044"; 454 reg = <0 0x1004c800 0 0x400>; 455 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 461 interrupt-names = "eri", "rxi", "txi", 462 "bri", "dri", "tei"; 463 clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>; 464 clock-names = "fck"; 465 power-domains = <&cpg>; 466 resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>; 467 status = "disabled"; 468 }; 469 470 sci0: serial@1004d000 { 471 compatible = "renesas,r9a07g044-sci", "renesas,sci"; 472 reg = <0 0x1004d000 0 0x400>; 473 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>, 475 <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>, 476 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 477 interrupt-names = "eri", "rxi", "txi", "tei"; 478 clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>; 479 clock-names = "fck"; 480 power-domains = <&cpg>; 481 resets = <&cpg R9A07G044_SCI0_RST>; 482 status = "disabled"; 483 }; 484 485 sci1: serial@1004d400 { 486 compatible = "renesas,r9a07g044-sci", "renesas,sci"; 487 reg = <0 0x1004d400 0 0x400>; 488 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>, 490 <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>, 491 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 492 interrupt-names = "eri", "rxi", "txi", "tei"; 493 clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>; 494 clock-names = "fck"; 495 power-domains = <&cpg>; 496 resets = <&cpg R9A07G044_SCI1_RST>; 497 status = "disabled"; 498 }; 499 500 canfd: can@10050000 { 501 compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd"; 502 reg = <0 0x10050000 0 0x8000>; 503 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 511 interrupt-names = "g_err", "g_recc", 512 "ch0_err", "ch0_rec", "ch0_trx", 513 "ch1_err", "ch1_rec", "ch1_trx"; 514 clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>, 515 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>, 516 <&can_clk>; 517 clock-names = "fck", "canfd", "can_clk"; 518 assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>; 519 assigned-clock-rates = <50000000>; 520 resets = <&cpg R9A07G044_CANFD_RSTP_N>, 521 <&cpg R9A07G044_CANFD_RSTC_N>; 522 reset-names = "rstp_n", "rstc_n"; 523 power-domains = <&cpg>; 524 status = "disabled"; 525 526 channel0 { 527 status = "disabled"; 528 }; 529 channel1 { 530 status = "disabled"; 531 }; 532 }; 533 534 i2c0: i2c@10058000 { 535 #address-cells = <1>; 536 #size-cells = <0>; 537 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; 538 reg = <0 0x10058000 0 0x400>; 539 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>, 541 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>, 542 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 547 interrupt-names = "tei", "ri", "ti", "spi", "sti", 548 "naki", "ali", "tmoi"; 549 clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>; 550 clock-frequency = <100000>; 551 resets = <&cpg R9A07G044_I2C0_MRST>; 552 power-domains = <&cpg>; 553 status = "disabled"; 554 }; 555 556 i2c1: i2c@10058400 { 557 #address-cells = <1>; 558 #size-cells = <0>; 559 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; 560 reg = <0 0x10058400 0 0x400>; 561 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>, 563 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>, 564 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 569 interrupt-names = "tei", "ri", "ti", "spi", "sti", 570 "naki", "ali", "tmoi"; 571 clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>; 572 clock-frequency = <100000>; 573 resets = <&cpg R9A07G044_I2C1_MRST>; 574 power-domains = <&cpg>; 575 status = "disabled"; 576 }; 577 578 i2c2: i2c@10058800 { 579 #address-cells = <1>; 580 #size-cells = <0>; 581 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; 582 reg = <0 0x10058800 0 0x400>; 583 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 585 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 586 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 591 interrupt-names = "tei", "ri", "ti", "spi", "sti", 592 "naki", "ali", "tmoi"; 593 clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>; 594 clock-frequency = <100000>; 595 resets = <&cpg R9A07G044_I2C2_MRST>; 596 power-domains = <&cpg>; 597 status = "disabled"; 598 }; 599 600 i2c3: i2c@10058c00 { 601 #address-cells = <1>; 602 #size-cells = <0>; 603 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz"; 604 reg = <0 0x10058c00 0 0x400>; 605 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>, 607 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 608 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 613 interrupt-names = "tei", "ri", "ti", "spi", "sti", 614 "naki", "ali", "tmoi"; 615 clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>; 616 clock-frequency = <100000>; 617 resets = <&cpg R9A07G044_I2C3_MRST>; 618 power-domains = <&cpg>; 619 status = "disabled"; 620 }; 621 622 adc: adc@10059000 { 623 compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc"; 624 reg = <0 0x10059000 0 0x400>; 625 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>; 626 clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>, 627 <&cpg CPG_MOD R9A07G044_ADC_PCLK>; 628 clock-names = "adclk", "pclk"; 629 resets = <&cpg R9A07G044_ADC_PRESETN>, 630 <&cpg R9A07G044_ADC_ADRST_N>; 631 reset-names = "presetn", "adrst-n"; 632 power-domains = <&cpg>; 633 status = "disabled"; 634 635 #address-cells = <1>; 636 #size-cells = <0>; 637 638 channel@0 { 639 reg = <0>; 640 }; 641 channel@1 { 642 reg = <1>; 643 }; 644 channel@2 { 645 reg = <2>; 646 }; 647 channel@3 { 648 reg = <3>; 649 }; 650 channel@4 { 651 reg = <4>; 652 }; 653 channel@5 { 654 reg = <5>; 655 }; 656 channel@6 { 657 reg = <6>; 658 }; 659 channel@7 { 660 reg = <7>; 661 }; 662 }; 663 664 tsu: thermal@10059400 { 665 compatible = "renesas,r9a07g044-tsu", 666 "renesas,rzg2l-tsu"; 667 reg = <0 0x10059400 0 0x400>; 668 clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>; 669 resets = <&cpg R9A07G044_TSU_PRESETN>; 670 power-domains = <&cpg>; 671 #thermal-sensor-cells = <1>; 672 }; 673 674 sbc: spi@10060000 { 675 compatible = "renesas,r9a07g044-rpc-if", 676 "renesas,rzg2l-rpc-if"; 677 reg = <0 0x10060000 0 0x10000>, 678 <0 0x20000000 0 0x10000000>, 679 <0 0x10070000 0 0x10000>; 680 reg-names = "regs", "dirmap", "wbuf"; 681 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 682 clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>, 683 <&cpg CPG_MOD R9A07G044_SPI_CLK>; 684 resets = <&cpg R9A07G044_SPI_RST>; 685 power-domains = <&cpg>; 686 #address-cells = <1>; 687 #size-cells = <0>; 688 status = "disabled"; 689 }; 690 691 cru: video@10830000 { 692 compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru"; 693 reg = <0 0x10830000 0 0x400>; 694 clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>, 695 <&cpg CPG_MOD R9A07G044_CRU_PCLK>, 696 <&cpg CPG_MOD R9A07G044_CRU_ACLK>; 697 clock-names = "video", "apb", "axi"; 698 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 701 interrupt-names = "image_conv", "image_conv_err", "axi_mst_err"; 702 resets = <&cpg R9A07G044_CRU_PRESETN>, 703 <&cpg R9A07G044_CRU_ARESETN>; 704 reset-names = "presetn", "aresetn"; 705 power-domains = <&cpg>; 706 status = "disabled"; 707 708 ports { 709 #address-cells = <1>; 710 #size-cells = <0>; 711 712 port@0 { 713 #address-cells = <1>; 714 #size-cells = <0>; 715 716 reg = <0>; 717 cruparallel: endpoint@0 { 718 reg = <0>; 719 }; 720 }; 721 722 port@1 { 723 #address-cells = <1>; 724 #size-cells = <0>; 725 726 reg = <1>; 727 crucsi2: endpoint@0 { 728 reg = <0>; 729 remote-endpoint = <&csi2cru>; 730 }; 731 }; 732 }; 733 }; 734 735 csi2: csi2@10830400 { 736 compatible = "renesas,r9a07g044-csi2", "renesas,rzg2l-csi2"; 737 reg = <0 0x10830400 0 0xfc00>; 738 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&cpg CPG_MOD R9A07G044_CRU_SYSCLK>, 740 <&cpg CPG_MOD R9A07G044_CRU_VCLK>, 741 <&cpg CPG_MOD R9A07G044_CRU_PCLK>; 742 clock-names = "system", "video", "apb"; 743 resets = <&cpg R9A07G044_CRU_PRESETN>, 744 <&cpg R9A07G044_CRU_CMN_RSTB>; 745 reset-names = "presetn", "cmn-rstb"; 746 power-domains = <&cpg>; 747 status = "disabled"; 748 749 ports { 750 #address-cells = <1>; 751 #size-cells = <0>; 752 753 port@0 { 754 reg = <0>; 755 }; 756 757 port@1 { 758 #address-cells = <1>; 759 #size-cells = <0>; 760 reg = <1>; 761 762 csi2cru: endpoint@0 { 763 reg = <0>; 764 remote-endpoint = <&crucsi2>; 765 }; 766 }; 767 }; 768 }; 769 770 dsi: dsi@10850000 { 771 compatible = "renesas,r9a07g044-mipi-dsi", 772 "renesas,rzg2l-mipi-dsi"; 773 reg = <0 0x10850000 0 0x20000>; 774 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 781 interrupt-names = "seq0", "seq1", "vin1", "rcv", 782 "ferr", "ppi", "debug"; 783 clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>, 784 <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>, 785 <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>, 786 <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>, 787 <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>, 788 <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>; 789 clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk"; 790 resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>, 791 <&cpg R9A07G044_MIPI_DSI_ARESET_N>, 792 <&cpg R9A07G044_MIPI_DSI_PRESET_N>; 793 reset-names = "rst", "arst", "prst"; 794 power-domains = <&cpg>; 795 status = "disabled"; 796 }; 797 798 vspd: vsp@10870000 { 799 compatible = "renesas,r9a07g044-vsp2"; 800 reg = <0 0x10870000 0 0x10000>; 801 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 802 clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, 803 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, 804 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; 805 clock-names = "aclk", "pclk", "vclk"; 806 power-domains = <&cpg>; 807 resets = <&cpg R9A07G044_LCDC_RESET_N>; 808 renesas,fcp = <&fcpvd>; 809 }; 810 811 fcpvd: fcp@10880000 { 812 compatible = "renesas,r9a07g044-fcpvd", 813 "renesas,fcpv"; 814 reg = <0 0x10880000 0 0x10000>; 815 clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>, 816 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>, 817 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>; 818 clock-names = "aclk", "pclk", "vclk"; 819 power-domains = <&cpg>; 820 resets = <&cpg R9A07G044_LCDC_RESET_N>; 821 }; 822 823 cpg: clock-controller@11010000 { 824 compatible = "renesas,r9a07g044-cpg"; 825 reg = <0 0x11010000 0 0x10000>; 826 clocks = <&extal_clk>; 827 clock-names = "extal"; 828 #clock-cells = <2>; 829 #reset-cells = <1>; 830 #power-domain-cells = <0>; 831 }; 832 833 sysc: system-controller@11020000 { 834 compatible = "renesas,r9a07g044-sysc"; 835 reg = <0 0x11020000 0 0x10000>; 836 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 840 interrupt-names = "lpm_int", "ca55stbydone_int", 841 "cm33stbyr_int", "ca55_deny"; 842 status = "disabled"; 843 }; 844 845 pinctrl: pinctrl@11030000 { 846 compatible = "renesas,r9a07g044-pinctrl"; 847 reg = <0 0x11030000 0 0x10000>; 848 gpio-controller; 849 #gpio-cells = <2>; 850 #interrupt-cells = <2>; 851 interrupt-parent = <&irqc>; 852 interrupt-controller; 853 gpio-ranges = <&pinctrl 0 0 392>; 854 clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>; 855 power-domains = <&cpg>; 856 resets = <&cpg R9A07G044_GPIO_RSTN>, 857 <&cpg R9A07G044_GPIO_PORT_RESETN>, 858 <&cpg R9A07G044_GPIO_SPARE_RESETN>; 859 }; 860 861 irqc: interrupt-controller@110a0000 { 862 compatible = "renesas,r9a07g044-irqc", 863 "renesas,rzg2l-irqc"; 864 #interrupt-cells = <2>; 865 #address-cells = <0>; 866 interrupt-controller; 867 reg = <0 0x110a0000 0 0x10000>; 868 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; 909 clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, 910 <&cpg CPG_MOD R9A07G044_IA55_PCLK>; 911 clock-names = "clk", "pclk"; 912 power-domains = <&cpg>; 913 resets = <&cpg R9A07G044_IA55_RESETN>; 914 }; 915 916 dmac: dma-controller@11820000 { 917 compatible = "renesas,r9a07g044-dmac", 918 "renesas,rz-dmac"; 919 reg = <0 0x11820000 0 0x10000>, 920 <0 0x11830000 0 0x10000>; 921 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, 922 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 923 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 924 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 925 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 926 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 927 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 928 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, 929 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, 930 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 931 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 932 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, 933 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 934 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, 935 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 936 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 937 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; 938 interrupt-names = "error", 939 "ch0", "ch1", "ch2", "ch3", 940 "ch4", "ch5", "ch6", "ch7", 941 "ch8", "ch9", "ch10", "ch11", 942 "ch12", "ch13", "ch14", "ch15"; 943 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>, 944 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>; 945 clock-names = "main", "register"; 946 power-domains = <&cpg>; 947 resets = <&cpg R9A07G044_DMAC_ARESETN>, 948 <&cpg R9A07G044_DMAC_RST_ASYNC>; 949 reset-names = "arst", "rst_async"; 950 #dma-cells = <1>; 951 dma-channels = <16>; 952 }; 953 954 gpu: gpu@11840000 { 955 compatible = "renesas,r9a07g044-mali", 956 "arm,mali-bifrost"; 957 reg = <0x0 0x11840000 0x0 0x10000>; 958 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 962 interrupt-names = "job", "mmu", "gpu", "event"; 963 clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>, 964 <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>, 965 <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>; 966 clock-names = "gpu", "bus", "bus_ace"; 967 power-domains = <&cpg>; 968 resets = <&cpg R9A07G044_GPU_RESETN>, 969 <&cpg R9A07G044_GPU_AXI_RESETN>, 970 <&cpg R9A07G044_GPU_ACE_RESETN>; 971 reset-names = "rst", "axi_rst", "ace_rst"; 972 operating-points-v2 = <&gpu_opp_table>; 973 }; 974 975 gic: interrupt-controller@11900000 { 976 compatible = "arm,gic-v3"; 977 #interrupt-cells = <3>; 978 #address-cells = <0>; 979 interrupt-controller; 980 reg = <0x0 0x11900000 0 0x40000>, 981 <0x0 0x11940000 0 0x60000>; 982 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 983 }; 984 985 sdhi0: mmc@11c00000 { 986 compatible = "renesas,sdhi-r9a07g044", 987 "renesas,rcar-gen3-sdhi"; 988 reg = <0x0 0x11c00000 0 0x10000>; 989 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 991 clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>, 992 <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>, 993 <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>, 994 <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>; 995 clock-names = "core", "clkh", "cd", "aclk"; 996 resets = <&cpg R9A07G044_SDHI0_IXRST>; 997 power-domains = <&cpg>; 998 status = "disabled"; 999 }; 1000 1001 sdhi1: mmc@11c10000 { 1002 compatible = "renesas,sdhi-r9a07g044", 1003 "renesas,rcar-gen3-sdhi"; 1004 reg = <0x0 0x11c10000 0 0x10000>; 1005 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1006 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1007 clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>, 1008 <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>, 1009 <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>, 1010 <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>; 1011 clock-names = "core", "clkh", "cd", "aclk"; 1012 resets = <&cpg R9A07G044_SDHI1_IXRST>; 1013 power-domains = <&cpg>; 1014 status = "disabled"; 1015 }; 1016 1017 eth0: ethernet@11c20000 { 1018 compatible = "renesas,r9a07g044-gbeth", 1019 "renesas,rzg2l-gbeth"; 1020 reg = <0 0x11c20000 0 0x10000>; 1021 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1024 interrupt-names = "mux", "fil", "arp_ns"; 1025 phy-mode = "rgmii"; 1026 clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>, 1027 <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>, 1028 <&cpg CPG_CORE R9A07G044_CLK_HP>; 1029 clock-names = "axi", "chi", "refclk"; 1030 resets = <&cpg R9A07G044_ETH0_RST_HW_N>; 1031 power-domains = <&cpg>; 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 status = "disabled"; 1035 }; 1036 1037 eth1: ethernet@11c30000 { 1038 compatible = "renesas,r9a07g044-gbeth", 1039 "renesas,rzg2l-gbeth"; 1040 reg = <0 0x11c30000 0 0x10000>; 1041 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 1042 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1043 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1044 interrupt-names = "mux", "fil", "arp_ns"; 1045 phy-mode = "rgmii"; 1046 clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>, 1047 <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>, 1048 <&cpg CPG_CORE R9A07G044_CLK_HP>; 1049 clock-names = "axi", "chi", "refclk"; 1050 resets = <&cpg R9A07G044_ETH1_RST_HW_N>; 1051 power-domains = <&cpg>; 1052 #address-cells = <1>; 1053 #size-cells = <0>; 1054 status = "disabled"; 1055 }; 1056 1057 phyrst: usbphy-ctrl@11c40000 { 1058 compatible = "renesas,r9a07g044-usbphy-ctrl", 1059 "renesas,rzg2l-usbphy-ctrl"; 1060 reg = <0 0x11c40000 0 0x10000>; 1061 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>; 1062 resets = <&cpg R9A07G044_USB_PRESETN>; 1063 power-domains = <&cpg>; 1064 #reset-cells = <1>; 1065 status = "disabled"; 1066 }; 1067 1068 ohci0: usb@11c50000 { 1069 compatible = "generic-ohci"; 1070 reg = <0 0x11c50000 0 0x100>; 1071 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1072 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 1073 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>; 1074 resets = <&phyrst 0>, 1075 <&cpg R9A07G044_USB_U2H0_HRESETN>; 1076 phys = <&usb2_phy0 1>; 1077 phy-names = "usb"; 1078 power-domains = <&cpg>; 1079 status = "disabled"; 1080 }; 1081 1082 ohci1: usb@11c70000 { 1083 compatible = "generic-ohci"; 1084 reg = <0 0x11c70000 0 0x100>; 1085 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1086 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 1087 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>; 1088 resets = <&phyrst 1>, 1089 <&cpg R9A07G044_USB_U2H1_HRESETN>; 1090 phys = <&usb2_phy1 1>; 1091 phy-names = "usb"; 1092 power-domains = <&cpg>; 1093 status = "disabled"; 1094 }; 1095 1096 ehci0: usb@11c50100 { 1097 compatible = "generic-ehci"; 1098 reg = <0 0x11c50100 0 0x100>; 1099 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1100 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 1101 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>; 1102 resets = <&phyrst 0>, 1103 <&cpg R9A07G044_USB_U2H0_HRESETN>; 1104 phys = <&usb2_phy0 2>; 1105 phy-names = "usb"; 1106 companion = <&ohci0>; 1107 power-domains = <&cpg>; 1108 status = "disabled"; 1109 }; 1110 1111 ehci1: usb@11c70100 { 1112 compatible = "generic-ehci"; 1113 reg = <0 0x11c70100 0 0x100>; 1114 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1115 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 1116 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>; 1117 resets = <&phyrst 1>, 1118 <&cpg R9A07G044_USB_U2H1_HRESETN>; 1119 phys = <&usb2_phy1 2>; 1120 phy-names = "usb"; 1121 companion = <&ohci1>; 1122 power-domains = <&cpg>; 1123 status = "disabled"; 1124 }; 1125 1126 usb2_phy0: usb-phy@11c50200 { 1127 compatible = "renesas,usb2-phy-r9a07g044", 1128 "renesas,rzg2l-usb2-phy"; 1129 reg = <0 0x11c50200 0 0x700>; 1130 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1131 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 1132 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>; 1133 resets = <&phyrst 0>; 1134 #phy-cells = <1>; 1135 power-domains = <&cpg>; 1136 status = "disabled"; 1137 }; 1138 1139 usb2_phy1: usb-phy@11c70200 { 1140 compatible = "renesas,usb2-phy-r9a07g044", 1141 "renesas,rzg2l-usb2-phy"; 1142 reg = <0 0x11c70200 0 0x700>; 1143 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1144 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 1145 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>; 1146 resets = <&phyrst 1>; 1147 #phy-cells = <1>; 1148 power-domains = <&cpg>; 1149 status = "disabled"; 1150 }; 1151 1152 hsusb: usb@11c60000 { 1153 compatible = "renesas,usbhs-r9a07g044", 1154 "renesas,rza2-usbhs"; 1155 reg = <0 0x11c60000 0 0x10000>; 1156 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, 1157 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1160 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>, 1161 <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>; 1162 resets = <&phyrst 0>, 1163 <&cpg R9A07G044_USB_U2P_EXL_SYSRST>; 1164 renesas,buswait = <7>; 1165 phys = <&usb2_phy0 3>; 1166 phy-names = "usb"; 1167 power-domains = <&cpg>; 1168 status = "disabled"; 1169 }; 1170 1171 wdt0: watchdog@12800800 { 1172 compatible = "renesas,r9a07g044-wdt", 1173 "renesas,rzg2l-wdt"; 1174 reg = <0 0x12800800 0 0x400>; 1175 clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>, 1176 <&cpg CPG_MOD R9A07G044_WDT0_CLK>; 1177 clock-names = "pclk", "oscclk"; 1178 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1180 interrupt-names = "wdt", "perrout"; 1181 resets = <&cpg R9A07G044_WDT0_PRESETN>; 1182 power-domains = <&cpg>; 1183 status = "disabled"; 1184 }; 1185 1186 wdt1: watchdog@12800c00 { 1187 compatible = "renesas,r9a07g044-wdt", 1188 "renesas,rzg2l-wdt"; 1189 reg = <0 0x12800C00 0 0x400>; 1190 clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>, 1191 <&cpg CPG_MOD R9A07G044_WDT1_CLK>; 1192 clock-names = "pclk", "oscclk"; 1193 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1195 interrupt-names = "wdt", "perrout"; 1196 resets = <&cpg R9A07G044_WDT1_PRESETN>; 1197 power-domains = <&cpg>; 1198 status = "disabled"; 1199 }; 1200 1201 ostm0: timer@12801000 { 1202 compatible = "renesas,r9a07g044-ostm", 1203 "renesas,ostm"; 1204 reg = <0x0 0x12801000 0x0 0x400>; 1205 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>; 1206 clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>; 1207 resets = <&cpg R9A07G044_OSTM0_PRESETZ>; 1208 power-domains = <&cpg>; 1209 status = "disabled"; 1210 }; 1211 1212 ostm1: timer@12801400 { 1213 compatible = "renesas,r9a07g044-ostm", 1214 "renesas,ostm"; 1215 reg = <0x0 0x12801400 0x0 0x400>; 1216 interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; 1217 clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>; 1218 resets = <&cpg R9A07G044_OSTM1_PRESETZ>; 1219 power-domains = <&cpg>; 1220 status = "disabled"; 1221 }; 1222 1223 ostm2: timer@12801800 { 1224 compatible = "renesas,r9a07g044-ostm", 1225 "renesas,ostm"; 1226 reg = <0x0 0x12801800 0x0 0x400>; 1227 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>; 1228 clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>; 1229 resets = <&cpg R9A07G044_OSTM2_PRESETZ>; 1230 power-domains = <&cpg>; 1231 status = "disabled"; 1232 }; 1233 }; 1234 1235 thermal-zones { 1236 cpu-thermal { 1237 polling-delay-passive = <250>; 1238 polling-delay = <1000>; 1239 thermal-sensors = <&tsu 0>; 1240 sustainable-power = <717>; 1241 1242 cooling-maps { 1243 map0 { 1244 trip = <&target>; 1245 cooling-device = <&cpu0 0 2>; 1246 contribution = <1024>; 1247 }; 1248 }; 1249 1250 trips { 1251 sensor_crit: sensor-crit { 1252 temperature = <125000>; 1253 hysteresis = <1000>; 1254 type = "critical"; 1255 }; 1256 1257 target: trip-point { 1258 temperature = <100000>; 1259 hysteresis = <1000>; 1260 type = "passive"; 1261 }; 1262 }; 1263 }; 1264 }; 1265 1266 timer { 1267 compatible = "arm,armv8-timer"; 1268 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1269 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1270 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1271 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 1272 }; 1273}; 1274