1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G2UL SoC 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a07g043-cpg.h> 10 11/ { 12 compatible = "renesas,r9a07g043"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_clk1: audio-clk1 { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by boards that provide it */ 20 clock-frequency = <0>; 21 }; 22 23 audio_clk2: audio-clk2 { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 /* This value must be overridden by boards that provide it */ 27 clock-frequency = <0>; 28 }; 29 30 /* External CAN clock - to be overridden by boards that provide it */ 31 can_clk: can-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <0>; 35 }; 36 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ 38 extal_clk: extal-clk { 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 41 /* This value must be overridden by the board */ 42 clock-frequency = <0>; 43 }; 44 45 cluster0_opp: opp-table-0 { 46 compatible = "operating-points-v2"; 47 opp-shared; 48 49 opp-125000000 { 50 opp-hz = /bits/ 64 <125000000>; 51 opp-microvolt = <1100000>; 52 clock-latency-ns = <300000>; 53 }; 54 opp-250000000 { 55 opp-hz = /bits/ 64 <250000000>; 56 opp-microvolt = <1100000>; 57 clock-latency-ns = <300000>; 58 }; 59 opp-500000000 { 60 opp-hz = /bits/ 64 <500000000>; 61 opp-microvolt = <1100000>; 62 clock-latency-ns = <300000>; 63 }; 64 opp-1000000000 { 65 opp-hz = /bits/ 64 <1000000000>; 66 opp-microvolt = <1100000>; 67 clock-latency-ns = <300000>; 68 opp-suspend; 69 }; 70 }; 71 72 cpus { 73 #address-cells = <1>; 74 #size-cells = <0>; 75 76 cpu0: cpu@0 { 77 compatible = "arm,cortex-a55"; 78 reg = <0>; 79 device_type = "cpu"; 80 #cooling-cells = <2>; 81 next-level-cache = <&L3_CA55>; 82 enable-method = "psci"; 83 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; 84 operating-points-v2 = <&cluster0_opp>; 85 }; 86 87 L3_CA55: cache-controller-0 { 88 compatible = "cache"; 89 cache-unified; 90 cache-size = <0x40000>; 91 }; 92 }; 93 94 psci { 95 compatible = "arm,psci-1.0", "arm,psci-0.2"; 96 method = "smc"; 97 }; 98 99 soc: soc { 100 compatible = "simple-bus"; 101 interrupt-parent = <&gic>; 102 #address-cells = <2>; 103 #size-cells = <2>; 104 ranges; 105 106 ssi0: ssi@10049c00 { 107 compatible = "renesas,r9a07g043-ssi", 108 "renesas,rz-ssi"; 109 reg = <0 0x10049c00 0 0x400>; 110 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 111 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>, 112 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, 113 <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>; 114 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 115 clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>, 116 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>, 117 <&audio_clk1>, <&audio_clk2>; 118 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 119 resets = <&cpg R9A07G043_SSI0_RST_M2_REG>; 120 dmas = <&dmac 0x2655>, <&dmac 0x2656>; 121 dma-names = "tx", "rx"; 122 power-domains = <&cpg>; 123 #sound-dai-cells = <0>; 124 status = "disabled"; 125 }; 126 127 ssi1: ssi@1004a000 { 128 compatible = "renesas,r9a07g043-ssi", 129 "renesas,rz-ssi"; 130 reg = <0 0x1004a000 0 0x400>; 131 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>, 133 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>, 134 <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>; 135 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 136 clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>, 137 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>, 138 <&audio_clk1>, <&audio_clk2>; 139 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 140 resets = <&cpg R9A07G043_SSI1_RST_M2_REG>; 141 dmas = <&dmac 0x2659>, <&dmac 0x265a>; 142 dma-names = "tx", "rx"; 143 power-domains = <&cpg>; 144 #sound-dai-cells = <0>; 145 status = "disabled"; 146 }; 147 148 ssi2: ssi@1004a400 { 149 compatible = "renesas,r9a07g043-ssi", 150 "renesas,rz-ssi"; 151 reg = <0 0x1004a400 0 0x400>; 152 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>, 154 <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>, 155 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>; 156 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 157 clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>, 158 <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>, 159 <&audio_clk1>, <&audio_clk2>; 160 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 161 resets = <&cpg R9A07G043_SSI2_RST_M2_REG>; 162 dmas = <&dmac 0x265f>; 163 dma-names = "rt"; 164 power-domains = <&cpg>; 165 #sound-dai-cells = <0>; 166 status = "disabled"; 167 }; 168 169 ssi3: ssi@1004a800 { 170 compatible = "renesas,r9a07g043-ssi", 171 "renesas,rz-ssi"; 172 reg = <0 0x1004a800 0 0x400>; 173 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>, 175 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>, 176 <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>; 177 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt"; 178 clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>, 179 <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>, 180 <&audio_clk1>, <&audio_clk2>; 181 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 182 resets = <&cpg R9A07G043_SSI3_RST_M2_REG>; 183 dmas = <&dmac 0x2661>, <&dmac 0x2662>; 184 dma-names = "tx", "rx"; 185 power-domains = <&cpg>; 186 #sound-dai-cells = <0>; 187 status = "disabled"; 188 }; 189 190 spi0: spi@1004ac00 { 191 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; 192 reg = <0 0x1004ac00 0 0x400>; 193 interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>; 196 interrupt-names = "error", "rx", "tx"; 197 clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>; 198 resets = <&cpg R9A07G043_RSPI0_RST>; 199 power-domains = <&cpg>; 200 num-cs = <1>; 201 #address-cells = <1>; 202 #size-cells = <0>; 203 status = "disabled"; 204 }; 205 206 spi1: spi@1004b000 { 207 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; 208 reg = <0 0x1004b000 0 0x400>; 209 interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>; 212 interrupt-names = "error", "rx", "tx"; 213 clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>; 214 resets = <&cpg R9A07G043_RSPI1_RST>; 215 power-domains = <&cpg>; 216 num-cs = <1>; 217 #address-cells = <1>; 218 #size-cells = <0>; 219 status = "disabled"; 220 }; 221 222 spi2: spi@1004b400 { 223 compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz"; 224 reg = <0 0x1004b400 0 0x400>; 225 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>; 228 interrupt-names = "error", "rx", "tx"; 229 clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>; 230 resets = <&cpg R9A07G043_RSPI2_RST>; 231 power-domains = <&cpg>; 232 num-cs = <1>; 233 #address-cells = <1>; 234 #size-cells = <0>; 235 status = "disabled"; 236 }; 237 238 scif0: serial@1004b800 { 239 compatible = "renesas,scif-r9a07g043", 240 "renesas,scif-r9a07g044"; 241 reg = <0 0x1004b800 0 0x400>; 242 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 248 interrupt-names = "eri", "rxi", "txi", 249 "bri", "dri", "tei"; 250 clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; 251 clock-names = "fck"; 252 power-domains = <&cpg>; 253 resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; 254 status = "disabled"; 255 }; 256 257 scif1: serial@1004bc00 { 258 compatible = "renesas,scif-r9a07g043", 259 "renesas,scif-r9a07g044"; 260 reg = <0 0x1004bc00 0 0x400>; 261 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 267 interrupt-names = "eri", "rxi", "txi", 268 "bri", "dri", "tei"; 269 clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>; 270 clock-names = "fck"; 271 power-domains = <&cpg>; 272 resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>; 273 status = "disabled"; 274 }; 275 276 scif2: serial@1004c000 { 277 compatible = "renesas,scif-r9a07g043", 278 "renesas,scif-r9a07g044"; 279 reg = <0 0x1004c000 0 0x400>; 280 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; 286 interrupt-names = "eri", "rxi", "txi", 287 "bri", "dri", "tei"; 288 clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>; 289 clock-names = "fck"; 290 power-domains = <&cpg>; 291 resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>; 292 status = "disabled"; 293 }; 294 295 scif3: serial@1004c400 { 296 compatible = "renesas,scif-r9a07g043", 297 "renesas,scif-r9a07g044"; 298 reg = <0 0x1004c400 0 0x400>; 299 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; 305 interrupt-names = "eri", "rxi", "txi", 306 "bri", "dri", "tei"; 307 clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>; 308 clock-names = "fck"; 309 power-domains = <&cpg>; 310 resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>; 311 status = "disabled"; 312 }; 313 314 scif4: serial@1004c800 { 315 compatible = "renesas,scif-r9a07g043", 316 "renesas,scif-r9a07g044"; 317 reg = <0 0x1004c800 0 0x400>; 318 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 324 interrupt-names = "eri", "rxi", "txi", 325 "bri", "dri", "tei"; 326 clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>; 327 clock-names = "fck"; 328 power-domains = <&cpg>; 329 resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>; 330 status = "disabled"; 331 }; 332 333 sci0: serial@1004d000 { 334 compatible = "renesas,r9a07g043-sci", "renesas,sci"; 335 reg = <0 0x1004d000 0 0x400>; 336 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 340 interrupt-names = "eri", "rxi", "txi", "tei"; 341 clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>; 342 clock-names = "fck"; 343 power-domains = <&cpg>; 344 resets = <&cpg R9A07G043_SCI0_RST>; 345 status = "disabled"; 346 }; 347 348 sci1: serial@1004d400 { 349 compatible = "renesas,r9a07g043-sci", "renesas,sci"; 350 reg = <0 0x1004d400 0 0x400>; 351 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>; 355 interrupt-names = "eri", "rxi", "txi", "tei"; 356 clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>; 357 clock-names = "fck"; 358 power-domains = <&cpg>; 359 resets = <&cpg R9A07G043_SCI1_RST>; 360 status = "disabled"; 361 }; 362 363 canfd: can@10050000 { 364 compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd"; 365 reg = <0 0x10050000 0 0x8000>; 366 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 369 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 370 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 371 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 374 interrupt-names = "g_err", "g_recc", 375 "ch0_err", "ch0_rec", "ch0_trx", 376 "ch1_err", "ch1_rec", "ch1_trx"; 377 clocks = <&cpg CPG_MOD R9A07G043_CANFD_PCLK>, 378 <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>, 379 <&can_clk>; 380 clock-names = "fck", "canfd", "can_clk"; 381 assigned-clocks = <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>; 382 assigned-clock-rates = <50000000>; 383 resets = <&cpg R9A07G043_CANFD_RSTP_N>, 384 <&cpg R9A07G043_CANFD_RSTC_N>; 385 reset-names = "rstp_n", "rstc_n"; 386 power-domains = <&cpg>; 387 status = "disabled"; 388 389 channel0 { 390 status = "disabled"; 391 }; 392 channel1 { 393 status = "disabled"; 394 }; 395 }; 396 397 i2c0: i2c@10058000 { 398 #address-cells = <1>; 399 #size-cells = <0>; 400 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 401 reg = <0 0x10058000 0 0x400>; 402 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>, 404 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>, 405 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 406 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 407 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 410 interrupt-names = "tei", "ri", "ti", "spi", "sti", 411 "naki", "ali", "tmoi"; 412 clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>; 413 clock-frequency = <100000>; 414 resets = <&cpg R9A07G043_I2C0_MRST>; 415 power-domains = <&cpg>; 416 status = "disabled"; 417 }; 418 419 i2c1: i2c@10058400 { 420 #address-cells = <1>; 421 #size-cells = <0>; 422 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 423 reg = <0 0x10058400 0 0x400>; 424 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>, 426 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>, 427 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 429 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 430 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 431 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 432 interrupt-names = "tei", "ri", "ti", "spi", "sti", 433 "naki", "ali", "tmoi"; 434 clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>; 435 clock-frequency = <100000>; 436 resets = <&cpg R9A07G043_I2C1_MRST>; 437 power-domains = <&cpg>; 438 status = "disabled"; 439 }; 440 441 i2c2: i2c@10058800 { 442 #address-cells = <1>; 443 #size-cells = <0>; 444 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 445 reg = <0 0x10058800 0 0x400>; 446 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 448 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 449 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 454 interrupt-names = "tei", "ri", "ti", "spi", "sti", 455 "naki", "ali", "tmoi"; 456 clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>; 457 clock-frequency = <100000>; 458 resets = <&cpg R9A07G043_I2C2_MRST>; 459 power-domains = <&cpg>; 460 status = "disabled"; 461 }; 462 463 i2c3: i2c@10058c00 { 464 #address-cells = <1>; 465 #size-cells = <0>; 466 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz"; 467 reg = <0 0x10058c00 0 0x400>; 468 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>, 470 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 471 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 476 interrupt-names = "tei", "ri", "ti", "spi", "sti", 477 "naki", "ali", "tmoi"; 478 clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>; 479 clock-frequency = <100000>; 480 resets = <&cpg R9A07G043_I2C3_MRST>; 481 power-domains = <&cpg>; 482 status = "disabled"; 483 }; 484 485 adc: adc@10059000 { 486 compatible = "renesas,r9a07g043-adc", "renesas,rzg2l-adc"; 487 reg = <0 0x10059000 0 0x400>; 488 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>; 489 clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>, 490 <&cpg CPG_MOD R9A07G043_ADC_PCLK>; 491 clock-names = "adclk", "pclk"; 492 resets = <&cpg R9A07G043_ADC_PRESETN>, 493 <&cpg R9A07G043_ADC_ADRST_N>; 494 reset-names = "presetn", "adrst-n"; 495 power-domains = <&cpg>; 496 status = "disabled"; 497 498 #address-cells = <1>; 499 #size-cells = <0>; 500 501 channel@0 { 502 reg = <0>; 503 }; 504 channel@1 { 505 reg = <1>; 506 }; 507 }; 508 509 tsu: thermal@10059400 { 510 compatible = "renesas,r9a07g043-tsu", 511 "renesas,rzg2l-tsu"; 512 reg = <0 0x10059400 0 0x400>; 513 clocks = <&cpg CPG_MOD R9A07G043_TSU_PCLK>; 514 resets = <&cpg R9A07G043_TSU_PRESETN>; 515 power-domains = <&cpg>; 516 #thermal-sensor-cells = <1>; 517 }; 518 519 sbc: spi@10060000 { 520 compatible = "renesas,r9a07g043-rpc-if", 521 "renesas,rzg2l-rpc-if"; 522 reg = <0 0x10060000 0 0x10000>, 523 <0 0x20000000 0 0x10000000>, 524 <0 0x10070000 0 0x10000>; 525 reg-names = "regs", "dirmap", "wbuf"; 526 clocks = <&cpg CPG_MOD R9A07G043_SPI_CLK2>, 527 <&cpg CPG_MOD R9A07G043_SPI_CLK>; 528 resets = <&cpg R9A07G043_SPI_RST>; 529 power-domains = <&cpg>; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 status = "disabled"; 533 }; 534 535 cpg: clock-controller@11010000 { 536 compatible = "renesas,r9a07g043-cpg"; 537 reg = <0 0x11010000 0 0x10000>; 538 clocks = <&extal_clk>; 539 clock-names = "extal"; 540 #clock-cells = <2>; 541 #reset-cells = <1>; 542 #power-domain-cells = <0>; 543 }; 544 545 sysc: system-controller@11020000 { 546 compatible = "renesas,r9a07g043-sysc"; 547 reg = <0 0x11020000 0 0x10000>; 548 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 552 interrupt-names = "lpm_int", "ca55stbydone_int", 553 "cm33stbyr_int", "ca55_deny"; 554 status = "disabled"; 555 }; 556 557 pinctrl: pinctrl@11030000 { 558 compatible = "renesas,r9a07g043-pinctrl"; 559 reg = <0 0x11030000 0 0x10000>; 560 gpio-controller; 561 #gpio-cells = <2>; 562 gpio-ranges = <&pinctrl 0 0 152>; 563 clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; 564 power-domains = <&cpg>; 565 resets = <&cpg R9A07G043_GPIO_RSTN>, 566 <&cpg R9A07G043_GPIO_PORT_RESETN>, 567 <&cpg R9A07G043_GPIO_SPARE_RESETN>; 568 }; 569 570 dmac: dma-controller@11820000 { 571 compatible = "renesas,r9a07g043-dmac", 572 "renesas,rz-dmac"; 573 reg = <0 0x11820000 0 0x10000>, 574 <0 0x11830000 0 0x10000>; 575 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, 576 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 577 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 578 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 579 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 580 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 581 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 582 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, 583 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, 584 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 585 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 586 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, 587 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 588 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, 589 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 590 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 591 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; 592 interrupt-names = "error", 593 "ch0", "ch1", "ch2", "ch3", 594 "ch4", "ch5", "ch6", "ch7", 595 "ch8", "ch9", "ch10", "ch11", 596 "ch12", "ch13", "ch14", "ch15"; 597 clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>, 598 <&cpg CPG_MOD R9A07G043_DMAC_PCLK>; 599 power-domains = <&cpg>; 600 resets = <&cpg R9A07G043_DMAC_ARESETN>, 601 <&cpg R9A07G043_DMAC_RST_ASYNC>; 602 #dma-cells = <1>; 603 dma-channels = <16>; 604 }; 605 606 gic: interrupt-controller@11900000 { 607 compatible = "arm,gic-v3"; 608 #interrupt-cells = <3>; 609 #address-cells = <0>; 610 interrupt-controller; 611 reg = <0x0 0x11900000 0 0x40000>, 612 <0x0 0x11940000 0 0x60000>; 613 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 614 }; 615 616 sdhi0: mmc@11c00000 { 617 compatible = "renesas,sdhi-r9a07g043", 618 "renesas,rcar-gen3-sdhi"; 619 reg = <0x0 0x11c00000 0 0x10000>; 620 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 622 clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>, 623 <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>, 624 <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>, 625 <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>; 626 clock-names = "core", "clkh", "cd", "aclk"; 627 resets = <&cpg R9A07G043_SDHI0_IXRST>; 628 power-domains = <&cpg>; 629 status = "disabled"; 630 }; 631 632 sdhi1: mmc@11c10000 { 633 compatible = "renesas,sdhi-r9a07g043", 634 "renesas,rcar-gen3-sdhi"; 635 reg = <0x0 0x11c10000 0 0x10000>; 636 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>, 639 <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>, 640 <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>, 641 <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>; 642 clock-names = "core", "clkh", "cd", "aclk"; 643 resets = <&cpg R9A07G043_SDHI1_IXRST>; 644 power-domains = <&cpg>; 645 status = "disabled"; 646 }; 647 648 eth0: ethernet@11c20000 { 649 compatible = "renesas,r9a07g043-gbeth", 650 "renesas,rzg2l-gbeth"; 651 reg = <0 0x11c20000 0 0x10000>; 652 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 655 interrupt-names = "mux", "fil", "arp_ns"; 656 phy-mode = "rgmii"; 657 clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>, 658 <&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>, 659 <&cpg CPG_CORE R9A07G043_CLK_HP>; 660 clock-names = "axi", "chi", "refclk"; 661 resets = <&cpg R9A07G043_ETH0_RST_HW_N>; 662 power-domains = <&cpg>; 663 #address-cells = <1>; 664 #size-cells = <0>; 665 status = "disabled"; 666 }; 667 668 eth1: ethernet@11c30000 { 669 compatible = "renesas,r9a07g043-gbeth", 670 "renesas,rzg2l-gbeth"; 671 reg = <0 0x11c30000 0 0x10000>; 672 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 675 interrupt-names = "mux", "fil", "arp_ns"; 676 phy-mode = "rgmii"; 677 clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>, 678 <&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>, 679 <&cpg CPG_CORE R9A07G043_CLK_HP>; 680 clock-names = "axi", "chi", "refclk"; 681 resets = <&cpg R9A07G043_ETH1_RST_HW_N>; 682 power-domains = <&cpg>; 683 #address-cells = <1>; 684 #size-cells = <0>; 685 status = "disabled"; 686 }; 687 688 phyrst: usbphy-ctrl@11c40000 { 689 compatible = "renesas,r9a07g043-usbphy-ctrl", 690 "renesas,rzg2l-usbphy-ctrl"; 691 reg = <0 0x11c40000 0 0x10000>; 692 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>; 693 resets = <&cpg R9A07G043_USB_PRESETN>; 694 power-domains = <&cpg>; 695 #reset-cells = <1>; 696 status = "disabled"; 697 }; 698 699 ohci0: usb@11c50000 { 700 compatible = "generic-ohci"; 701 reg = <0 0x11c50000 0 0x100>; 702 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 704 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; 705 resets = <&phyrst 0>, 706 <&cpg R9A07G043_USB_U2H0_HRESETN>; 707 phys = <&usb2_phy0 1>; 708 phy-names = "usb"; 709 power-domains = <&cpg>; 710 status = "disabled"; 711 }; 712 713 ohci1: usb@11c70000 { 714 compatible = "generic-ohci"; 715 reg = <0 0x11c70000 0 0x100>; 716 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 717 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 718 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; 719 resets = <&phyrst 1>, 720 <&cpg R9A07G043_USB_U2H1_HRESETN>; 721 phys = <&usb2_phy1 1>; 722 phy-names = "usb"; 723 power-domains = <&cpg>; 724 status = "disabled"; 725 }; 726 727 ehci0: usb@11c50100 { 728 compatible = "generic-ehci"; 729 reg = <0 0x11c50100 0 0x100>; 730 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 732 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; 733 resets = <&phyrst 0>, 734 <&cpg R9A07G043_USB_U2H0_HRESETN>; 735 phys = <&usb2_phy0 2>; 736 phy-names = "usb"; 737 companion = <&ohci0>; 738 power-domains = <&cpg>; 739 status = "disabled"; 740 }; 741 742 ehci1: usb@11c70100 { 743 compatible = "generic-ehci"; 744 reg = <0 0x11c70100 0 0x100>; 745 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 746 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 747 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; 748 resets = <&phyrst 1>, 749 <&cpg R9A07G043_USB_U2H1_HRESETN>; 750 phys = <&usb2_phy1 2>; 751 phy-names = "usb"; 752 companion = <&ohci1>; 753 power-domains = <&cpg>; 754 status = "disabled"; 755 }; 756 757 usb2_phy0: usb-phy@11c50200 { 758 compatible = "renesas,usb2-phy-r9a07g043", 759 "renesas,rzg2l-usb2-phy"; 760 reg = <0 0x11c50200 0 0x700>; 761 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 762 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 763 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>; 764 resets = <&phyrst 0>; 765 #phy-cells = <1>; 766 power-domains = <&cpg>; 767 status = "disabled"; 768 }; 769 770 usb2_phy1: usb-phy@11c70200 { 771 compatible = "renesas,usb2-phy-r9a07g043", 772 "renesas,rzg2l-usb2-phy"; 773 reg = <0 0x11c70200 0 0x700>; 774 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 776 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>; 777 resets = <&phyrst 1>; 778 #phy-cells = <1>; 779 power-domains = <&cpg>; 780 status = "disabled"; 781 }; 782 783 hsusb: usb@11c60000 { 784 compatible = "renesas,usbhs-r9a07g043", 785 "renesas,rza2-usbhs"; 786 reg = <0 0x11c60000 0 0x10000>; 787 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, 788 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 791 clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>, 792 <&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>; 793 resets = <&phyrst 0>, 794 <&cpg R9A07G043_USB_U2P_EXL_SYSRST>; 795 renesas,buswait = <7>; 796 phys = <&usb2_phy0 3>; 797 phy-names = "usb"; 798 power-domains = <&cpg>; 799 status = "disabled"; 800 }; 801 802 wdt0: watchdog@12800800 { 803 compatible = "renesas,r9a07g043-wdt", 804 "renesas,rzg2l-wdt"; 805 reg = <0 0x12800800 0 0x400>; 806 clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>, 807 <&cpg CPG_MOD R9A07G043_WDT0_CLK>; 808 clock-names = "pclk", "oscclk"; 809 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 810 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 811 interrupt-names = "wdt", "perrout"; 812 resets = <&cpg R9A07G043_WDT0_PRESETN>; 813 power-domains = <&cpg>; 814 status = "disabled"; 815 }; 816 817 wdt2: watchdog@12800400 { 818 compatible = "renesas,r9a07g043-wdt", 819 "renesas,rzg2l-wdt"; 820 reg = <0 0x12800400 0 0x400>; 821 clocks = <&cpg CPG_MOD R9A07G043_WDT2_PCLK>, 822 <&cpg CPG_MOD R9A07G043_WDT2_CLK>; 823 clock-names = "pclk", "oscclk"; 824 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 826 interrupt-names = "wdt", "perrout"; 827 resets = <&cpg R9A07G043_WDT2_PRESETN>; 828 power-domains = <&cpg>; 829 status = "disabled"; 830 }; 831 832 ostm0: timer@12801000 { 833 compatible = "renesas,r9a07g043-ostm", 834 "renesas,ostm"; 835 reg = <0x0 0x12801000 0x0 0x400>; 836 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>; 837 clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>; 838 resets = <&cpg R9A07G043_OSTM0_PRESETZ>; 839 power-domains = <&cpg>; 840 status = "disabled"; 841 }; 842 843 ostm1: timer@12801400 { 844 compatible = "renesas,r9a07g043-ostm", 845 "renesas,ostm"; 846 reg = <0x0 0x12801400 0x0 0x400>; 847 interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; 848 clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>; 849 resets = <&cpg R9A07G043_OSTM1_PRESETZ>; 850 power-domains = <&cpg>; 851 status = "disabled"; 852 }; 853 854 ostm2: timer@12801800 { 855 compatible = "renesas,r9a07g043-ostm", 856 "renesas,ostm"; 857 reg = <0x0 0x12801800 0x0 0x400>; 858 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>; 859 clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>; 860 resets = <&cpg R9A07G043_OSTM2_PRESETZ>; 861 power-domains = <&cpg>; 862 status = "disabled"; 863 }; 864 }; 865 866 thermal-zones { 867 cpu-thermal { 868 polling-delay-passive = <250>; 869 polling-delay = <1000>; 870 thermal-sensors = <&tsu 0>; 871 sustainable-power = <717>; 872 873 cooling-maps { 874 map0 { 875 trip = <&target>; 876 cooling-device = <&cpu0 0 2>; 877 contribution = <1024>; 878 }; 879 }; 880 881 trips { 882 sensor_crit: sensor-crit { 883 temperature = <125000>; 884 hysteresis = <1000>; 885 type = "critical"; 886 }; 887 888 target: trip-point { 889 temperature = <100000>; 890 hysteresis = <1000>; 891 type = "passive"; 892 }; 893 }; 894 }; 895 }; 896 897 timer { 898 compatible = "arm,armv8-timer"; 899 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 900 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 901 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 902 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 903 }; 904}; 905