1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the ebisu board 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8/dts-v1/; 9#include "r8a77990.dtsi" 10#include <dt-bindings/gpio/gpio.h> 11 12/ { 13 model = "Renesas Ebisu board based on r8a77990"; 14 compatible = "renesas,ebisu", "renesas,r8a77990"; 15 16 aliases { 17 serial0 = &scif2; 18 ethernet0 = &avb; 19 mmc0 = &sdhi3; 20 mmc1 = &sdhi0; 21 mmc2 = &sdhi1; 22 }; 23 24 chosen { 25 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 26 stdout-path = "serial0:115200n8"; 27 }; 28 29 audio_clkout: audio-clkout { 30 /* 31 * This is same as <&rcar_sound 0> 32 * but needed to avoid cs2000/rcar_sound probe dead-lock 33 */ 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <11289600>; 37 }; 38 39 backlight: backlight { 40 compatible = "pwm-backlight"; 41 pwms = <&pwm3 0 50000>; 42 43 brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>; 44 default-brightness-level = <10>; 45 46 power-supply = <®_12p0v>; 47 }; 48 49 cvbs-in { 50 compatible = "composite-video-connector"; 51 label = "CVBS IN"; 52 53 port { 54 cvbs_con: endpoint { 55 remote-endpoint = <&adv7482_ain7>; 56 }; 57 }; 58 }; 59 60 hdmi-in { 61 compatible = "hdmi-connector"; 62 label = "HDMI IN"; 63 type = "a"; 64 65 port { 66 hdmi_in_con: endpoint { 67 remote-endpoint = <&adv7482_hdmi>; 68 }; 69 }; 70 }; 71 72 hdmi-out { 73 compatible = "hdmi-connector"; 74 type = "a"; 75 76 port { 77 hdmi_con_out: endpoint { 78 remote-endpoint = <&adv7511_out>; 79 }; 80 }; 81 }; 82 83 lvds-decoder { 84 compatible = "thine,thc63lvd1024"; 85 vcc-supply = <®_3p3v>; 86 87 ports { 88 #address-cells = <1>; 89 #size-cells = <0>; 90 91 port@0 { 92 reg = <0>; 93 thc63lvd1024_in: endpoint { 94 remote-endpoint = <&lvds0_out>; 95 }; 96 }; 97 98 port@2 { 99 reg = <2>; 100 thc63lvd1024_out: endpoint { 101 remote-endpoint = <&adv7511_in>; 102 }; 103 }; 104 }; 105 }; 106 107 memory@48000000 { 108 device_type = "memory"; 109 /* first 128MB is reserved for secure area. */ 110 reg = <0x0 0x48000000 0x0 0x38000000>; 111 }; 112 113 reg_1p8v: regulator0 { 114 compatible = "regulator-fixed"; 115 regulator-name = "fixed-1.8V"; 116 regulator-min-microvolt = <1800000>; 117 regulator-max-microvolt = <1800000>; 118 regulator-boot-on; 119 regulator-always-on; 120 }; 121 122 reg_3p3v: regulator1 { 123 compatible = "regulator-fixed"; 124 regulator-name = "fixed-3.3V"; 125 regulator-min-microvolt = <3300000>; 126 regulator-max-microvolt = <3300000>; 127 regulator-boot-on; 128 regulator-always-on; 129 }; 130 131 reg_12p0v: regulator2 { 132 compatible = "regulator-fixed"; 133 regulator-name = "D12.0V"; 134 regulator-min-microvolt = <12000000>; 135 regulator-max-microvolt = <12000000>; 136 regulator-boot-on; 137 regulator-always-on; 138 }; 139 140 rsnd_ak4613: sound { 141 compatible = "simple-audio-card"; 142 143 simple-audio-card,name = "rsnd-ak4613"; 144 simple-audio-card,format = "left_j"; 145 simple-audio-card,bitclock-master = <&sndcpu>; 146 simple-audio-card,frame-master = <&sndcpu>; 147 148 sndcodec: simple-audio-card,codec { 149 sound-dai = <&ak4613>; 150 }; 151 152 sndcpu: simple-audio-card,cpu { 153 sound-dai = <&rcar_sound>; 154 }; 155 }; 156 157 vbus0_usb2: regulator-vbus0-usb2 { 158 compatible = "regulator-fixed"; 159 160 regulator-name = "USB20_VBUS_CN"; 161 regulator-min-microvolt = <5000000>; 162 regulator-max-microvolt = <5000000>; 163 164 gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>; 165 enable-active-high; 166 }; 167 168 vcc_sdhi0: regulator-vcc-sdhi0 { 169 compatible = "regulator-fixed"; 170 171 regulator-name = "SDHI0 Vcc"; 172 regulator-min-microvolt = <3300000>; 173 regulator-max-microvolt = <3300000>; 174 175 gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; 176 enable-active-high; 177 }; 178 179 vccq_sdhi0: regulator-vccq-sdhi0 { 180 compatible = "regulator-gpio"; 181 182 regulator-name = "SDHI0 VccQ"; 183 regulator-min-microvolt = <1800000>; 184 regulator-max-microvolt = <3300000>; 185 186 gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; 187 gpios-states = <1>; 188 states = <3300000 1>, <1800000 0>; 189 }; 190 191 vcc_sdhi1: regulator-vcc-sdhi1 { 192 compatible = "regulator-fixed"; 193 194 regulator-name = "SDHI1 Vcc"; 195 regulator-min-microvolt = <3300000>; 196 regulator-max-microvolt = <3300000>; 197 198 gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; 199 enable-active-high; 200 }; 201 202 vccq_sdhi1: regulator-vccq-sdhi1 { 203 compatible = "regulator-gpio"; 204 205 regulator-name = "SDHI1 VccQ"; 206 regulator-min-microvolt = <1800000>; 207 regulator-max-microvolt = <3300000>; 208 209 gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; 210 gpios-states = <1>; 211 states = <3300000 1>, <1800000 0>; 212 }; 213 214 vga { 215 compatible = "vga-connector"; 216 217 port { 218 vga_in: endpoint { 219 remote-endpoint = <&adv7123_out>; 220 }; 221 }; 222 }; 223 224 vga-encoder { 225 compatible = "adi,adv7123"; 226 227 ports { 228 #address-cells = <1>; 229 #size-cells = <0>; 230 231 port@0 { 232 reg = <0>; 233 adv7123_in: endpoint { 234 remote-endpoint = <&du_out_rgb>; 235 }; 236 }; 237 port@1 { 238 reg = <1>; 239 adv7123_out: endpoint { 240 remote-endpoint = <&vga_in>; 241 }; 242 }; 243 }; 244 }; 245 246 x12_clk: x12 { 247 compatible = "fixed-clock"; 248 #clock-cells = <0>; 249 clock-frequency = <24576000>; 250 }; 251 252 x13_clk: x13 { 253 compatible = "fixed-clock"; 254 #clock-cells = <0>; 255 clock-frequency = <74250000>; 256 }; 257}; 258 259&audio_clk_a { 260 clock-frequency = <22579200>; 261}; 262 263&avb { 264 pinctrl-0 = <&avb_pins>; 265 pinctrl-names = "default"; 266 phy-handle = <&phy0>; 267 status = "okay"; 268 269 phy0: ethernet-phy@0 { 270 rxc-skew-ps = <1500>; 271 reg = <0>; 272 interrupt-parent = <&gpio2>; 273 interrupts = <21 IRQ_TYPE_LEVEL_LOW>; 274 reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; 275 /* 276 * TX clock internal delay mode is required for reliable 277 * 1Gbps communication using the KSZ9031RNX phy present on 278 * the Ebisu board, however, TX clock internal delay mode 279 * isn't supported on r8a77990. Thus, limit speed to 280 * 100Mbps for reliable communication. 281 */ 282 max-speed = <100>; 283 }; 284}; 285 286&canfd { 287 pinctrl-0 = <&canfd0_pins>; 288 pinctrl-names = "default"; 289 status = "okay"; 290 291 channel0 { 292 status = "okay"; 293 }; 294}; 295 296&csi40 { 297 status = "okay"; 298 299 ports { 300 port@0 { 301 csi40_in: endpoint { 302 clock-lanes = <0>; 303 data-lanes = <1 2>; 304 remote-endpoint = <&adv7482_txa>; 305 }; 306 }; 307 }; 308}; 309 310&du { 311 pinctrl-0 = <&du_pins>; 312 pinctrl-names = "default"; 313 status = "okay"; 314 315 clocks = <&cpg CPG_MOD 724>, 316 <&cpg CPG_MOD 723>, 317 <&x13_clk>; 318 clock-names = "du.0", "du.1", "dclkin.0"; 319 320 ports { 321 port@0 { 322 endpoint { 323 remote-endpoint = <&adv7123_in>; 324 }; 325 }; 326 }; 327}; 328 329&ehci0 { 330 dr_mode = "otg"; 331 status = "okay"; 332}; 333 334&extal_clk { 335 clock-frequency = <48000000>; 336}; 337 338&hsusb { 339 dr_mode = "otg"; 340 status = "okay"; 341}; 342 343&i2c0 { 344 status = "okay"; 345 346 io_expander: gpio@20 { 347 compatible = "onnn,pca9654"; 348 reg = <0x20>; 349 gpio-controller; 350 #gpio-cells = <2>; 351 interrupt-parent = <&gpio2>; 352 interrupts = <22 IRQ_TYPE_LEVEL_LOW>; 353 }; 354 355 hdmi-encoder@39 { 356 compatible = "adi,adv7511w"; 357 reg = <0x39>; 358 interrupt-parent = <&gpio1>; 359 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 360 361 adi,input-depth = <8>; 362 adi,input-colorspace = "rgb"; 363 adi,input-clock = "1x"; 364 365 ports { 366 #address-cells = <1>; 367 #size-cells = <0>; 368 369 port@0 { 370 reg = <0>; 371 adv7511_in: endpoint { 372 remote-endpoint = <&thc63lvd1024_out>; 373 }; 374 }; 375 376 port@1 { 377 reg = <1>; 378 adv7511_out: endpoint { 379 remote-endpoint = <&hdmi_con_out>; 380 }; 381 }; 382 }; 383 }; 384 385 video-receiver@70 { 386 compatible = "adi,adv7482"; 387 reg = <0x70>; 388 389 #address-cells = <1>; 390 #size-cells = <0>; 391 392 interrupt-parent = <&gpio0>; 393 interrupt-names = "intrq1", "intrq2"; 394 interrupts = <7 IRQ_TYPE_LEVEL_LOW>, 395 <17 IRQ_TYPE_LEVEL_LOW>; 396 397 port@7 { 398 reg = <7>; 399 400 adv7482_ain7: endpoint { 401 remote-endpoint = <&cvbs_con>; 402 }; 403 }; 404 405 port@8 { 406 reg = <8>; 407 408 adv7482_hdmi: endpoint { 409 remote-endpoint = <&hdmi_in_con>; 410 }; 411 }; 412 413 port@a { 414 reg = <10>; 415 416 adv7482_txa: endpoint { 417 clock-lanes = <0>; 418 data-lanes = <1 2>; 419 remote-endpoint = <&csi40_in>; 420 }; 421 }; 422 }; 423}; 424 425&i2c3 { 426 status = "okay"; 427 428 ak4613: codec@10 { 429 compatible = "asahi-kasei,ak4613"; 430 #sound-dai-cells = <0>; 431 reg = <0x10>; 432 clocks = <&rcar_sound 3>; 433 434 asahi-kasei,in1-single-end; 435 asahi-kasei,in2-single-end; 436 asahi-kasei,out1-single-end; 437 asahi-kasei,out2-single-end; 438 asahi-kasei,out3-single-end; 439 asahi-kasei,out4-single-end; 440 asahi-kasei,out5-single-end; 441 asahi-kasei,out6-single-end; 442 }; 443 444 cs2000: clk-multiplier@4f { 445 #clock-cells = <0>; 446 compatible = "cirrus,cs2000-cp"; 447 reg = <0x4f>; 448 clocks = <&audio_clkout>, <&x12_clk>; 449 clock-names = "clk_in", "ref_clk"; 450 451 assigned-clocks = <&cs2000>; 452 assigned-clock-rates = <24576000>; /* 1/1 divide */ 453 }; 454}; 455 456&i2c_dvfs { 457 status = "okay"; 458 459 clock-frequency = <400000>; 460 461 pmic: pmic@30 { 462 pinctrl-0 = <&irq0_pins>; 463 pinctrl-names = "default"; 464 465 compatible = "rohm,bd9571mwv"; 466 reg = <0x30>; 467 interrupt-parent = <&intc_ex>; 468 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 469 interrupt-controller; 470 #interrupt-cells = <2>; 471 gpio-controller; 472 #gpio-cells = <2>; 473 rohm,ddr-backup-power = <0x1>; 474 rohm,rstbmode-level; 475 }; 476}; 477 478&lvds0 { 479 status = "okay"; 480 481 clocks = <&cpg CPG_MOD 727>, 482 <&x13_clk>, 483 <&extal_clk>; 484 clock-names = "fck", "dclkin.0", "extal"; 485 486 ports { 487 port@1 { 488 lvds0_out: endpoint { 489 remote-endpoint = <&thc63lvd1024_in>; 490 }; 491 }; 492 }; 493}; 494 495&lvds1 { 496 /* 497 * Even though the LVDS1 output is not connected, the encoder must be 498 * enabled to supply a pixel clock to the DU for the DPAD output when 499 * LVDS0 is in use. 500 */ 501 status = "okay"; 502 503 clocks = <&cpg CPG_MOD 727>, 504 <&x13_clk>, 505 <&extal_clk>; 506 clock-names = "fck", "dclkin.0", "extal"; 507}; 508 509&ohci0 { 510 dr_mode = "otg"; 511 status = "okay"; 512}; 513 514&pcie_bus_clk { 515 clock-frequency = <100000000>; 516}; 517 518&pciec0 { 519 status = "okay"; 520}; 521 522&pfc { 523 avb_pins: avb { 524 groups = "avb_link", "avb_mii"; 525 function = "avb"; 526 }; 527 528 canfd0_pins: canfd0 { 529 groups = "canfd0_data"; 530 function = "canfd0"; 531 }; 532 533 du_pins: du { 534 groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; 535 function = "du"; 536 }; 537 538 irq0_pins: irq0 { 539 groups = "intc_ex_irq0"; 540 function = "intc_ex"; 541 }; 542 543 pwm3_pins: pwm3 { 544 groups = "pwm3_b"; 545 function = "pwm3"; 546 }; 547 548 pwm5_pins: pwm5 { 549 groups = "pwm5_a"; 550 function = "pwm5"; 551 }; 552 553 scif2_pins: scif2 { 554 groups = "scif2_data_a"; 555 function = "scif2"; 556 }; 557 558 sdhi0_pins: sd0 { 559 groups = "sdhi0_data4", "sdhi0_ctrl"; 560 function = "sdhi0"; 561 power-source = <3300>; 562 }; 563 564 sdhi0_pins_uhs: sd0_uhs { 565 groups = "sdhi0_data4", "sdhi0_ctrl"; 566 function = "sdhi0"; 567 power-source = <1800>; 568 }; 569 570 sdhi1_pins: sd1 { 571 groups = "sdhi1_data4", "sdhi1_ctrl"; 572 function = "sdhi1"; 573 power-source = <3300>; 574 }; 575 576 sdhi1_pins_uhs: sd1_uhs { 577 groups = "sdhi1_data4", "sdhi1_ctrl"; 578 function = "sdhi1"; 579 power-source = <1800>; 580 }; 581 582 sdhi3_pins: sd3 { 583 groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; 584 function = "sdhi3"; 585 power-source = <1800>; 586 }; 587 588 sound_clk_pins: sound_clk { 589 groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a", 590 "audio_clkout_a", "audio_clkout1_a"; 591 function = "audio_clk"; 592 }; 593 594 sound_pins: sound { 595 groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data"; 596 function = "ssi"; 597 }; 598 599 usb0_pins: usb { 600 groups = "usb0_b", "usb0_id"; 601 function = "usb0"; 602 }; 603 604 usb30_pins: usb30 { 605 groups = "usb30"; 606 function = "usb30"; 607 }; 608}; 609 610&pwm3 { 611 pinctrl-0 = <&pwm3_pins>; 612 pinctrl-names = "default"; 613 614 status = "okay"; 615}; 616 617&pwm5 { 618 pinctrl-0 = <&pwm5_pins>; 619 pinctrl-names = "default"; 620 621 status = "okay"; 622}; 623 624&rcar_sound { 625 pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; 626 pinctrl-names = "default"; 627 628 /* Single DAI */ 629 #sound-dai-cells = <0>; 630 631 /* audio_clkout0/1/2/3 */ 632 #clock-cells = <1>; 633 clock-frequency = <12288000 11289600>; 634 635 status = "okay"; 636 637 /* update <audio_clk_b> to <cs2000> */ 638 clocks = <&cpg CPG_MOD 1005>, 639 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 640 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 641 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 642 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 643 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 644 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 645 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 646 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 647 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 648 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 649 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 650 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 651 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 652 <&audio_clk_a>, <&cs2000>, <&audio_clk_c>, 653 <&cpg CPG_CORE R8A77990_CLK_ZA2>; 654 655 rcar_sound,dai { 656 dai0 { 657 playback = <&ssi0>, <&src0>, <&dvc0>; 658 capture = <&ssi1>, <&src1>, <&dvc1>; 659 }; 660 }; 661 662}; 663 664&rwdt { 665 timeout-sec = <60>; 666 status = "okay"; 667}; 668 669&scif2 { 670 pinctrl-0 = <&scif2_pins>; 671 pinctrl-names = "default"; 672 673 status = "okay"; 674}; 675 676&sdhi0 { 677 pinctrl-0 = <&sdhi0_pins>; 678 pinctrl-1 = <&sdhi0_pins_uhs>; 679 pinctrl-names = "default", "state_uhs"; 680 681 vmmc-supply = <&vcc_sdhi0>; 682 vqmmc-supply = <&vccq_sdhi0>; 683 cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; 684 wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; 685 bus-width = <4>; 686 sd-uhs-sdr50; 687 sd-uhs-sdr104; 688 status = "okay"; 689}; 690 691&sdhi1 { 692 pinctrl-0 = <&sdhi1_pins>; 693 pinctrl-1 = <&sdhi1_pins_uhs>; 694 pinctrl-names = "default", "state_uhs"; 695 696 vmmc-supply = <&vcc_sdhi1>; 697 vqmmc-supply = <&vccq_sdhi1>; 698 cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>; 699 bus-width = <4>; 700 sd-uhs-sdr50; 701 sd-uhs-sdr104; 702 status = "okay"; 703}; 704 705&sdhi3 { 706 /* used for on-board 8bit eMMC */ 707 pinctrl-0 = <&sdhi3_pins>; 708 pinctrl-1 = <&sdhi3_pins>; 709 pinctrl-names = "default", "state_uhs"; 710 711 vmmc-supply = <®_3p3v>; 712 vqmmc-supply = <®_1p8v>; 713 mmc-hs200-1_8v; 714 mmc-hs400-1_8v; 715 bus-width = <8>; 716 no-sd; 717 no-sdio; 718 non-removable; 719 full-pwr-cycle-in-suspend; 720 status = "okay"; 721}; 722 723&ssi1 { 724 shared-pin; 725}; 726 727&usb2_phy0 { 728 pinctrl-0 = <&usb0_pins>; 729 pinctrl-names = "default"; 730 731 vbus-supply = <&vbus0_usb2>; 732 status = "okay"; 733}; 734 735&usb3_peri0 { 736 companion = <&xhci0>; 737 status = "okay"; 738}; 739 740&vin4 { 741 status = "okay"; 742}; 743 744&vin5 { 745 status = "okay"; 746}; 747 748&xhci0 { 749 pinctrl-0 = <&usb30_pins>; 750 pinctrl-names = "default"; 751 752 status = "okay"; 753}; 754