1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the V3M Starter Kit board 4 * 5 * Copyright (C) 2017 Renesas Electronics Corp. 6 * Copyright (C) 2017 Cogent Embedded, Inc. 7 */ 8 9/dts-v1/; 10#include "r8a77970.dtsi" 11 12/ { 13 model = "Renesas V3M Starter Kit board"; 14 compatible = "renesas,v3msk", "renesas,r8a77970"; 15 16 aliases { 17 serial0 = &scif0; 18 }; 19 20 chosen { 21 stdout-path = "serial0:115200n8"; 22 }; 23 24 hdmi-out { 25 compatible = "hdmi-connector"; 26 type = "a"; 27 28 port { 29 hdmi_con: endpoint { 30 remote-endpoint = <&adv7511_out>; 31 }; 32 }; 33 }; 34 35 lvds-decoder { 36 compatible = "thine,thc63lvd1024"; 37 vcc-supply = <&vcc_d3_3v>; 38 39 ports { 40 #address-cells = <1>; 41 #size-cells = <0>; 42 43 port@0 { 44 reg = <0>; 45 thc63lvd1024_in: endpoint { 46 remote-endpoint = <&lvds0_out>; 47 }; 48 }; 49 50 port@2 { 51 reg = <2>; 52 thc63lvd1024_out: endpoint { 53 remote-endpoint = <&adv7511_in>; 54 }; 55 }; 56 }; 57 }; 58 59 memory@48000000 { 60 device_type = "memory"; 61 /* first 128MB is reserved for secure area. */ 62 reg = <0x0 0x48000000 0x0 0x38000000>; 63 }; 64 65 osc5_clk: osc5-clock { 66 compatible = "fixed-clock"; 67 #clock-cells = <0>; 68 clock-frequency = <148500000>; 69 }; 70 71 vcc_d1_8v: regulator-0 { 72 compatible = "regulator-fixed"; 73 regulator-name = "VCC_D1.8V"; 74 regulator-min-microvolt = <1800000>; 75 regulator-max-microvolt = <1800000>; 76 regulator-boot-on; 77 regulator-always-on; 78 }; 79 80 vcc_d3_3v: regulator-1 { 81 compatible = "regulator-fixed"; 82 regulator-name = "VCC_D3.3V"; 83 regulator-min-microvolt = <3300000>; 84 regulator-max-microvolt = <3300000>; 85 regulator-boot-on; 86 regulator-always-on; 87 }; 88 89 vcc_vddq_vin0: regulator-2 { 90 compatible = "regulator-fixed"; 91 regulator-name = "VCC_VDDQ_VIN0"; 92 regulator-min-microvolt = <3300000>; 93 regulator-max-microvolt = <3300000>; 94 regulator-boot-on; 95 regulator-always-on; 96 }; 97}; 98 99&avb { 100 pinctrl-0 = <&avb_pins>; 101 pinctrl-names = "default"; 102 103 renesas,no-ether-link; 104 phy-handle = <&phy0>; 105 phy-mode = "rgmii-id"; 106 status = "okay"; 107 108 phy0: ethernet-phy@0 { 109 rxc-skew-ps = <1500>; 110 reg = <0>; 111 interrupt-parent = <&gpio1>; 112 interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 113 }; 114}; 115 116&du { 117 clocks = <&cpg CPG_MOD 724>, 118 <&osc5_clk>; 119 clock-names = "du.0", "dclkin.0"; 120 status = "okay"; 121}; 122 123&extal_clk { 124 clock-frequency = <16666666>; 125}; 126 127&extalr_clk { 128 clock-frequency = <32768>; 129}; 130 131&i2c0 { 132 pinctrl-0 = <&i2c0_pins>; 133 pinctrl-names = "default"; 134 135 status = "okay"; 136 clock-frequency = <400000>; 137 138 hdmi@39{ 139 compatible = "adi,adv7511w"; 140 #sound-dai-cells = <0>; 141 reg = <0x39>; 142 interrupt-parent = <&gpio1>; 143 interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 144 avdd-supply = <&vcc_d1_8v>; 145 dvdd-supply = <&vcc_d1_8v>; 146 pvdd-supply = <&vcc_d1_8v>; 147 bgvdd-supply = <&vcc_d1_8v>; 148 dvdd-3v-supply = <&vcc_d3_3v>; 149 150 adi,input-depth = <8>; 151 adi,input-colorspace = "rgb"; 152 adi,input-clock = "1x"; 153 154 ports { 155 #address-cells = <1>; 156 #size-cells = <0>; 157 158 port@0 { 159 reg = <0>; 160 adv7511_in: endpoint { 161 remote-endpoint = <&thc63lvd1024_out>; 162 }; 163 }; 164 165 port@1 { 166 reg = <1>; 167 adv7511_out: endpoint { 168 remote-endpoint = <&hdmi_con>; 169 }; 170 }; 171 }; 172 }; 173}; 174 175&lvds0 { 176 status = "okay"; 177 178 ports { 179 port@1 { 180 lvds0_out: endpoint { 181 remote-endpoint = <&thc63lvd1024_in>; 182 }; 183 }; 184 }; 185}; 186 187&mmc0 { 188 pinctrl-0 = <&mmc_pins>; 189 pinctrl-names = "default"; 190 191 vmmc-supply = <&vcc_d3_3v>; 192 vqmmc-supply = <&vcc_vddq_vin0>; 193 bus-width = <8>; 194 non-removable; 195 status = "okay"; 196}; 197 198&pfc { 199 avb_pins: avb0 { 200 groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; 201 function = "avb0"; 202 }; 203 204 i2c0_pins: i2c0 { 205 groups = "i2c0"; 206 function = "i2c0"; 207 }; 208 209 mmc_pins: mmc_3_3v { 210 groups = "mmc_data8", "mmc_ctrl"; 211 function = "mmc"; 212 power-source = <3300>; 213 }; 214 215 qspi0_pins: qspi0 { 216 groups = "qspi0_ctrl", "qspi0_data4"; 217 function = "qspi0"; 218 }; 219 220 scif0_pins: scif0 { 221 groups = "scif0_data"; 222 function = "scif0"; 223 }; 224}; 225 226&rpc { 227 pinctrl-0 = <&qspi0_pins>; 228 pinctrl-names = "default"; 229 230 status = "okay"; 231 232 flash@0 { 233 compatible = "spansion,s25fs512s", "jedec,spi-nor"; 234 reg = <0>; 235 spi-max-frequency = <50000000>; 236 spi-rx-bus-width = <4>; 237 238 partitions { 239 compatible = "fixed-partitions"; 240 #address-cells = <1>; 241 #size-cells = <1>; 242 243 bootparam@0 { 244 reg = <0x00000000 0x040000>; 245 read-only; 246 }; 247 cr7@40000 { 248 reg = <0x00040000 0x080000>; 249 read-only; 250 }; 251 cert_header_sa3@c0000 { 252 reg = <0x000c0000 0x080000>; 253 read-only; 254 }; 255 bl2@140000 { 256 reg = <0x00140000 0x040000>; 257 read-only; 258 }; 259 cert_header_sa6@180000 { 260 reg = <0x00180000 0x040000>; 261 read-only; 262 }; 263 bl31@1c0000 { 264 reg = <0x001c0000 0x460000>; 265 read-only; 266 }; 267 uboot@640000 { 268 reg = <0x00640000 0x0c0000>; 269 read-only; 270 }; 271 uboot-env@700000 { 272 reg = <0x00700000 0x040000>; 273 read-only; 274 }; 275 dtb@740000 { 276 reg = <0x00740000 0x080000>; 277 }; 278 kernel@7c0000 { 279 reg = <0x007c0000 0x1400000>; 280 }; 281 user@1bc0000 { 282 reg = <0x01bc0000 0x2440000>; 283 }; 284 }; 285 }; 286}; 287 288&scif0 { 289 pinctrl-0 = <&scif0_pins>; 290 pinctrl-names = "default"; 291 292 status = "okay"; 293}; 294