1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the V3M Starter Kit board 4 * 5 * Copyright (C) 2017 Renesas Electronics Corp. 6 * Copyright (C) 2017 Cogent Embedded, Inc. 7 */ 8 9/dts-v1/; 10#include "r8a77970.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12 13/ { 14 model = "Renesas V3M Starter Kit board"; 15 compatible = "renesas,v3msk", "renesas,r8a77970"; 16 17 aliases { 18 i2c0 = &i2c0; 19 i2c1 = &i2c1; 20 i2c2 = &i2c2; 21 i2c3 = &i2c3; 22 i2c4 = &i2c4; 23 serial0 = &scif0; 24 }; 25 26 chosen { 27 stdout-path = "serial0:115200n8"; 28 }; 29 30 hdmi-out { 31 compatible = "hdmi-connector"; 32 type = "a"; 33 34 port { 35 hdmi_con: endpoint { 36 remote-endpoint = <&adv7511_out>; 37 }; 38 }; 39 }; 40 41 lvds-decoder { 42 compatible = "thine,thc63lvd1024"; 43 vcc-supply = <&vcc_d3_3v>; 44 45 ports { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 49 port@0 { 50 reg = <0>; 51 thc63lvd1024_in: endpoint { 52 remote-endpoint = <&lvds0_out>; 53 }; 54 }; 55 56 port@2 { 57 reg = <2>; 58 thc63lvd1024_out: endpoint { 59 remote-endpoint = <&adv7511_in>; 60 }; 61 }; 62 }; 63 }; 64 65 memory@48000000 { 66 device_type = "memory"; 67 /* first 128MB is reserved for secure area. */ 68 reg = <0x0 0x48000000 0x0 0x78000000>; 69 }; 70 71 osc5_clk: osc5-clock { 72 compatible = "fixed-clock"; 73 #clock-cells = <0>; 74 clock-frequency = <148500000>; 75 }; 76 77 vcc_d1_8v: regulator-0 { 78 compatible = "regulator-fixed"; 79 regulator-name = "VCC_D1.8V"; 80 regulator-min-microvolt = <1800000>; 81 regulator-max-microvolt = <1800000>; 82 regulator-boot-on; 83 regulator-always-on; 84 }; 85 86 vcc_d3_3v: regulator-1 { 87 compatible = "regulator-fixed"; 88 regulator-name = "VCC_D3.3V"; 89 regulator-min-microvolt = <3300000>; 90 regulator-max-microvolt = <3300000>; 91 regulator-boot-on; 92 regulator-always-on; 93 }; 94 95 vcc_vddq_vin0: regulator-2 { 96 compatible = "regulator-fixed"; 97 regulator-name = "VCC_VDDQ_VIN0"; 98 regulator-min-microvolt = <3300000>; 99 regulator-max-microvolt = <3300000>; 100 regulator-boot-on; 101 regulator-always-on; 102 }; 103}; 104 105&avb { 106 pinctrl-0 = <&avb_pins>; 107 pinctrl-names = "default"; 108 109 renesas,no-ether-link; 110 phy-handle = <&phy0>; 111 rx-internal-delay-ps = <1800>; 112 tx-internal-delay-ps = <2000>; 113 status = "okay"; 114 115 phy0: ethernet-phy@0 { 116 compatible = "ethernet-phy-id0022.1622", 117 "ethernet-phy-ieee802.3-c22"; 118 rxc-skew-ps = <1500>; 119 reg = <0>; 120 interrupt-parent = <&gpio1>; 121 interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 122 reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; 123 }; 124}; 125 126&du { 127 clocks = <&cpg CPG_MOD 724>, 128 <&osc5_clk>; 129 clock-names = "du.0", "dclkin.0"; 130 status = "okay"; 131}; 132 133&extal_clk { 134 clock-frequency = <16666666>; 135}; 136 137&extalr_clk { 138 clock-frequency = <32768>; 139}; 140 141&i2c0 { 142 pinctrl-0 = <&i2c0_pins>; 143 pinctrl-names = "default"; 144 145 status = "okay"; 146 clock-frequency = <400000>; 147 148 hdmi@39 { 149 compatible = "adi,adv7511w"; 150 #sound-dai-cells = <0>; 151 reg = <0x39>; 152 interrupt-parent = <&gpio1>; 153 interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 154 avdd-supply = <&vcc_d1_8v>; 155 dvdd-supply = <&vcc_d1_8v>; 156 pvdd-supply = <&vcc_d1_8v>; 157 bgvdd-supply = <&vcc_d1_8v>; 158 dvdd-3v-supply = <&vcc_d3_3v>; 159 160 adi,input-depth = <8>; 161 adi,input-colorspace = "rgb"; 162 adi,input-clock = "1x"; 163 164 ports { 165 #address-cells = <1>; 166 #size-cells = <0>; 167 168 port@0 { 169 reg = <0>; 170 adv7511_in: endpoint { 171 remote-endpoint = <&thc63lvd1024_out>; 172 }; 173 }; 174 175 port@1 { 176 reg = <1>; 177 adv7511_out: endpoint { 178 remote-endpoint = <&hdmi_con>; 179 }; 180 }; 181 }; 182 }; 183}; 184 185&lvds0 { 186 status = "okay"; 187 188 ports { 189 port@1 { 190 lvds0_out: endpoint { 191 remote-endpoint = <&thc63lvd1024_in>; 192 }; 193 }; 194 }; 195}; 196 197&mmc0 { 198 pinctrl-0 = <&mmc_pins>; 199 pinctrl-names = "default"; 200 201 vmmc-supply = <&vcc_d3_3v>; 202 vqmmc-supply = <&vcc_vddq_vin0>; 203 bus-width = <8>; 204 non-removable; 205 status = "okay"; 206}; 207 208&pfc { 209 avb_pins: avb0 { 210 groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; 211 function = "avb0"; 212 }; 213 214 i2c0_pins: i2c0 { 215 groups = "i2c0"; 216 function = "i2c0"; 217 }; 218 219 mmc_pins: mmc_3_3v { 220 groups = "mmc_data8", "mmc_ctrl"; 221 function = "mmc"; 222 power-source = <3300>; 223 }; 224 225 qspi0_pins: qspi0 { 226 groups = "qspi0_ctrl", "qspi0_data4"; 227 function = "qspi0"; 228 }; 229 230 scif0_pins: scif0 { 231 groups = "scif0_data"; 232 function = "scif0"; 233 }; 234}; 235 236&rpc { 237 pinctrl-0 = <&qspi0_pins>; 238 pinctrl-names = "default"; 239 240 status = "okay"; 241 242 flash@0 { 243 compatible = "spansion,s25fs512s", "jedec,spi-nor"; 244 reg = <0>; 245 spi-max-frequency = <50000000>; 246 spi-rx-bus-width = <4>; 247 248 partitions { 249 compatible = "fixed-partitions"; 250 #address-cells = <1>; 251 #size-cells = <1>; 252 253 bootparam@0 { 254 reg = <0x00000000 0x040000>; 255 read-only; 256 }; 257 cr7@40000 { 258 reg = <0x00040000 0x080000>; 259 read-only; 260 }; 261 cert_header_sa3@c0000 { 262 reg = <0x000c0000 0x080000>; 263 read-only; 264 }; 265 bl2@140000 { 266 reg = <0x00140000 0x040000>; 267 read-only; 268 }; 269 cert_header_sa6@180000 { 270 reg = <0x00180000 0x040000>; 271 read-only; 272 }; 273 bl31@1c0000 { 274 reg = <0x001c0000 0x460000>; 275 read-only; 276 }; 277 uboot@640000 { 278 reg = <0x00640000 0x0c0000>; 279 read-only; 280 }; 281 uboot-env@700000 { 282 reg = <0x00700000 0x040000>; 283 read-only; 284 }; 285 dtb@740000 { 286 reg = <0x00740000 0x080000>; 287 }; 288 kernel@7c0000 { 289 reg = <0x007c0000 0x1400000>; 290 }; 291 user@1bc0000 { 292 reg = <0x01bc0000 0x2440000>; 293 }; 294 }; 295 }; 296}; 297 298&scif0 { 299 pinctrl-0 = <&scif0_pins>; 300 pinctrl-names = "default"; 301 302 status = "okay"; 303}; 304