1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the Eagle board with R-Car V3M 4 * 5 * Copyright (C) 2016-2017 Renesas Electronics Corp. 6 * Copyright (C) 2017 Cogent Embedded, Inc. 7 */ 8 9/dts-v1/; 10#include "r8a77970.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12 13/ { 14 model = "Renesas Eagle board based on r8a77970"; 15 compatible = "renesas,eagle", "renesas,r8a77970"; 16 17 aliases { 18 serial0 = &scif0; 19 ethernet0 = &avb; 20 }; 21 22 chosen { 23 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 24 stdout-path = "serial0:115200n8"; 25 }; 26 27 d3p3: regulator-fixed { 28 compatible = "regulator-fixed"; 29 regulator-name = "fixed-3.3V"; 30 regulator-min-microvolt = <3300000>; 31 regulator-max-microvolt = <3300000>; 32 regulator-boot-on; 33 regulator-always-on; 34 }; 35 36 hdmi-out { 37 compatible = "hdmi-connector"; 38 type = "a"; 39 40 port { 41 hdmi_con_out: endpoint { 42 remote-endpoint = <&adv7511_out>; 43 }; 44 }; 45 }; 46 47 lvds-decoder { 48 compatible = "thine,thc63lvd1024"; 49 50 vcc-supply = <&d3p3>; 51 52 ports { 53 #address-cells = <1>; 54 #size-cells = <0>; 55 56 port@0 { 57 reg = <0>; 58 thc63lvd1024_in: endpoint { 59 remote-endpoint = <&lvds0_out>; 60 }; 61 }; 62 63 port@2 { 64 reg = <2>; 65 thc63lvd1024_out: endpoint { 66 remote-endpoint = <&adv7511_in>; 67 }; 68 }; 69 }; 70 }; 71 72 memory@48000000 { 73 device_type = "memory"; 74 /* first 128MB is reserved for secure area. */ 75 reg = <0x0 0x48000000 0x0 0x38000000>; 76 }; 77 78 x1_clk: x1-clock { 79 compatible = "fixed-clock"; 80 #clock-cells = <0>; 81 clock-frequency = <148500000>; 82 }; 83}; 84 85&avb { 86 pinctrl-0 = <&avb_pins>; 87 pinctrl-names = "default"; 88 89 renesas,no-ether-link; 90 phy-handle = <&phy0>; 91 rx-internal-delay-ps = <1800>; 92 tx-internal-delay-ps = <2000>; 93 status = "okay"; 94 95 phy0: ethernet-phy@0 { 96 compatible = "ethernet-phy-id0022.1622", 97 "ethernet-phy-ieee802.3-c22"; 98 rxc-skew-ps = <1500>; 99 reg = <0>; 100 interrupt-parent = <&gpio1>; 101 interrupts = <17 IRQ_TYPE_LEVEL_LOW>; 102 reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; 103 }; 104}; 105 106&canfd { 107 pinctrl-0 = <&canfd0_pins>; 108 pinctrl-names = "default"; 109 status = "okay"; 110 111 channel0 { 112 status = "okay"; 113 }; 114}; 115 116&du { 117 clocks = <&cpg CPG_MOD 724>, <&x1_clk>; 118 clock-names = "du.0", "dclkin.0"; 119 status = "okay"; 120}; 121 122&extal_clk { 123 clock-frequency = <16666666>; 124}; 125 126&extalr_clk { 127 clock-frequency = <32768>; 128}; 129 130&i2c0 { 131 pinctrl-0 = <&i2c0_pins>; 132 pinctrl-names = "default"; 133 134 status = "okay"; 135 clock-frequency = <400000>; 136 137 io_expander: gpio@20 { 138 compatible = "onnn,pca9654"; 139 reg = <0x20>; 140 gpio-controller; 141 #gpio-cells = <2>; 142 }; 143 144 hdmi@39 { 145 compatible = "adi,adv7511w"; 146 reg = <0x39>; 147 interrupt-parent = <&gpio1>; 148 interrupts = <20 IRQ_TYPE_LEVEL_LOW>; 149 150 adi,input-depth = <8>; 151 adi,input-colorspace = "rgb"; 152 adi,input-clock = "1x"; 153 154 ports { 155 #address-cells = <1>; 156 #size-cells = <0>; 157 158 port@0 { 159 reg = <0>; 160 adv7511_in: endpoint { 161 remote-endpoint = <&thc63lvd1024_out>; 162 }; 163 }; 164 165 port@1 { 166 reg = <1>; 167 adv7511_out: endpoint { 168 remote-endpoint = <&hdmi_con_out>; 169 }; 170 }; 171 }; 172 }; 173}; 174 175&lvds0 { 176 status = "okay"; 177 178 ports { 179 port@1 { 180 lvds0_out: endpoint { 181 remote-endpoint = <&thc63lvd1024_in>; 182 }; 183 }; 184 }; 185}; 186 187&pfc { 188 avb_pins: avb0 { 189 groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; 190 function = "avb0"; 191 }; 192 193 canfd0_pins: canfd0 { 194 groups = "canfd0_data_a"; 195 function = "canfd0"; 196 }; 197 198 i2c0_pins: i2c0 { 199 groups = "i2c0"; 200 function = "i2c0"; 201 }; 202 203 qspi0_pins: qspi0 { 204 groups = "qspi0_ctrl", "qspi0_data4"; 205 function = "qspi0"; 206 }; 207 208 scif0_pins: scif0 { 209 groups = "scif0_data"; 210 function = "scif0"; 211 }; 212}; 213 214&rpc { 215 pinctrl-0 = <&qspi0_pins>; 216 pinctrl-names = "default"; 217 218 status = "okay"; 219 220 flash@0 { 221 compatible = "spansion,s25fs512s", "jedec,spi-nor"; 222 reg = <0>; 223 spi-max-frequency = <50000000>; 224 spi-rx-bus-width = <4>; 225 226 partitions { 227 compatible = "fixed-partitions"; 228 #address-cells = <1>; 229 #size-cells = <1>; 230 231 bootparam@0 { 232 reg = <0x00000000 0x040000>; 233 read-only; 234 }; 235 cr7@40000 { 236 reg = <0x00040000 0x080000>; 237 read-only; 238 }; 239 cert_header_sa3@c0000 { 240 reg = <0x000c0000 0x080000>; 241 read-only; 242 }; 243 bl2@140000 { 244 reg = <0x00140000 0x040000>; 245 read-only; 246 }; 247 cert_header_sa6@180000 { 248 reg = <0x00180000 0x040000>; 249 read-only; 250 }; 251 bl31@1c0000 { 252 reg = <0x001c0000 0x460000>; 253 read-only; 254 }; 255 uboot@640000 { 256 reg = <0x00640000 0x0c0000>; 257 read-only; 258 }; 259 uboot-env@700000 { 260 reg = <0x00700000 0x040000>; 261 read-only; 262 }; 263 dtb@740000 { 264 reg = <0x00740000 0x080000>; 265 }; 266 kernel@7c0000 { 267 reg = <0x007c0000 0x1400000>; 268 }; 269 user@1bc0000 { 270 reg = <0x01bc0000 0x2440000>; 271 }; 272 }; 273 }; 274}; 275 276&rwdt { 277 timeout-sec = <60>; 278 status = "okay"; 279}; 280 281&scif0 { 282 pinctrl-0 = <&scif0_pins>; 283 pinctrl-names = "default"; 284 285 status = "okay"; 286}; 287