1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC 4 * 5 * Copyright (C) 2016-2017 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a77961-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a77961-sysc.h> 11 12#define CPG_AUDIO_CLK_I R8A77961_CLK_S0D4 13 14/ { 15 compatible = "renesas,r8a77961"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 /* 20 * The external audio clocks are configured as 0 Hz fixed frequency 21 * clocks by default. 22 * Boards that provide audio clocks should override them. 23 */ 24 audio_clk_a: audio_clk_a { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 clock-frequency = <0>; 28 }; 29 30 audio_clk_b: audio_clk_b { 31 compatible = "fixed-clock"; 32 #clock-cells = <0>; 33 clock-frequency = <0>; 34 }; 35 36 audio_clk_c: audio_clk_c { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <0>; 40 }; 41 42 /* External CAN clock - to be overridden by boards that provide it */ 43 can_clk: can { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <0>; 47 }; 48 49 cluster0_opp: opp_table0 { 50 compatible = "operating-points-v2"; 51 opp-shared; 52 53 opp-500000000 { 54 opp-hz = /bits/ 64 <500000000>; 55 opp-microvolt = <820000>; 56 clock-latency-ns = <300000>; 57 }; 58 opp-1000000000 { 59 opp-hz = /bits/ 64 <1000000000>; 60 opp-microvolt = <820000>; 61 clock-latency-ns = <300000>; 62 }; 63 opp-1500000000 { 64 opp-hz = /bits/ 64 <1500000000>; 65 opp-microvolt = <820000>; 66 clock-latency-ns = <300000>; 67 }; 68 opp-1600000000 { 69 opp-hz = /bits/ 64 <1600000000>; 70 opp-microvolt = <900000>; 71 clock-latency-ns = <300000>; 72 turbo-mode; 73 }; 74 opp-1700000000 { 75 opp-hz = /bits/ 64 <1700000000>; 76 opp-microvolt = <900000>; 77 clock-latency-ns = <300000>; 78 turbo-mode; 79 }; 80 opp-1800000000 { 81 opp-hz = /bits/ 64 <1800000000>; 82 opp-microvolt = <960000>; 83 clock-latency-ns = <300000>; 84 turbo-mode; 85 }; 86 }; 87 88 cluster1_opp: opp_table1 { 89 compatible = "operating-points-v2"; 90 opp-shared; 91 92 opp-800000000 { 93 opp-hz = /bits/ 64 <800000000>; 94 opp-microvolt = <820000>; 95 clock-latency-ns = <300000>; 96 }; 97 opp-1000000000 { 98 opp-hz = /bits/ 64 <1000000000>; 99 opp-microvolt = <820000>; 100 clock-latency-ns = <300000>; 101 }; 102 opp-1200000000 { 103 opp-hz = /bits/ 64 <1200000000>; 104 opp-microvolt = <820000>; 105 clock-latency-ns = <300000>; 106 }; 107 opp-1300000000 { 108 opp-hz = /bits/ 64 <1300000000>; 109 opp-microvolt = <820000>; 110 clock-latency-ns = <300000>; 111 turbo-mode; 112 }; 113 }; 114 115 cpus { 116 #address-cells = <1>; 117 #size-cells = <0>; 118 119 cpu-map { 120 cluster0 { 121 core0 { 122 cpu = <&a57_0>; 123 }; 124 core1 { 125 cpu = <&a57_1>; 126 }; 127 }; 128 129 cluster1 { 130 core0 { 131 cpu = <&a53_0>; 132 }; 133 core1 { 134 cpu = <&a53_1>; 135 }; 136 core2 { 137 cpu = <&a53_2>; 138 }; 139 core3 { 140 cpu = <&a53_3>; 141 }; 142 }; 143 }; 144 145 a57_0: cpu@0 { 146 compatible = "arm,cortex-a57"; 147 reg = <0x0>; 148 device_type = "cpu"; 149 power-domains = <&sysc R8A77961_PD_CA57_CPU0>; 150 next-level-cache = <&L2_CA57>; 151 enable-method = "psci"; 152 cpu-idle-states = <&CPU_SLEEP_0>; 153 dynamic-power-coefficient = <854>; 154 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; 155 operating-points-v2 = <&cluster0_opp>; 156 capacity-dmips-mhz = <1024>; 157 #cooling-cells = <2>; 158 }; 159 160 a57_1: cpu@1 { 161 compatible = "arm,cortex-a57"; 162 reg = <0x1>; 163 device_type = "cpu"; 164 power-domains = <&sysc R8A77961_PD_CA57_CPU1>; 165 next-level-cache = <&L2_CA57>; 166 enable-method = "psci"; 167 cpu-idle-states = <&CPU_SLEEP_0>; 168 clocks = <&cpg CPG_CORE R8A77961_CLK_Z>; 169 operating-points-v2 = <&cluster0_opp>; 170 capacity-dmips-mhz = <1024>; 171 #cooling-cells = <2>; 172 }; 173 174 a53_0: cpu@100 { 175 compatible = "arm,cortex-a53"; 176 reg = <0x100>; 177 device_type = "cpu"; 178 power-domains = <&sysc R8A77961_PD_CA53_CPU0>; 179 next-level-cache = <&L2_CA53>; 180 enable-method = "psci"; 181 cpu-idle-states = <&CPU_SLEEP_1>; 182 #cooling-cells = <2>; 183 dynamic-power-coefficient = <277>; 184 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 185 operating-points-v2 = <&cluster1_opp>; 186 capacity-dmips-mhz = <535>; 187 }; 188 189 a53_1: cpu@101 { 190 compatible = "arm,cortex-a53"; 191 reg = <0x101>; 192 device_type = "cpu"; 193 power-domains = <&sysc R8A77961_PD_CA53_CPU1>; 194 next-level-cache = <&L2_CA53>; 195 enable-method = "psci"; 196 cpu-idle-states = <&CPU_SLEEP_1>; 197 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 198 operating-points-v2 = <&cluster1_opp>; 199 capacity-dmips-mhz = <535>; 200 }; 201 202 a53_2: cpu@102 { 203 compatible = "arm,cortex-a53"; 204 reg = <0x102>; 205 device_type = "cpu"; 206 power-domains = <&sysc R8A77961_PD_CA53_CPU2>; 207 next-level-cache = <&L2_CA53>; 208 enable-method = "psci"; 209 cpu-idle-states = <&CPU_SLEEP_1>; 210 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 211 operating-points-v2 = <&cluster1_opp>; 212 capacity-dmips-mhz = <535>; 213 }; 214 215 a53_3: cpu@103 { 216 compatible = "arm,cortex-a53"; 217 reg = <0x103>; 218 device_type = "cpu"; 219 power-domains = <&sysc R8A77961_PD_CA53_CPU3>; 220 next-level-cache = <&L2_CA53>; 221 enable-method = "psci"; 222 cpu-idle-states = <&CPU_SLEEP_1>; 223 clocks = <&cpg CPG_CORE R8A77961_CLK_Z2>; 224 operating-points-v2 = <&cluster1_opp>; 225 capacity-dmips-mhz = <535>; 226 }; 227 228 L2_CA57: cache-controller-0 { 229 compatible = "cache"; 230 power-domains = <&sysc R8A77961_PD_CA57_SCU>; 231 cache-unified; 232 cache-level = <2>; 233 }; 234 235 L2_CA53: cache-controller-1 { 236 compatible = "cache"; 237 power-domains = <&sysc R8A77961_PD_CA53_SCU>; 238 cache-unified; 239 cache-level = <2>; 240 }; 241 242 idle-states { 243 entry-method = "psci"; 244 245 CPU_SLEEP_0: cpu-sleep-0 { 246 compatible = "arm,idle-state"; 247 arm,psci-suspend-param = <0x0010000>; 248 local-timer-stop; 249 entry-latency-us = <400>; 250 exit-latency-us = <500>; 251 min-residency-us = <4000>; 252 }; 253 254 CPU_SLEEP_1: cpu-sleep-1 { 255 compatible = "arm,idle-state"; 256 arm,psci-suspend-param = <0x0010000>; 257 local-timer-stop; 258 entry-latency-us = <700>; 259 exit-latency-us = <700>; 260 min-residency-us = <5000>; 261 }; 262 }; 263 }; 264 265 extal_clk: extal { 266 compatible = "fixed-clock"; 267 #clock-cells = <0>; 268 /* This value must be overridden by the board */ 269 clock-frequency = <0>; 270 }; 271 272 extalr_clk: extalr { 273 compatible = "fixed-clock"; 274 #clock-cells = <0>; 275 /* This value must be overridden by the board */ 276 clock-frequency = <0>; 277 }; 278 279 /* External PCIe clock - can be overridden by the board */ 280 pcie_bus_clk: pcie_bus { 281 compatible = "fixed-clock"; 282 #clock-cells = <0>; 283 clock-frequency = <0>; 284 }; 285 286 pmu_a53 { 287 compatible = "arm,cortex-a53-pmu"; 288 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 289 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 290 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 291 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 292 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 293 }; 294 295 pmu_a57 { 296 compatible = "arm,cortex-a57-pmu"; 297 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 298 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 299 interrupt-affinity = <&a57_0>, <&a57_1>; 300 }; 301 302 psci { 303 compatible = "arm,psci-1.0", "arm,psci-0.2"; 304 method = "smc"; 305 }; 306 307 /* External SCIF clock - to be overridden by boards that provide it */ 308 scif_clk: scif { 309 compatible = "fixed-clock"; 310 #clock-cells = <0>; 311 clock-frequency = <0>; 312 }; 313 314 soc { 315 compatible = "simple-bus"; 316 interrupt-parent = <&gic>; 317 #address-cells = <2>; 318 #size-cells = <2>; 319 ranges; 320 321 rwdt: watchdog@e6020000 { 322 compatible = "renesas,r8a77961-wdt", 323 "renesas,rcar-gen3-wdt"; 324 reg = <0 0xe6020000 0 0x0c>; 325 clocks = <&cpg CPG_MOD 402>; 326 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 327 resets = <&cpg 402>; 328 status = "disabled"; 329 }; 330 331 gpio0: gpio@e6050000 { 332 compatible = "renesas,gpio-r8a77961", 333 "renesas,rcar-gen3-gpio"; 334 reg = <0 0xe6050000 0 0x50>; 335 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 336 #gpio-cells = <2>; 337 gpio-controller; 338 gpio-ranges = <&pfc 0 0 16>; 339 #interrupt-cells = <2>; 340 interrupt-controller; 341 clocks = <&cpg CPG_MOD 912>; 342 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 343 resets = <&cpg 912>; 344 }; 345 346 gpio1: gpio@e6051000 { 347 compatible = "renesas,gpio-r8a77961", 348 "renesas,rcar-gen3-gpio"; 349 reg = <0 0xe6051000 0 0x50>; 350 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 351 #gpio-cells = <2>; 352 gpio-controller; 353 gpio-ranges = <&pfc 0 32 29>; 354 #interrupt-cells = <2>; 355 interrupt-controller; 356 clocks = <&cpg CPG_MOD 911>; 357 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 358 resets = <&cpg 911>; 359 }; 360 361 gpio2: gpio@e6052000 { 362 compatible = "renesas,gpio-r8a77961", 363 "renesas,rcar-gen3-gpio"; 364 reg = <0 0xe6052000 0 0x50>; 365 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 366 #gpio-cells = <2>; 367 gpio-controller; 368 gpio-ranges = <&pfc 0 64 15>; 369 #interrupt-cells = <2>; 370 interrupt-controller; 371 clocks = <&cpg CPG_MOD 910>; 372 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 373 resets = <&cpg 910>; 374 }; 375 376 gpio3: gpio@e6053000 { 377 compatible = "renesas,gpio-r8a77961", 378 "renesas,rcar-gen3-gpio"; 379 reg = <0 0xe6053000 0 0x50>; 380 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 381 #gpio-cells = <2>; 382 gpio-controller; 383 gpio-ranges = <&pfc 0 96 16>; 384 #interrupt-cells = <2>; 385 interrupt-controller; 386 clocks = <&cpg CPG_MOD 909>; 387 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 388 resets = <&cpg 909>; 389 }; 390 391 gpio4: gpio@e6054000 { 392 compatible = "renesas,gpio-r8a77961", 393 "renesas,rcar-gen3-gpio"; 394 reg = <0 0xe6054000 0 0x50>; 395 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 396 #gpio-cells = <2>; 397 gpio-controller; 398 gpio-ranges = <&pfc 0 128 18>; 399 #interrupt-cells = <2>; 400 interrupt-controller; 401 clocks = <&cpg CPG_MOD 908>; 402 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 403 resets = <&cpg 908>; 404 }; 405 406 gpio5: gpio@e6055000 { 407 compatible = "renesas,gpio-r8a77961", 408 "renesas,rcar-gen3-gpio"; 409 reg = <0 0xe6055000 0 0x50>; 410 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 411 #gpio-cells = <2>; 412 gpio-controller; 413 gpio-ranges = <&pfc 0 160 26>; 414 #interrupt-cells = <2>; 415 interrupt-controller; 416 clocks = <&cpg CPG_MOD 907>; 417 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 418 resets = <&cpg 907>; 419 }; 420 421 gpio6: gpio@e6055400 { 422 compatible = "renesas,gpio-r8a77961", 423 "renesas,rcar-gen3-gpio"; 424 reg = <0 0xe6055400 0 0x50>; 425 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 426 #gpio-cells = <2>; 427 gpio-controller; 428 gpio-ranges = <&pfc 0 192 32>; 429 #interrupt-cells = <2>; 430 interrupt-controller; 431 clocks = <&cpg CPG_MOD 906>; 432 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 433 resets = <&cpg 906>; 434 }; 435 436 gpio7: gpio@e6055800 { 437 compatible = "renesas,gpio-r8a77961", 438 "renesas,rcar-gen3-gpio"; 439 reg = <0 0xe6055800 0 0x50>; 440 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 441 #gpio-cells = <2>; 442 gpio-controller; 443 gpio-ranges = <&pfc 0 224 4>; 444 #interrupt-cells = <2>; 445 interrupt-controller; 446 clocks = <&cpg CPG_MOD 905>; 447 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 448 resets = <&cpg 905>; 449 }; 450 451 pfc: pinctrl@e6060000 { 452 compatible = "renesas,pfc-r8a77961"; 453 reg = <0 0xe6060000 0 0x50c>; 454 }; 455 456 cpg: clock-controller@e6150000 { 457 compatible = "renesas,r8a77961-cpg-mssr"; 458 reg = <0 0xe6150000 0 0x1000>; 459 clocks = <&extal_clk>, <&extalr_clk>; 460 clock-names = "extal", "extalr"; 461 #clock-cells = <2>; 462 #power-domain-cells = <0>; 463 #reset-cells = <1>; 464 }; 465 466 rst: reset-controller@e6160000 { 467 compatible = "renesas,r8a77961-rst"; 468 reg = <0 0xe6160000 0 0x0200>; 469 }; 470 471 sysc: system-controller@e6180000 { 472 compatible = "renesas,r8a77961-sysc"; 473 reg = <0 0xe6180000 0 0x0400>; 474 #power-domain-cells = <1>; 475 }; 476 477 tsc: thermal@e6198000 { 478 compatible = "renesas,r8a77961-thermal"; 479 reg = <0 0xe6198000 0 0x100>, 480 <0 0xe61a0000 0 0x100>, 481 <0 0xe61a8000 0 0x100>; 482 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 485 clocks = <&cpg CPG_MOD 522>; 486 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 487 resets = <&cpg 522>; 488 #thermal-sensor-cells = <1>; 489 }; 490 491 intc_ex: interrupt-controller@e61c0000 { 492 #interrupt-cells = <2>; 493 interrupt-controller; 494 reg = <0 0xe61c0000 0 0x200>; 495 /* placeholder */ 496 }; 497 498 i2c0: i2c@e6500000 { 499 #address-cells = <1>; 500 #size-cells = <0>; 501 compatible = "renesas,i2c-r8a77961", 502 "renesas,rcar-gen3-i2c"; 503 reg = <0 0xe6500000 0 0x40>; 504 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 505 clocks = <&cpg CPG_MOD 931>; 506 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 507 resets = <&cpg 931>; 508 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 509 <&dmac2 0x91>, <&dmac2 0x90>; 510 dma-names = "tx", "rx", "tx", "rx"; 511 i2c-scl-internal-delay-ns = <110>; 512 status = "disabled"; 513 }; 514 515 i2c1: i2c@e6508000 { 516 #address-cells = <1>; 517 #size-cells = <0>; 518 compatible = "renesas,i2c-r8a77961", 519 "renesas,rcar-gen3-i2c"; 520 reg = <0 0xe6508000 0 0x40>; 521 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&cpg CPG_MOD 930>; 523 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 524 resets = <&cpg 930>; 525 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 526 <&dmac2 0x93>, <&dmac2 0x92>; 527 dma-names = "tx", "rx", "tx", "rx"; 528 i2c-scl-internal-delay-ns = <6>; 529 status = "disabled"; 530 }; 531 532 i2c2: i2c@e6510000 { 533 #address-cells = <1>; 534 #size-cells = <0>; 535 compatible = "renesas,i2c-r8a77961", 536 "renesas,rcar-gen3-i2c"; 537 reg = <0 0xe6510000 0 0x40>; 538 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&cpg CPG_MOD 929>; 540 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 541 resets = <&cpg 929>; 542 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 543 <&dmac2 0x95>, <&dmac2 0x94>; 544 dma-names = "tx", "rx", "tx", "rx"; 545 i2c-scl-internal-delay-ns = <6>; 546 status = "disabled"; 547 }; 548 549 i2c3: i2c@e66d0000 { 550 #address-cells = <1>; 551 #size-cells = <0>; 552 compatible = "renesas,i2c-r8a77961", 553 "renesas,rcar-gen3-i2c"; 554 reg = <0 0xe66d0000 0 0x40>; 555 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&cpg CPG_MOD 928>; 557 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 558 resets = <&cpg 928>; 559 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 560 dma-names = "tx", "rx"; 561 i2c-scl-internal-delay-ns = <110>; 562 status = "disabled"; 563 }; 564 565 i2c4: i2c@e66d8000 { 566 #address-cells = <1>; 567 #size-cells = <0>; 568 compatible = "renesas,i2c-r8a77961", 569 "renesas,rcar-gen3-i2c"; 570 reg = <0 0xe66d8000 0 0x40>; 571 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&cpg CPG_MOD 927>; 573 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 574 resets = <&cpg 927>; 575 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 576 dma-names = "tx", "rx"; 577 i2c-scl-internal-delay-ns = <110>; 578 status = "disabled"; 579 }; 580 581 i2c5: i2c@e66e0000 { 582 #address-cells = <1>; 583 #size-cells = <0>; 584 compatible = "renesas,i2c-r8a77961", 585 "renesas,rcar-gen3-i2c"; 586 reg = <0 0xe66e0000 0 0x40>; 587 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&cpg CPG_MOD 919>; 589 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 590 resets = <&cpg 919>; 591 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 592 dma-names = "tx", "rx"; 593 i2c-scl-internal-delay-ns = <110>; 594 status = "disabled"; 595 }; 596 597 i2c6: i2c@e66e8000 { 598 #address-cells = <1>; 599 #size-cells = <0>; 600 compatible = "renesas,i2c-r8a77961", 601 "renesas,rcar-gen3-i2c"; 602 reg = <0 0xe66e8000 0 0x40>; 603 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 604 clocks = <&cpg CPG_MOD 918>; 605 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 606 resets = <&cpg 918>; 607 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 608 dma-names = "tx", "rx"; 609 i2c-scl-internal-delay-ns = <6>; 610 status = "disabled"; 611 }; 612 613 i2c_dvfs: i2c@e60b0000 { 614 #address-cells = <1>; 615 #size-cells = <0>; 616 compatible = "renesas,iic-r8a77961", 617 "renesas,rcar-gen3-iic", 618 "renesas,rmobile-iic"; 619 reg = <0 0xe60b0000 0 0x425>; 620 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&cpg CPG_MOD 926>; 622 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 623 resets = <&cpg 926>; 624 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 625 dma-names = "tx", "rx"; 626 status = "disabled"; 627 }; 628 629 hscif0: serial@e6540000 { 630 compatible = "renesas,hscif-r8a77961", 631 "renesas,rcar-gen3-hscif", 632 "renesas,hscif"; 633 reg = <0 0xe6540000 0 0x60>; 634 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 635 clocks = <&cpg CPG_MOD 520>, 636 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 637 <&scif_clk>; 638 clock-names = "fck", "brg_int", "scif_clk"; 639 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 640 <&dmac2 0x31>, <&dmac2 0x30>; 641 dma-names = "tx", "rx", "tx", "rx"; 642 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 643 resets = <&cpg 520>; 644 status = "disabled"; 645 }; 646 647 hscif1: serial@e6550000 { 648 compatible = "renesas,hscif-r8a77961", 649 "renesas,rcar-gen3-hscif", 650 "renesas,hscif"; 651 reg = <0 0xe6550000 0 0x60>; 652 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&cpg CPG_MOD 519>, 654 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 655 <&scif_clk>; 656 clock-names = "fck", "brg_int", "scif_clk"; 657 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 658 <&dmac2 0x33>, <&dmac2 0x32>; 659 dma-names = "tx", "rx", "tx", "rx"; 660 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 661 resets = <&cpg 519>; 662 status = "disabled"; 663 }; 664 665 hscif2: serial@e6560000 { 666 compatible = "renesas,hscif-r8a77961", 667 "renesas,rcar-gen3-hscif", 668 "renesas,hscif"; 669 reg = <0 0xe6560000 0 0x60>; 670 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&cpg CPG_MOD 518>, 672 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 673 <&scif_clk>; 674 clock-names = "fck", "brg_int", "scif_clk"; 675 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 676 <&dmac2 0x35>, <&dmac2 0x34>; 677 dma-names = "tx", "rx", "tx", "rx"; 678 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 679 resets = <&cpg 518>; 680 status = "disabled"; 681 }; 682 683 hscif3: serial@e66a0000 { 684 compatible = "renesas,hscif-r8a77961", 685 "renesas,rcar-gen3-hscif", 686 "renesas,hscif"; 687 reg = <0 0xe66a0000 0 0x60>; 688 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&cpg CPG_MOD 517>, 690 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 691 <&scif_clk>; 692 clock-names = "fck", "brg_int", "scif_clk"; 693 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 694 dma-names = "tx", "rx"; 695 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 696 resets = <&cpg 517>; 697 status = "disabled"; 698 }; 699 700 hscif4: serial@e66b0000 { 701 compatible = "renesas,hscif-r8a77961", 702 "renesas,rcar-gen3-hscif", 703 "renesas,hscif"; 704 reg = <0 0xe66b0000 0 0x60>; 705 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&cpg CPG_MOD 516>, 707 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 708 <&scif_clk>; 709 clock-names = "fck", "brg_int", "scif_clk"; 710 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 711 dma-names = "tx", "rx"; 712 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 713 resets = <&cpg 516>; 714 status = "disabled"; 715 }; 716 717 hsusb: usb@e6590000 { 718 compatible = "renesas,usbhs-r8a77961", 719 "renesas,rcar-gen3-usbhs"; 720 reg = <0 0xe6590000 0 0x200>; 721 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 723 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 724 <&usb_dmac1 0>, <&usb_dmac1 1>; 725 dma-names = "ch0", "ch1", "ch2", "ch3"; 726 renesas,buswait = <11>; 727 phys = <&usb2_phy0 3>; 728 phy-names = "usb"; 729 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 730 resets = <&cpg 704>, <&cpg 703>; 731 status = "disabled"; 732 }; 733 734 usb_dmac0: dma-controller@e65a0000 { 735 compatible = "renesas,r8a77961-usb-dmac", 736 "renesas,usb-dmac"; 737 reg = <0 0xe65a0000 0 0x100>; 738 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 740 interrupt-names = "ch0", "ch1"; 741 clocks = <&cpg CPG_MOD 330>; 742 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 743 resets = <&cpg 330>; 744 #dma-cells = <1>; 745 dma-channels = <2>; 746 }; 747 748 usb_dmac1: dma-controller@e65b0000 { 749 compatible = "renesas,r8a77961-usb-dmac", 750 "renesas,usb-dmac"; 751 reg = <0 0xe65b0000 0 0x100>; 752 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 754 interrupt-names = "ch0", "ch1"; 755 clocks = <&cpg CPG_MOD 331>; 756 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 757 resets = <&cpg 331>; 758 #dma-cells = <1>; 759 dma-channels = <2>; 760 }; 761 762 usb3_phy0: usb-phy@e65ee000 { 763 compatible = "renesas,r8a77961-usb3-phy", 764 "renesas,rcar-gen3-usb3-phy"; 765 reg = <0 0xe65ee000 0 0x90>; 766 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 767 <&usb_extal_clk>; 768 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 769 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 770 resets = <&cpg 328>; 771 #phy-cells = <0>; 772 status = "disabled"; 773 }; 774 775 arm_cc630p: crypto@e6601000 { 776 compatible = "arm,cryptocell-630p-ree"; 777 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 778 reg = <0x0 0xe6601000 0 0x1000>; 779 clocks = <&cpg CPG_MOD 229>; 780 resets = <&cpg 229>; 781 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 782 }; 783 784 dmac0: dma-controller@e6700000 { 785 compatible = "renesas,dmac-r8a77961", 786 "renesas,rcar-dmac"; 787 reg = <0 0xe6700000 0 0x10000>; 788 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 802 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 803 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 805 interrupt-names = "error", 806 "ch0", "ch1", "ch2", "ch3", 807 "ch4", "ch5", "ch6", "ch7", 808 "ch8", "ch9", "ch10", "ch11", 809 "ch12", "ch13", "ch14", "ch15"; 810 clocks = <&cpg CPG_MOD 219>; 811 clock-names = "fck"; 812 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 813 resets = <&cpg 219>; 814 #dma-cells = <1>; 815 dma-channels = <16>; 816 }; 817 818 dmac1: dma-controller@e7300000 { 819 compatible = "renesas,dmac-r8a77961", 820 "renesas,rcar-dmac"; 821 reg = <0 0xe7300000 0 0x10000>; 822 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 839 interrupt-names = "error", 840 "ch0", "ch1", "ch2", "ch3", 841 "ch4", "ch5", "ch6", "ch7", 842 "ch8", "ch9", "ch10", "ch11", 843 "ch12", "ch13", "ch14", "ch15"; 844 clocks = <&cpg CPG_MOD 218>; 845 clock-names = "fck"; 846 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 847 resets = <&cpg 218>; 848 #dma-cells = <1>; 849 dma-channels = <16>; 850 }; 851 852 dmac2: dma-controller@e7310000 { 853 compatible = "renesas,dmac-r8a77961", 854 "renesas,rcar-dmac"; 855 reg = <0 0xe7310000 0 0x10000>; 856 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 857 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 858 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 873 interrupt-names = "error", 874 "ch0", "ch1", "ch2", "ch3", 875 "ch4", "ch5", "ch6", "ch7", 876 "ch8", "ch9", "ch10", "ch11", 877 "ch12", "ch13", "ch14", "ch15"; 878 clocks = <&cpg CPG_MOD 217>; 879 clock-names = "fck"; 880 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 881 resets = <&cpg 217>; 882 #dma-cells = <1>; 883 dma-channels = <16>; 884 }; 885 886 ipmmu_ds0: iommu@e6740000 { 887 compatible = "renesas,ipmmu-r8a77961"; 888 reg = <0 0xe6740000 0 0x1000>; 889 renesas,ipmmu-main = <&ipmmu_mm 0>; 890 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 891 #iommu-cells = <1>; 892 }; 893 894 ipmmu_ds1: iommu@e7740000 { 895 compatible = "renesas,ipmmu-r8a77961"; 896 reg = <0 0xe7740000 0 0x1000>; 897 renesas,ipmmu-main = <&ipmmu_mm 1>; 898 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 899 #iommu-cells = <1>; 900 }; 901 902 ipmmu_hc: iommu@e6570000 { 903 compatible = "renesas,ipmmu-r8a77961"; 904 reg = <0 0xe6570000 0 0x1000>; 905 renesas,ipmmu-main = <&ipmmu_mm 2>; 906 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 907 #iommu-cells = <1>; 908 }; 909 910 ipmmu_ir: iommu@ff8b0000 { 911 compatible = "renesas,ipmmu-r8a77961"; 912 reg = <0 0xff8b0000 0 0x1000>; 913 renesas,ipmmu-main = <&ipmmu_mm 3>; 914 power-domains = <&sysc R8A77961_PD_A3IR>; 915 #iommu-cells = <1>; 916 }; 917 918 ipmmu_mm: iommu@e67b0000 { 919 compatible = "renesas,ipmmu-r8a77961"; 920 reg = <0 0xe67b0000 0 0x1000>; 921 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 923 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 924 #iommu-cells = <1>; 925 }; 926 927 ipmmu_mp: iommu@ec670000 { 928 compatible = "renesas,ipmmu-r8a77961"; 929 reg = <0 0xec670000 0 0x1000>; 930 renesas,ipmmu-main = <&ipmmu_mm 4>; 931 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 932 #iommu-cells = <1>; 933 }; 934 935 ipmmu_pv0: iommu@fd800000 { 936 compatible = "renesas,ipmmu-r8a77961"; 937 reg = <0 0xfd800000 0 0x1000>; 938 renesas,ipmmu-main = <&ipmmu_mm 5>; 939 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 940 #iommu-cells = <1>; 941 }; 942 943 ipmmu_pv1: iommu@fd950000 { 944 compatible = "renesas,ipmmu-r8a77961"; 945 reg = <0 0xfd950000 0 0x1000>; 946 renesas,ipmmu-main = <&ipmmu_mm 6>; 947 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 948 #iommu-cells = <1>; 949 }; 950 951 ipmmu_rt: iommu@ffc80000 { 952 compatible = "renesas,ipmmu-r8a77961"; 953 reg = <0 0xffc80000 0 0x1000>; 954 renesas,ipmmu-main = <&ipmmu_mm 7>; 955 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 956 #iommu-cells = <1>; 957 }; 958 959 ipmmu_vc0: iommu@fe6b0000 { 960 compatible = "renesas,ipmmu-r8a77961"; 961 reg = <0 0xfe6b0000 0 0x1000>; 962 renesas,ipmmu-main = <&ipmmu_mm 8>; 963 power-domains = <&sysc R8A77961_PD_A3VC>; 964 #iommu-cells = <1>; 965 }; 966 967 ipmmu_vi0: iommu@febd0000 { 968 compatible = "renesas,ipmmu-r8a77961"; 969 reg = <0 0xfebd0000 0 0x1000>; 970 renesas,ipmmu-main = <&ipmmu_mm 9>; 971 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 972 #iommu-cells = <1>; 973 }; 974 975 avb: ethernet@e6800000 { 976 compatible = "renesas,etheravb-r8a77961", 977 "renesas,etheravb-rcar-gen3"; 978 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 979 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 980 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 982 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 983 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 984 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1003 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1004 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1005 "ch4", "ch5", "ch6", "ch7", 1006 "ch8", "ch9", "ch10", "ch11", 1007 "ch12", "ch13", "ch14", "ch15", 1008 "ch16", "ch17", "ch18", "ch19", 1009 "ch20", "ch21", "ch22", "ch23", 1010 "ch24"; 1011 clocks = <&cpg CPG_MOD 812>; 1012 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1013 resets = <&cpg 812>; 1014 phy-mode = "rgmii"; 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 status = "disabled"; 1018 }; 1019 1020 pwm0: pwm@e6e30000 { 1021 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1022 reg = <0 0xe6e30000 0 8>; 1023 #pwm-cells = <2>; 1024 clocks = <&cpg CPG_MOD 523>; 1025 resets = <&cpg 523>; 1026 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1027 status = "disabled"; 1028 }; 1029 1030 pwm1: pwm@e6e31000 { 1031 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1032 reg = <0 0xe6e31000 0 8>; 1033 #pwm-cells = <2>; 1034 clocks = <&cpg CPG_MOD 523>; 1035 resets = <&cpg 523>; 1036 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1037 status = "disabled"; 1038 }; 1039 1040 pwm2: pwm@e6e32000 { 1041 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1042 reg = <0 0xe6e32000 0 8>; 1043 #pwm-cells = <2>; 1044 clocks = <&cpg CPG_MOD 523>; 1045 resets = <&cpg 523>; 1046 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1047 status = "disabled"; 1048 }; 1049 1050 pwm3: pwm@e6e33000 { 1051 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1052 reg = <0 0xe6e33000 0 8>; 1053 #pwm-cells = <2>; 1054 clocks = <&cpg CPG_MOD 523>; 1055 resets = <&cpg 523>; 1056 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1057 status = "disabled"; 1058 }; 1059 1060 pwm4: pwm@e6e34000 { 1061 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1062 reg = <0 0xe6e34000 0 8>; 1063 #pwm-cells = <2>; 1064 clocks = <&cpg CPG_MOD 523>; 1065 resets = <&cpg 523>; 1066 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1067 status = "disabled"; 1068 }; 1069 1070 pwm5: pwm@e6e35000 { 1071 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1072 reg = <0 0xe6e35000 0 8>; 1073 #pwm-cells = <2>; 1074 clocks = <&cpg CPG_MOD 523>; 1075 resets = <&cpg 523>; 1076 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1077 status = "disabled"; 1078 }; 1079 1080 pwm6: pwm@e6e36000 { 1081 compatible = "renesas,pwm-r8a77961", "renesas,pwm-rcar"; 1082 reg = <0 0xe6e36000 0 8>; 1083 #pwm-cells = <2>; 1084 clocks = <&cpg CPG_MOD 523>; 1085 resets = <&cpg 523>; 1086 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1087 status = "disabled"; 1088 }; 1089 1090 scif0: serial@e6e60000 { 1091 compatible = "renesas,scif-r8a77961", 1092 "renesas,rcar-gen3-scif", "renesas,scif"; 1093 reg = <0 0xe6e60000 0 64>; 1094 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1095 clocks = <&cpg CPG_MOD 207>, 1096 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1097 <&scif_clk>; 1098 clock-names = "fck", "brg_int", "scif_clk"; 1099 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1100 <&dmac2 0x51>, <&dmac2 0x50>; 1101 dma-names = "tx", "rx", "tx", "rx"; 1102 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1103 resets = <&cpg 207>; 1104 status = "disabled"; 1105 }; 1106 1107 scif1: serial@e6e68000 { 1108 compatible = "renesas,scif-r8a77961", 1109 "renesas,rcar-gen3-scif", "renesas,scif"; 1110 reg = <0 0xe6e68000 0 64>; 1111 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1112 clocks = <&cpg CPG_MOD 206>, 1113 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1114 <&scif_clk>; 1115 clock-names = "fck", "brg_int", "scif_clk"; 1116 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1117 <&dmac2 0x53>, <&dmac2 0x52>; 1118 dma-names = "tx", "rx", "tx", "rx"; 1119 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1120 resets = <&cpg 206>; 1121 status = "disabled"; 1122 }; 1123 1124 scif2: serial@e6e88000 { 1125 compatible = "renesas,scif-r8a77961", 1126 "renesas,rcar-gen3-scif", "renesas,scif"; 1127 reg = <0 0xe6e88000 0 64>; 1128 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1129 clocks = <&cpg CPG_MOD 310>, 1130 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1131 <&scif_clk>; 1132 clock-names = "fck", "brg_int", "scif_clk"; 1133 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1134 <&dmac2 0x13>, <&dmac2 0x12>; 1135 dma-names = "tx", "rx", "tx", "rx"; 1136 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1137 resets = <&cpg 310>; 1138 status = "disabled"; 1139 }; 1140 1141 scif3: serial@e6c50000 { 1142 compatible = "renesas,scif-r8a77961", 1143 "renesas,rcar-gen3-scif", "renesas,scif"; 1144 reg = <0 0xe6c50000 0 64>; 1145 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1146 clocks = <&cpg CPG_MOD 204>, 1147 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1148 <&scif_clk>; 1149 clock-names = "fck", "brg_int", "scif_clk"; 1150 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1151 dma-names = "tx", "rx"; 1152 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1153 resets = <&cpg 204>; 1154 status = "disabled"; 1155 }; 1156 1157 scif4: serial@e6c40000 { 1158 compatible = "renesas,scif-r8a77961", 1159 "renesas,rcar-gen3-scif", "renesas,scif"; 1160 reg = <0 0xe6c40000 0 64>; 1161 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1162 clocks = <&cpg CPG_MOD 203>, 1163 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1164 <&scif_clk>; 1165 clock-names = "fck", "brg_int", "scif_clk"; 1166 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1167 dma-names = "tx", "rx"; 1168 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1169 resets = <&cpg 203>; 1170 status = "disabled"; 1171 }; 1172 1173 scif5: serial@e6f30000 { 1174 compatible = "renesas,scif-r8a77961", 1175 "renesas,rcar-gen3-scif", "renesas,scif"; 1176 reg = <0 0xe6f30000 0 64>; 1177 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1178 clocks = <&cpg CPG_MOD 202>, 1179 <&cpg CPG_CORE R8A77961_CLK_S3D1>, 1180 <&scif_clk>; 1181 clock-names = "fck", "brg_int", "scif_clk"; 1182 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1183 <&dmac2 0x5b>, <&dmac2 0x5a>; 1184 dma-names = "tx", "rx", "tx", "rx"; 1185 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1186 resets = <&cpg 202>; 1187 status = "disabled"; 1188 }; 1189 1190 vin0: video@e6ef0000 { 1191 reg = <0 0xe6ef0000 0 0x1000>; 1192 /* placeholder */ 1193 }; 1194 1195 vin1: video@e6ef1000 { 1196 reg = <0 0xe6ef1000 0 0x1000>; 1197 /* placeholder */ 1198 }; 1199 1200 vin2: video@e6ef2000 { 1201 reg = <0 0xe6ef2000 0 0x1000>; 1202 /* placeholder */ 1203 }; 1204 1205 vin3: video@e6ef3000 { 1206 reg = <0 0xe6ef3000 0 0x1000>; 1207 /* placeholder */ 1208 }; 1209 1210 vin4: video@e6ef4000 { 1211 reg = <0 0xe6ef4000 0 0x1000>; 1212 /* placeholder */ 1213 }; 1214 1215 vin5: video@e6ef5000 { 1216 reg = <0 0xe6ef5000 0 0x1000>; 1217 /* placeholder */ 1218 }; 1219 1220 vin6: video@e6ef6000 { 1221 reg = <0 0xe6ef6000 0 0x1000>; 1222 /* placeholder */ 1223 }; 1224 1225 vin7: video@e6ef7000 { 1226 reg = <0 0xe6ef7000 0 0x1000>; 1227 /* placeholder */ 1228 }; 1229 1230 rcar_sound: sound@ec500000 { 1231 /* 1232 * #sound-dai-cells is required 1233 * 1234 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1235 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1236 */ 1237 /* 1238 * #clock-cells is required for audio_clkout0/1/2/3 1239 * 1240 * clkout : #clock-cells = <0>; <&rcar_sound>; 1241 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1242 */ 1243 compatible = "renesas,rcar_sound-r8a77961", "renesas,rcar_sound-gen3"; 1244 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1245 <0 0xec5a0000 0 0x100>, /* ADG */ 1246 <0 0xec540000 0 0x1000>, /* SSIU */ 1247 <0 0xec541000 0 0x280>, /* SSI */ 1248 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1249 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1250 1251 clocks = <&cpg CPG_MOD 1005>, 1252 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1253 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1254 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1255 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1256 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1257 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1258 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1259 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1260 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1261 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1262 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1263 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1264 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1265 <&audio_clk_a>, <&audio_clk_b>, 1266 <&audio_clk_c>, 1267 <&cpg CPG_CORE R8A77961_CLK_S0D4>; 1268 clock-names = "ssi-all", 1269 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1270 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1271 "ssi.1", "ssi.0", 1272 "src.9", "src.8", "src.7", "src.6", 1273 "src.5", "src.4", "src.3", "src.2", 1274 "src.1", "src.0", 1275 "mix.1", "mix.0", 1276 "ctu.1", "ctu.0", 1277 "dvc.0", "dvc.1", 1278 "clk_a", "clk_b", "clk_c", "clk_i"; 1279 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1280 resets = <&cpg 1005>, 1281 <&cpg 1006>, <&cpg 1007>, 1282 <&cpg 1008>, <&cpg 1009>, 1283 <&cpg 1010>, <&cpg 1011>, 1284 <&cpg 1012>, <&cpg 1013>, 1285 <&cpg 1014>, <&cpg 1015>; 1286 reset-names = "ssi-all", 1287 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1288 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1289 "ssi.1", "ssi.0"; 1290 status = "disabled"; 1291 1292 rcar_sound,ctu { 1293 ctu00: ctu-0 { }; 1294 ctu01: ctu-1 { }; 1295 ctu02: ctu-2 { }; 1296 ctu03: ctu-3 { }; 1297 ctu10: ctu-4 { }; 1298 ctu11: ctu-5 { }; 1299 ctu12: ctu-6 { }; 1300 ctu13: ctu-7 { }; 1301 }; 1302 1303 rcar_sound,dvc { 1304 dvc0: dvc-0 { 1305 dmas = <&audma1 0xbc>; 1306 dma-names = "tx"; 1307 }; 1308 dvc1: dvc-1 { 1309 dmas = <&audma1 0xbe>; 1310 dma-names = "tx"; 1311 }; 1312 }; 1313 1314 rcar_sound,mix { 1315 mix0: mix-0 { }; 1316 mix1: mix-1 { }; 1317 }; 1318 1319 rcar_sound,src { 1320 src0: src-0 { 1321 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1322 dmas = <&audma0 0x85>, <&audma1 0x9a>; 1323 dma-names = "rx", "tx"; 1324 }; 1325 src1: src-1 { 1326 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1327 dmas = <&audma0 0x87>, <&audma1 0x9c>; 1328 dma-names = "rx", "tx"; 1329 }; 1330 src2: src-2 { 1331 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1332 dmas = <&audma0 0x89>, <&audma1 0x9e>; 1333 dma-names = "rx", "tx"; 1334 }; 1335 src3: src-3 { 1336 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1337 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 1338 dma-names = "rx", "tx"; 1339 }; 1340 src4: src-4 { 1341 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1342 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 1343 dma-names = "rx", "tx"; 1344 }; 1345 src5: src-5 { 1346 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1347 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 1348 dma-names = "rx", "tx"; 1349 }; 1350 src6: src-6 { 1351 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1352 dmas = <&audma0 0x91>, <&audma1 0xb4>; 1353 dma-names = "rx", "tx"; 1354 }; 1355 src7: src-7 { 1356 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1357 dmas = <&audma0 0x93>, <&audma1 0xb6>; 1358 dma-names = "rx", "tx"; 1359 }; 1360 src8: src-8 { 1361 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1362 dmas = <&audma0 0x95>, <&audma1 0xb8>; 1363 dma-names = "rx", "tx"; 1364 }; 1365 src9: src-9 { 1366 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1367 dmas = <&audma0 0x97>, <&audma1 0xba>; 1368 dma-names = "rx", "tx"; 1369 }; 1370 }; 1371 1372 rcar_sound,ssi { 1373 ssi0: ssi-0 { 1374 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1375 dmas = <&audma0 0x01>, <&audma1 0x02>; 1376 dma-names = "rx", "tx"; 1377 }; 1378 ssi1: ssi-1 { 1379 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1380 dmas = <&audma0 0x03>, <&audma1 0x04>; 1381 dma-names = "rx", "tx"; 1382 }; 1383 ssi2: ssi-2 { 1384 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1385 dmas = <&audma0 0x05>, <&audma1 0x06>; 1386 dma-names = "rx", "tx"; 1387 }; 1388 ssi3: ssi-3 { 1389 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1390 dmas = <&audma0 0x07>, <&audma1 0x08>; 1391 dma-names = "rx", "tx"; 1392 }; 1393 ssi4: ssi-4 { 1394 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1395 dmas = <&audma0 0x09>, <&audma1 0x0a>; 1396 dma-names = "rx", "tx"; 1397 }; 1398 ssi5: ssi-5 { 1399 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1400 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 1401 dma-names = "rx", "tx"; 1402 }; 1403 ssi6: ssi-6 { 1404 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1405 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 1406 dma-names = "rx", "tx"; 1407 }; 1408 ssi7: ssi-7 { 1409 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1410 dmas = <&audma0 0x0f>, <&audma1 0x10>; 1411 dma-names = "rx", "tx"; 1412 }; 1413 ssi8: ssi-8 { 1414 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1415 dmas = <&audma0 0x11>, <&audma1 0x12>; 1416 dma-names = "rx", "tx"; 1417 }; 1418 ssi9: ssi-9 { 1419 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1420 dmas = <&audma0 0x13>, <&audma1 0x14>; 1421 dma-names = "rx", "tx"; 1422 }; 1423 }; 1424 1425 rcar_sound,ssiu { 1426 ssiu00: ssiu-0 { 1427 dmas = <&audma0 0x15>, <&audma1 0x16>; 1428 dma-names = "rx", "tx"; 1429 }; 1430 ssiu01: ssiu-1 { 1431 dmas = <&audma0 0x35>, <&audma1 0x36>; 1432 dma-names = "rx", "tx"; 1433 }; 1434 ssiu02: ssiu-2 { 1435 dmas = <&audma0 0x37>, <&audma1 0x38>; 1436 dma-names = "rx", "tx"; 1437 }; 1438 ssiu03: ssiu-3 { 1439 dmas = <&audma0 0x47>, <&audma1 0x48>; 1440 dma-names = "rx", "tx"; 1441 }; 1442 ssiu04: ssiu-4 { 1443 dmas = <&audma0 0x3F>, <&audma1 0x40>; 1444 dma-names = "rx", "tx"; 1445 }; 1446 ssiu05: ssiu-5 { 1447 dmas = <&audma0 0x43>, <&audma1 0x44>; 1448 dma-names = "rx", "tx"; 1449 }; 1450 ssiu06: ssiu-6 { 1451 dmas = <&audma0 0x4F>, <&audma1 0x50>; 1452 dma-names = "rx", "tx"; 1453 }; 1454 ssiu07: ssiu-7 { 1455 dmas = <&audma0 0x53>, <&audma1 0x54>; 1456 dma-names = "rx", "tx"; 1457 }; 1458 ssiu10: ssiu-8 { 1459 dmas = <&audma0 0x49>, <&audma1 0x4a>; 1460 dma-names = "rx", "tx"; 1461 }; 1462 ssiu11: ssiu-9 { 1463 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 1464 dma-names = "rx", "tx"; 1465 }; 1466 ssiu12: ssiu-10 { 1467 dmas = <&audma0 0x57>, <&audma1 0x58>; 1468 dma-names = "rx", "tx"; 1469 }; 1470 ssiu13: ssiu-11 { 1471 dmas = <&audma0 0x59>, <&audma1 0x5A>; 1472 dma-names = "rx", "tx"; 1473 }; 1474 ssiu14: ssiu-12 { 1475 dmas = <&audma0 0x5F>, <&audma1 0x60>; 1476 dma-names = "rx", "tx"; 1477 }; 1478 ssiu15: ssiu-13 { 1479 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 1480 dma-names = "rx", "tx"; 1481 }; 1482 ssiu16: ssiu-14 { 1483 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 1484 dma-names = "rx", "tx"; 1485 }; 1486 ssiu17: ssiu-15 { 1487 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 1488 dma-names = "rx", "tx"; 1489 }; 1490 ssiu20: ssiu-16 { 1491 dmas = <&audma0 0x63>, <&audma1 0x64>; 1492 dma-names = "rx", "tx"; 1493 }; 1494 ssiu21: ssiu-17 { 1495 dmas = <&audma0 0x67>, <&audma1 0x68>; 1496 dma-names = "rx", "tx"; 1497 }; 1498 ssiu22: ssiu-18 { 1499 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 1500 dma-names = "rx", "tx"; 1501 }; 1502 ssiu23: ssiu-19 { 1503 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 1504 dma-names = "rx", "tx"; 1505 }; 1506 ssiu24: ssiu-20 { 1507 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 1508 dma-names = "rx", "tx"; 1509 }; 1510 ssiu25: ssiu-21 { 1511 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 1512 dma-names = "rx", "tx"; 1513 }; 1514 ssiu26: ssiu-22 { 1515 dmas = <&audma0 0xED>, <&audma1 0xEE>; 1516 dma-names = "rx", "tx"; 1517 }; 1518 ssiu27: ssiu-23 { 1519 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 1520 dma-names = "rx", "tx"; 1521 }; 1522 ssiu30: ssiu-24 { 1523 dmas = <&audma0 0x6f>, <&audma1 0x70>; 1524 dma-names = "rx", "tx"; 1525 }; 1526 ssiu31: ssiu-25 { 1527 dmas = <&audma0 0x21>, <&audma1 0x22>; 1528 dma-names = "rx", "tx"; 1529 }; 1530 ssiu32: ssiu-26 { 1531 dmas = <&audma0 0x23>, <&audma1 0x24>; 1532 dma-names = "rx", "tx"; 1533 }; 1534 ssiu33: ssiu-27 { 1535 dmas = <&audma0 0x25>, <&audma1 0x26>; 1536 dma-names = "rx", "tx"; 1537 }; 1538 ssiu34: ssiu-28 { 1539 dmas = <&audma0 0x27>, <&audma1 0x28>; 1540 dma-names = "rx", "tx"; 1541 }; 1542 ssiu35: ssiu-29 { 1543 dmas = <&audma0 0x29>, <&audma1 0x2A>; 1544 dma-names = "rx", "tx"; 1545 }; 1546 ssiu36: ssiu-30 { 1547 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 1548 dma-names = "rx", "tx"; 1549 }; 1550 ssiu37: ssiu-31 { 1551 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 1552 dma-names = "rx", "tx"; 1553 }; 1554 ssiu40: ssiu-32 { 1555 dmas = <&audma0 0x71>, <&audma1 0x72>; 1556 dma-names = "rx", "tx"; 1557 }; 1558 ssiu41: ssiu-33 { 1559 dmas = <&audma0 0x17>, <&audma1 0x18>; 1560 dma-names = "rx", "tx"; 1561 }; 1562 ssiu42: ssiu-34 { 1563 dmas = <&audma0 0x19>, <&audma1 0x1A>; 1564 dma-names = "rx", "tx"; 1565 }; 1566 ssiu43: ssiu-35 { 1567 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 1568 dma-names = "rx", "tx"; 1569 }; 1570 ssiu44: ssiu-36 { 1571 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 1572 dma-names = "rx", "tx"; 1573 }; 1574 ssiu45: ssiu-37 { 1575 dmas = <&audma0 0x1F>, <&audma1 0x20>; 1576 dma-names = "rx", "tx"; 1577 }; 1578 ssiu46: ssiu-38 { 1579 dmas = <&audma0 0x31>, <&audma1 0x32>; 1580 dma-names = "rx", "tx"; 1581 }; 1582 ssiu47: ssiu-39 { 1583 dmas = <&audma0 0x33>, <&audma1 0x34>; 1584 dma-names = "rx", "tx"; 1585 }; 1586 ssiu50: ssiu-40 { 1587 dmas = <&audma0 0x73>, <&audma1 0x74>; 1588 dma-names = "rx", "tx"; 1589 }; 1590 ssiu60: ssiu-41 { 1591 dmas = <&audma0 0x75>, <&audma1 0x76>; 1592 dma-names = "rx", "tx"; 1593 }; 1594 ssiu70: ssiu-42 { 1595 dmas = <&audma0 0x79>, <&audma1 0x7a>; 1596 dma-names = "rx", "tx"; 1597 }; 1598 ssiu80: ssiu-43 { 1599 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 1600 dma-names = "rx", "tx"; 1601 }; 1602 ssiu90: ssiu-44 { 1603 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 1604 dma-names = "rx", "tx"; 1605 }; 1606 ssiu91: ssiu-45 { 1607 dmas = <&audma0 0x7F>, <&audma1 0x80>; 1608 dma-names = "rx", "tx"; 1609 }; 1610 ssiu92: ssiu-46 { 1611 dmas = <&audma0 0x81>, <&audma1 0x82>; 1612 dma-names = "rx", "tx"; 1613 }; 1614 ssiu93: ssiu-47 { 1615 dmas = <&audma0 0x83>, <&audma1 0x84>; 1616 dma-names = "rx", "tx"; 1617 }; 1618 ssiu94: ssiu-48 { 1619 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 1620 dma-names = "rx", "tx"; 1621 }; 1622 ssiu95: ssiu-49 { 1623 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 1624 dma-names = "rx", "tx"; 1625 }; 1626 ssiu96: ssiu-50 { 1627 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 1628 dma-names = "rx", "tx"; 1629 }; 1630 ssiu97: ssiu-51 { 1631 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 1632 dma-names = "rx", "tx"; 1633 }; 1634 }; 1635 }; 1636 1637 audma0: dma-controller@ec700000 { 1638 compatible = "renesas,dmac-r8a77961", 1639 "renesas,rcar-dmac"; 1640 reg = <0 0xec700000 0 0x10000>; 1641 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1651 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1652 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1655 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1656 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1657 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1658 interrupt-names = "error", 1659 "ch0", "ch1", "ch2", "ch3", 1660 "ch4", "ch5", "ch6", "ch7", 1661 "ch8", "ch9", "ch10", "ch11", 1662 "ch12", "ch13", "ch14", "ch15"; 1663 clocks = <&cpg CPG_MOD 502>; 1664 clock-names = "fck"; 1665 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1666 resets = <&cpg 502>; 1667 #dma-cells = <1>; 1668 dma-channels = <16>; 1669 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 1670 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 1671 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 1672 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 1673 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 1674 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 1675 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 1676 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 1677 }; 1678 1679 audma1: dma-controller@ec720000 { 1680 compatible = "renesas,dmac-r8a77961", 1681 "renesas,rcar-dmac"; 1682 reg = <0 0xec720000 0 0x10000>; 1683 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 1684 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1685 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1686 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1687 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1688 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1689 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1690 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1691 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1692 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1693 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1694 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 1695 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1696 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 1697 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1698 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 1699 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 1700 interrupt-names = "error", 1701 "ch0", "ch1", "ch2", "ch3", 1702 "ch4", "ch5", "ch6", "ch7", 1703 "ch8", "ch9", "ch10", "ch11", 1704 "ch12", "ch13", "ch14", "ch15"; 1705 clocks = <&cpg CPG_MOD 501>; 1706 clock-names = "fck"; 1707 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1708 resets = <&cpg 501>; 1709 #dma-cells = <1>; 1710 dma-channels = <16>; 1711 iommus = <&ipmmu_mp 16>, <&ipmmu_mp 17>, 1712 <&ipmmu_mp 18>, <&ipmmu_mp 19>, 1713 <&ipmmu_mp 20>, <&ipmmu_mp 21>, 1714 <&ipmmu_mp 22>, <&ipmmu_mp 23>, 1715 <&ipmmu_mp 24>, <&ipmmu_mp 25>, 1716 <&ipmmu_mp 26>, <&ipmmu_mp 27>, 1717 <&ipmmu_mp 28>, <&ipmmu_mp 29>, 1718 <&ipmmu_mp 30>, <&ipmmu_mp 31>; 1719 }; 1720 1721 xhci0: usb@ee000000 { 1722 compatible = "renesas,xhci-r8a77961", 1723 "renesas,rcar-gen3-xhci"; 1724 reg = <0 0xee000000 0 0xc00>; 1725 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1726 clocks = <&cpg CPG_MOD 328>; 1727 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1728 resets = <&cpg 328>; 1729 status = "disabled"; 1730 }; 1731 1732 usb3_peri0: usb@ee020000 { 1733 compatible = "renesas,r8a77961-usb3-peri", 1734 "renesas,rcar-gen3-usb3-peri"; 1735 reg = <0 0xee020000 0 0x400>; 1736 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1737 clocks = <&cpg CPG_MOD 328>; 1738 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1739 resets = <&cpg 328>; 1740 status = "disabled"; 1741 }; 1742 1743 ohci0: usb@ee080000 { 1744 compatible = "generic-ohci"; 1745 reg = <0 0xee080000 0 0x100>; 1746 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1747 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1748 phys = <&usb2_phy0 1>; 1749 phy-names = "usb"; 1750 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1751 resets = <&cpg 703>, <&cpg 704>; 1752 status = "disabled"; 1753 }; 1754 1755 ohci1: usb@ee0a0000 { 1756 compatible = "generic-ohci"; 1757 reg = <0 0xee0a0000 0 0x100>; 1758 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1759 clocks = <&cpg CPG_MOD 702>; 1760 phys = <&usb2_phy1 1>; 1761 phy-names = "usb"; 1762 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1763 resets = <&cpg 702>; 1764 status = "disabled"; 1765 }; 1766 1767 ehci0: usb@ee080100 { 1768 compatible = "generic-ehci"; 1769 reg = <0 0xee080100 0 0x100>; 1770 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1771 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1772 phys = <&usb2_phy0 2>; 1773 phy-names = "usb"; 1774 companion = <&ohci0>; 1775 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1776 resets = <&cpg 703>, <&cpg 704>; 1777 status = "disabled"; 1778 }; 1779 1780 ehci1: usb@ee0a0100 { 1781 compatible = "generic-ehci"; 1782 reg = <0 0xee0a0100 0 0x100>; 1783 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1784 clocks = <&cpg CPG_MOD 702>; 1785 phys = <&usb2_phy1 2>; 1786 phy-names = "usb"; 1787 companion = <&ohci1>; 1788 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1789 resets = <&cpg 702>; 1790 status = "disabled"; 1791 }; 1792 1793 usb2_phy0: usb-phy@ee080200 { 1794 compatible = "renesas,usb2-phy-r8a77961", 1795 "renesas,rcar-gen3-usb2-phy"; 1796 reg = <0 0xee080200 0 0x700>; 1797 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1798 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1799 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1800 resets = <&cpg 703>, <&cpg 704>; 1801 #phy-cells = <1>; 1802 status = "disabled"; 1803 }; 1804 1805 usb2_phy1: usb-phy@ee0a0200 { 1806 compatible = "renesas,usb2-phy-r8a77961", 1807 "renesas,rcar-gen3-usb2-phy"; 1808 reg = <0 0xee0a0200 0 0x700>; 1809 clocks = <&cpg CPG_MOD 702>; 1810 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1811 resets = <&cpg 702>; 1812 #phy-cells = <1>; 1813 status = "disabled"; 1814 }; 1815 1816 sdhi0: mmc@ee100000 { 1817 compatible = "renesas,sdhi-r8a77961", 1818 "renesas,rcar-gen3-sdhi"; 1819 reg = <0 0xee100000 0 0x2000>; 1820 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1821 clocks = <&cpg CPG_MOD 314>; 1822 max-frequency = <200000000>; 1823 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1824 resets = <&cpg 314>; 1825 status = "disabled"; 1826 }; 1827 1828 sdhi1: mmc@ee120000 { 1829 compatible = "renesas,sdhi-r8a77961", 1830 "renesas,rcar-gen3-sdhi"; 1831 reg = <0 0xee120000 0 0x2000>; 1832 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1833 clocks = <&cpg CPG_MOD 313>; 1834 max-frequency = <200000000>; 1835 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1836 resets = <&cpg 313>; 1837 status = "disabled"; 1838 }; 1839 1840 sdhi2: mmc@ee140000 { 1841 compatible = "renesas,sdhi-r8a77961", 1842 "renesas,rcar-gen3-sdhi"; 1843 reg = <0 0xee140000 0 0x2000>; 1844 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 1845 clocks = <&cpg CPG_MOD 312>; 1846 max-frequency = <200000000>; 1847 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1848 resets = <&cpg 312>; 1849 status = "disabled"; 1850 }; 1851 1852 sdhi3: mmc@ee160000 { 1853 compatible = "renesas,sdhi-r8a77961", 1854 "renesas,rcar-gen3-sdhi"; 1855 reg = <0 0xee160000 0 0x2000>; 1856 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1857 clocks = <&cpg CPG_MOD 311>; 1858 max-frequency = <200000000>; 1859 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1860 resets = <&cpg 311>; 1861 status = "disabled"; 1862 }; 1863 1864 gic: interrupt-controller@f1010000 { 1865 compatible = "arm,gic-400"; 1866 #interrupt-cells = <3>; 1867 #address-cells = <0>; 1868 interrupt-controller; 1869 reg = <0x0 0xf1010000 0 0x1000>, 1870 <0x0 0xf1020000 0 0x20000>, 1871 <0x0 0xf1040000 0 0x20000>, 1872 <0x0 0xf1060000 0 0x20000>; 1873 interrupts = <GIC_PPI 9 1874 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 1875 clocks = <&cpg CPG_MOD 408>; 1876 clock-names = "clk"; 1877 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1878 resets = <&cpg 408>; 1879 }; 1880 1881 pciec0: pcie@fe000000 { 1882 compatible = "renesas,pcie-r8a77961", 1883 "renesas,pcie-rcar-gen3"; 1884 reg = <0 0xfe000000 0 0x80000>; 1885 #address-cells = <3>; 1886 #size-cells = <2>; 1887 bus-range = <0x00 0xff>; 1888 device_type = "pci"; 1889 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 1890 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 1891 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 1892 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 1893 /* Map all possible DDR as inbound ranges */ 1894 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 1895 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1897 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1898 #interrupt-cells = <1>; 1899 interrupt-map-mask = <0 0 0 0>; 1900 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1901 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1902 clock-names = "pcie", "pcie_bus"; 1903 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1904 resets = <&cpg 319>; 1905 status = "disabled"; 1906 }; 1907 1908 pciec1: pcie@ee800000 { 1909 compatible = "renesas,pcie-r8a77961", 1910 "renesas,pcie-rcar-gen3"; 1911 reg = <0 0xee800000 0 0x80000>; 1912 #address-cells = <3>; 1913 #size-cells = <2>; 1914 bus-range = <0x00 0xff>; 1915 device_type = "pci"; 1916 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, 1917 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, 1918 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, 1919 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 1920 /* Map all possible DDR as inbound ranges */ 1921 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; 1922 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1923 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1924 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1925 #interrupt-cells = <1>; 1926 interrupt-map-mask = <0 0 0 0>; 1927 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1928 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 1929 clock-names = "pcie", "pcie_bus"; 1930 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1931 resets = <&cpg 318>; 1932 status = "disabled"; 1933 }; 1934 1935 fcpf0: fcp@fe950000 { 1936 compatible = "renesas,fcpf"; 1937 reg = <0 0xfe950000 0 0x200>; 1938 clocks = <&cpg CPG_MOD 615>; 1939 power-domains = <&sysc R8A77961_PD_A3VC>; 1940 resets = <&cpg 615>; 1941 }; 1942 1943 fcpvb0: fcp@fe96f000 { 1944 compatible = "renesas,fcpv"; 1945 reg = <0 0xfe96f000 0 0x200>; 1946 clocks = <&cpg CPG_MOD 607>; 1947 power-domains = <&sysc R8A77961_PD_A3VC>; 1948 resets = <&cpg 607>; 1949 }; 1950 1951 fcpvi0: fcp@fe9af000 { 1952 compatible = "renesas,fcpv"; 1953 reg = <0 0xfe9af000 0 0x200>; 1954 clocks = <&cpg CPG_MOD 611>; 1955 power-domains = <&sysc R8A77961_PD_A3VC>; 1956 resets = <&cpg 611>; 1957 iommus = <&ipmmu_vc0 19>; 1958 }; 1959 1960 fcpvd0: fcp@fea27000 { 1961 compatible = "renesas,fcpv"; 1962 reg = <0 0xfea27000 0 0x200>; 1963 clocks = <&cpg CPG_MOD 603>; 1964 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1965 resets = <&cpg 603>; 1966 iommus = <&ipmmu_vi0 8>; 1967 }; 1968 1969 fcpvd1: fcp@fea2f000 { 1970 compatible = "renesas,fcpv"; 1971 reg = <0 0xfea2f000 0 0x200>; 1972 clocks = <&cpg CPG_MOD 602>; 1973 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1974 resets = <&cpg 602>; 1975 iommus = <&ipmmu_vi0 9>; 1976 }; 1977 1978 fcpvd2: fcp@fea37000 { 1979 compatible = "renesas,fcpv"; 1980 reg = <0 0xfea37000 0 0x200>; 1981 clocks = <&cpg CPG_MOD 601>; 1982 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 1983 resets = <&cpg 601>; 1984 iommus = <&ipmmu_vi0 10>; 1985 }; 1986 1987 vspb: vsp@fe960000 { 1988 compatible = "renesas,vsp2"; 1989 reg = <0 0xfe960000 0 0x8000>; 1990 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1991 clocks = <&cpg CPG_MOD 626>; 1992 power-domains = <&sysc R8A77961_PD_A3VC>; 1993 resets = <&cpg 626>; 1994 1995 renesas,fcp = <&fcpvb0>; 1996 }; 1997 1998 vspd0: vsp@fea20000 { 1999 compatible = "renesas,vsp2"; 2000 reg = <0 0xfea20000 0 0x5000>; 2001 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2002 clocks = <&cpg CPG_MOD 623>; 2003 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2004 resets = <&cpg 623>; 2005 2006 renesas,fcp = <&fcpvd0>; 2007 }; 2008 2009 vspd1: vsp@fea28000 { 2010 compatible = "renesas,vsp2"; 2011 reg = <0 0xfea28000 0 0x5000>; 2012 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2013 clocks = <&cpg CPG_MOD 622>; 2014 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2015 resets = <&cpg 622>; 2016 2017 renesas,fcp = <&fcpvd1>; 2018 }; 2019 2020 vspd2: vsp@fea30000 { 2021 compatible = "renesas,vsp2"; 2022 reg = <0 0xfea30000 0 0x5000>; 2023 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 2024 clocks = <&cpg CPG_MOD 621>; 2025 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2026 resets = <&cpg 621>; 2027 2028 renesas,fcp = <&fcpvd2>; 2029 }; 2030 2031 vspi0: vsp@fe9a0000 { 2032 compatible = "renesas,vsp2"; 2033 reg = <0 0xfe9a0000 0 0x8000>; 2034 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2035 clocks = <&cpg CPG_MOD 631>; 2036 power-domains = <&sysc R8A77961_PD_A3VC>; 2037 resets = <&cpg 631>; 2038 2039 renesas,fcp = <&fcpvi0>; 2040 }; 2041 2042 csi20: csi2@fea80000 { 2043 reg = <0 0xfea80000 0 0x10000>; 2044 /* placeholder */ 2045 2046 ports { 2047 #address-cells = <1>; 2048 #size-cells = <0>; 2049 2050 port@1 { 2051 #address-cells = <1>; 2052 #size-cells = <0>; 2053 reg = <1>; 2054 }; 2055 }; 2056 }; 2057 2058 csi40: csi2@feaa0000 { 2059 reg = <0 0xfeaa0000 0 0x10000>; 2060 /* placeholder */ 2061 2062 ports { 2063 #address-cells = <1>; 2064 #size-cells = <0>; 2065 2066 port@1 { 2067 #address-cells = <1>; 2068 #size-cells = <0>; 2069 2070 reg = <1>; 2071 }; 2072 }; 2073 }; 2074 2075 hdmi0: hdmi@fead0000 { 2076 compatible = "renesas,r8a77961-hdmi", "renesas,rcar-gen3-hdmi"; 2077 reg = <0 0xfead0000 0 0x10000>; 2078 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 2079 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A77961_CLK_HDMI>; 2080 clock-names = "iahb", "isfr"; 2081 power-domains = <&sysc R8A77961_PD_ALWAYS_ON>; 2082 resets = <&cpg 729>; 2083 status = "disabled"; 2084 2085 ports { 2086 #address-cells = <1>; 2087 #size-cells = <0>; 2088 port@0 { 2089 reg = <0>; 2090 dw_hdmi0_in: endpoint { 2091 remote-endpoint = <&du_out_hdmi0>; 2092 }; 2093 }; 2094 port@1 { 2095 reg = <1>; 2096 }; 2097 port@2 { 2098 /* HDMI sound */ 2099 reg = <2>; 2100 }; 2101 }; 2102 }; 2103 2104 du: display@feb00000 { 2105 compatible = "renesas,du-r8a77961"; 2106 reg = <0 0xfeb00000 0 0x70000>; 2107 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 2110 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, 2111 <&cpg CPG_MOD 722>; 2112 clock-names = "du.0", "du.1", "du.2"; 2113 resets = <&cpg 724>, <&cpg 722>; 2114 reset-names = "du.0", "du.2"; 2115 2116 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>; 2117 status = "disabled"; 2118 2119 ports { 2120 #address-cells = <1>; 2121 #size-cells = <0>; 2122 2123 port@0 { 2124 reg = <0>; 2125 du_out_rgb: endpoint { 2126 }; 2127 }; 2128 port@1 { 2129 reg = <1>; 2130 du_out_hdmi0: endpoint { 2131 remote-endpoint = <&dw_hdmi0_in>; 2132 }; 2133 }; 2134 port@2 { 2135 reg = <2>; 2136 du_out_lvds0: endpoint { 2137 }; 2138 }; 2139 }; 2140 }; 2141 2142 prr: chipid@fff00044 { 2143 compatible = "renesas,prr"; 2144 reg = <0 0xfff00044 0 4>; 2145 }; 2146 }; 2147 2148 thermal-zones { 2149 sensor_thermal1: sensor-thermal1 { 2150 polling-delay-passive = <250>; 2151 polling-delay = <1000>; 2152 thermal-sensors = <&tsc 0>; 2153 sustainable-power = <3874>; 2154 2155 trips { 2156 sensor1_crit: sensor1-crit { 2157 temperature = <120000>; 2158 hysteresis = <1000>; 2159 type = "critical"; 2160 }; 2161 }; 2162 }; 2163 2164 sensor_thermal2: sensor-thermal2 { 2165 polling-delay-passive = <250>; 2166 polling-delay = <1000>; 2167 thermal-sensors = <&tsc 1>; 2168 sustainable-power = <3874>; 2169 2170 trips { 2171 sensor2_crit: sensor2-crit { 2172 temperature = <120000>; 2173 hysteresis = <1000>; 2174 type = "critical"; 2175 }; 2176 }; 2177 }; 2178 2179 sensor_thermal3: sensor-thermal3 { 2180 polling-delay-passive = <250>; 2181 polling-delay = <1000>; 2182 thermal-sensors = <&tsc 2>; 2183 sustainable-power = <3874>; 2184 2185 cooling-maps { 2186 map0 { 2187 trip = <&target>; 2188 cooling-device = <&a57_0 2 4>; 2189 contribution = <1024>; 2190 }; 2191 map1 { 2192 trip = <&target>; 2193 cooling-device = <&a53_0 0 2>; 2194 contribution = <1024>; 2195 }; 2196 }; 2197 trips { 2198 target: trip-point1 { 2199 temperature = <100000>; 2200 hysteresis = <1000>; 2201 type = "passive"; 2202 }; 2203 2204 sensor3_crit: sensor3-crit { 2205 temperature = <120000>; 2206 hysteresis = <1000>; 2207 type = "critical"; 2208 }; 2209 }; 2210 }; 2211 }; 2212 2213 timer { 2214 compatible = "arm,armv8-timer"; 2215 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2216 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2217 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 2218 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 2219 }; 2220 2221 /* External USB clocks - can be overridden by the board */ 2222 usb3s0_clk: usb3s0 { 2223 compatible = "fixed-clock"; 2224 #clock-cells = <0>; 2225 clock-frequency = <0>; 2226 }; 2227 2228 usb_extal_clk: usb_extal { 2229 compatible = "fixed-clock"; 2230 #clock-cells = <0>; 2231 clock-frequency = <0>; 2232 }; 2233}; 2234