1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car H3 (R8A77951) SoC 4 * 5 * Copyright (C) 2015 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a7795-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a7795-sysc.h> 11 12#define CPG_AUDIO_CLK_I R8A7795_CLK_S0D4 13 14#define SOC_HAS_HDMI1 15#define SOC_HAS_SATA 16#define SOC_HAS_USB2_CH2 17#define SOC_HAS_USB2_CH3 18 19/ { 20 compatible = "renesas,r8a7795"; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { 25 i2c0 = &i2c0; 26 i2c1 = &i2c1; 27 i2c2 = &i2c2; 28 i2c3 = &i2c3; 29 i2c4 = &i2c4; 30 i2c5 = &i2c5; 31 i2c6 = &i2c6; 32 i2c7 = &i2c_dvfs; 33 }; 34 35 /* 36 * The external audio clocks are configured as 0 Hz fixed frequency 37 * clocks by default. 38 * Boards that provide audio clocks should override them. 39 */ 40 audio_clk_a: audio_clk_a { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <0>; 44 }; 45 46 audio_clk_b: audio_clk_b { 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 clock-frequency = <0>; 50 }; 51 52 audio_clk_c: audio_clk_c { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <0>; 56 }; 57 58 /* External CAN clock - to be overridden by boards that provide it */ 59 can_clk: can { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <0>; 63 }; 64 65 cluster0_opp: opp-table-0 { 66 compatible = "operating-points-v2"; 67 opp-shared; 68 69 opp-500000000 { 70 opp-hz = /bits/ 64 <500000000>; 71 opp-microvolt = <830000>; 72 clock-latency-ns = <300000>; 73 }; 74 opp-1000000000 { 75 opp-hz = /bits/ 64 <1000000000>; 76 opp-microvolt = <830000>; 77 clock-latency-ns = <300000>; 78 }; 79 opp-1500000000 { 80 opp-hz = /bits/ 64 <1500000000>; 81 opp-microvolt = <830000>; 82 clock-latency-ns = <300000>; 83 opp-suspend; 84 }; 85 opp-1600000000 { 86 opp-hz = /bits/ 64 <1600000000>; 87 opp-microvolt = <900000>; 88 clock-latency-ns = <300000>; 89 turbo-mode; 90 }; 91 opp-1700000000 { 92 opp-hz = /bits/ 64 <1700000000>; 93 opp-microvolt = <960000>; 94 clock-latency-ns = <300000>; 95 turbo-mode; 96 }; 97 }; 98 99 cluster1_opp: opp-table-1 { 100 compatible = "operating-points-v2"; 101 opp-shared; 102 103 opp-800000000 { 104 opp-hz = /bits/ 64 <800000000>; 105 opp-microvolt = <820000>; 106 clock-latency-ns = <300000>; 107 }; 108 opp-1000000000 { 109 opp-hz = /bits/ 64 <1000000000>; 110 opp-microvolt = <820000>; 111 clock-latency-ns = <300000>; 112 }; 113 opp-1200000000 { 114 opp-hz = /bits/ 64 <1200000000>; 115 opp-microvolt = <820000>; 116 clock-latency-ns = <300000>; 117 }; 118 }; 119 120 cpus { 121 #address-cells = <1>; 122 #size-cells = <0>; 123 124 cpu-map { 125 cluster0 { 126 core0 { 127 cpu = <&a57_0>; 128 }; 129 core1 { 130 cpu = <&a57_1>; 131 }; 132 core2 { 133 cpu = <&a57_2>; 134 }; 135 core3 { 136 cpu = <&a57_3>; 137 }; 138 }; 139 140 cluster1 { 141 core0 { 142 cpu = <&a53_0>; 143 }; 144 core1 { 145 cpu = <&a53_1>; 146 }; 147 core2 { 148 cpu = <&a53_2>; 149 }; 150 core3 { 151 cpu = <&a53_3>; 152 }; 153 }; 154 }; 155 156 a57_0: cpu@0 { 157 compatible = "arm,cortex-a57"; 158 reg = <0x0>; 159 device_type = "cpu"; 160 power-domains = <&sysc R8A7795_PD_CA57_CPU0>; 161 next-level-cache = <&L2_CA57>; 162 enable-method = "psci"; 163 cpu-idle-states = <&CPU_SLEEP_0>; 164 dynamic-power-coefficient = <854>; 165 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; 166 operating-points-v2 = <&cluster0_opp>; 167 capacity-dmips-mhz = <1024>; 168 #cooling-cells = <2>; 169 }; 170 171 a57_1: cpu@1 { 172 compatible = "arm,cortex-a57"; 173 reg = <0x1>; 174 device_type = "cpu"; 175 power-domains = <&sysc R8A7795_PD_CA57_CPU1>; 176 next-level-cache = <&L2_CA57>; 177 enable-method = "psci"; 178 cpu-idle-states = <&CPU_SLEEP_0>; 179 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; 180 operating-points-v2 = <&cluster0_opp>; 181 capacity-dmips-mhz = <1024>; 182 #cooling-cells = <2>; 183 }; 184 185 a57_2: cpu@2 { 186 compatible = "arm,cortex-a57"; 187 reg = <0x2>; 188 device_type = "cpu"; 189 power-domains = <&sysc R8A7795_PD_CA57_CPU2>; 190 next-level-cache = <&L2_CA57>; 191 enable-method = "psci"; 192 cpu-idle-states = <&CPU_SLEEP_0>; 193 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; 194 operating-points-v2 = <&cluster0_opp>; 195 capacity-dmips-mhz = <1024>; 196 #cooling-cells = <2>; 197 }; 198 199 a57_3: cpu@3 { 200 compatible = "arm,cortex-a57"; 201 reg = <0x3>; 202 device_type = "cpu"; 203 power-domains = <&sysc R8A7795_PD_CA57_CPU3>; 204 next-level-cache = <&L2_CA57>; 205 enable-method = "psci"; 206 cpu-idle-states = <&CPU_SLEEP_0>; 207 clocks = <&cpg CPG_CORE R8A7795_CLK_Z>; 208 operating-points-v2 = <&cluster0_opp>; 209 capacity-dmips-mhz = <1024>; 210 #cooling-cells = <2>; 211 }; 212 213 a53_0: cpu@100 { 214 compatible = "arm,cortex-a53"; 215 reg = <0x100>; 216 device_type = "cpu"; 217 power-domains = <&sysc R8A7795_PD_CA53_CPU0>; 218 next-level-cache = <&L2_CA53>; 219 enable-method = "psci"; 220 cpu-idle-states = <&CPU_SLEEP_1>; 221 #cooling-cells = <2>; 222 dynamic-power-coefficient = <277>; 223 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; 224 operating-points-v2 = <&cluster1_opp>; 225 capacity-dmips-mhz = <535>; 226 }; 227 228 a53_1: cpu@101 { 229 compatible = "arm,cortex-a53"; 230 reg = <0x101>; 231 device_type = "cpu"; 232 power-domains = <&sysc R8A7795_PD_CA53_CPU1>; 233 next-level-cache = <&L2_CA53>; 234 enable-method = "psci"; 235 cpu-idle-states = <&CPU_SLEEP_1>; 236 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; 237 operating-points-v2 = <&cluster1_opp>; 238 capacity-dmips-mhz = <535>; 239 }; 240 241 a53_2: cpu@102 { 242 compatible = "arm,cortex-a53"; 243 reg = <0x102>; 244 device_type = "cpu"; 245 power-domains = <&sysc R8A7795_PD_CA53_CPU2>; 246 next-level-cache = <&L2_CA53>; 247 enable-method = "psci"; 248 cpu-idle-states = <&CPU_SLEEP_1>; 249 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; 250 operating-points-v2 = <&cluster1_opp>; 251 capacity-dmips-mhz = <535>; 252 }; 253 254 a53_3: cpu@103 { 255 compatible = "arm,cortex-a53"; 256 reg = <0x103>; 257 device_type = "cpu"; 258 power-domains = <&sysc R8A7795_PD_CA53_CPU3>; 259 next-level-cache = <&L2_CA53>; 260 enable-method = "psci"; 261 cpu-idle-states = <&CPU_SLEEP_1>; 262 clocks = <&cpg CPG_CORE R8A7795_CLK_Z2>; 263 operating-points-v2 = <&cluster1_opp>; 264 capacity-dmips-mhz = <535>; 265 }; 266 267 L2_CA57: cache-controller-0 { 268 compatible = "cache"; 269 power-domains = <&sysc R8A7795_PD_CA57_SCU>; 270 cache-unified; 271 cache-level = <2>; 272 }; 273 274 L2_CA53: cache-controller-1 { 275 compatible = "cache"; 276 power-domains = <&sysc R8A7795_PD_CA53_SCU>; 277 cache-unified; 278 cache-level = <2>; 279 }; 280 281 idle-states { 282 entry-method = "psci"; 283 284 CPU_SLEEP_0: cpu-sleep-0 { 285 compatible = "arm,idle-state"; 286 arm,psci-suspend-param = <0x0010000>; 287 local-timer-stop; 288 entry-latency-us = <400>; 289 exit-latency-us = <500>; 290 min-residency-us = <4000>; 291 }; 292 293 CPU_SLEEP_1: cpu-sleep-1 { 294 compatible = "arm,idle-state"; 295 arm,psci-suspend-param = <0x0010000>; 296 local-timer-stop; 297 entry-latency-us = <700>; 298 exit-latency-us = <700>; 299 min-residency-us = <5000>; 300 }; 301 }; 302 }; 303 304 extal_clk: extal { 305 compatible = "fixed-clock"; 306 #clock-cells = <0>; 307 /* This value must be overridden by the board */ 308 clock-frequency = <0>; 309 }; 310 311 extalr_clk: extalr { 312 compatible = "fixed-clock"; 313 #clock-cells = <0>; 314 /* This value must be overridden by the board */ 315 clock-frequency = <0>; 316 }; 317 318 /* External PCIe clock - can be overridden by the board */ 319 pcie_bus_clk: pcie_bus { 320 compatible = "fixed-clock"; 321 #clock-cells = <0>; 322 clock-frequency = <0>; 323 }; 324 325 pmu_a53 { 326 compatible = "arm,cortex-a53-pmu"; 327 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 328 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 329 <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 330 <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 331 interrupt-affinity = <&a53_0>, 332 <&a53_1>, 333 <&a53_2>, 334 <&a53_3>; 335 }; 336 337 pmu_a57 { 338 compatible = "arm,cortex-a57-pmu"; 339 interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 340 <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 341 <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 342 <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 343 interrupt-affinity = <&a57_0>, 344 <&a57_1>, 345 <&a57_2>, 346 <&a57_3>; 347 }; 348 349 psci { 350 compatible = "arm,psci-1.0", "arm,psci-0.2"; 351 method = "smc"; 352 }; 353 354 /* External SCIF clock - to be overridden by boards that provide it */ 355 scif_clk: scif { 356 compatible = "fixed-clock"; 357 #clock-cells = <0>; 358 clock-frequency = <0>; 359 }; 360 361 soc: soc { 362 compatible = "simple-bus"; 363 interrupt-parent = <&gic>; 364 365 #address-cells = <2>; 366 #size-cells = <2>; 367 ranges; 368 369 rwdt: watchdog@e6020000 { 370 compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; 371 reg = <0 0xe6020000 0 0x0c>; 372 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 373 clocks = <&cpg CPG_MOD 402>; 374 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 375 resets = <&cpg 402>; 376 status = "disabled"; 377 }; 378 379 gpio0: gpio@e6050000 { 380 compatible = "renesas,gpio-r8a7795", 381 "renesas,rcar-gen3-gpio"; 382 reg = <0 0xe6050000 0 0x50>; 383 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 384 #gpio-cells = <2>; 385 gpio-controller; 386 gpio-ranges = <&pfc 0 0 16>; 387 #interrupt-cells = <2>; 388 interrupt-controller; 389 clocks = <&cpg CPG_MOD 912>; 390 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 391 resets = <&cpg 912>; 392 }; 393 394 gpio1: gpio@e6051000 { 395 compatible = "renesas,gpio-r8a7795", 396 "renesas,rcar-gen3-gpio"; 397 reg = <0 0xe6051000 0 0x50>; 398 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 399 #gpio-cells = <2>; 400 gpio-controller; 401 gpio-ranges = <&pfc 0 32 29>; 402 #interrupt-cells = <2>; 403 interrupt-controller; 404 clocks = <&cpg CPG_MOD 911>; 405 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 406 resets = <&cpg 911>; 407 }; 408 409 gpio2: gpio@e6052000 { 410 compatible = "renesas,gpio-r8a7795", 411 "renesas,rcar-gen3-gpio"; 412 reg = <0 0xe6052000 0 0x50>; 413 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 414 #gpio-cells = <2>; 415 gpio-controller; 416 gpio-ranges = <&pfc 0 64 15>; 417 #interrupt-cells = <2>; 418 interrupt-controller; 419 clocks = <&cpg CPG_MOD 910>; 420 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 421 resets = <&cpg 910>; 422 }; 423 424 gpio3: gpio@e6053000 { 425 compatible = "renesas,gpio-r8a7795", 426 "renesas,rcar-gen3-gpio"; 427 reg = <0 0xe6053000 0 0x50>; 428 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 429 #gpio-cells = <2>; 430 gpio-controller; 431 gpio-ranges = <&pfc 0 96 16>; 432 #interrupt-cells = <2>; 433 interrupt-controller; 434 clocks = <&cpg CPG_MOD 909>; 435 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 436 resets = <&cpg 909>; 437 }; 438 439 gpio4: gpio@e6054000 { 440 compatible = "renesas,gpio-r8a7795", 441 "renesas,rcar-gen3-gpio"; 442 reg = <0 0xe6054000 0 0x50>; 443 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 444 #gpio-cells = <2>; 445 gpio-controller; 446 gpio-ranges = <&pfc 0 128 18>; 447 #interrupt-cells = <2>; 448 interrupt-controller; 449 clocks = <&cpg CPG_MOD 908>; 450 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 451 resets = <&cpg 908>; 452 }; 453 454 gpio5: gpio@e6055000 { 455 compatible = "renesas,gpio-r8a7795", 456 "renesas,rcar-gen3-gpio"; 457 reg = <0 0xe6055000 0 0x50>; 458 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 459 #gpio-cells = <2>; 460 gpio-controller; 461 gpio-ranges = <&pfc 0 160 26>; 462 #interrupt-cells = <2>; 463 interrupt-controller; 464 clocks = <&cpg CPG_MOD 907>; 465 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 466 resets = <&cpg 907>; 467 }; 468 469 gpio6: gpio@e6055400 { 470 compatible = "renesas,gpio-r8a7795", 471 "renesas,rcar-gen3-gpio"; 472 reg = <0 0xe6055400 0 0x50>; 473 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 474 #gpio-cells = <2>; 475 gpio-controller; 476 gpio-ranges = <&pfc 0 192 32>; 477 #interrupt-cells = <2>; 478 interrupt-controller; 479 clocks = <&cpg CPG_MOD 906>; 480 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 481 resets = <&cpg 906>; 482 }; 483 484 gpio7: gpio@e6055800 { 485 compatible = "renesas,gpio-r8a7795", 486 "renesas,rcar-gen3-gpio"; 487 reg = <0 0xe6055800 0 0x50>; 488 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 489 #gpio-cells = <2>; 490 gpio-controller; 491 gpio-ranges = <&pfc 0 224 4>; 492 #interrupt-cells = <2>; 493 interrupt-controller; 494 clocks = <&cpg CPG_MOD 905>; 495 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 496 resets = <&cpg 905>; 497 }; 498 499 pfc: pinctrl@e6060000 { 500 compatible = "renesas,pfc-r8a7795"; 501 reg = <0 0xe6060000 0 0x50c>; 502 }; 503 504 cmt0: timer@e60f0000 { 505 compatible = "renesas,r8a7795-cmt0", 506 "renesas,rcar-gen3-cmt0"; 507 reg = <0 0xe60f0000 0 0x1004>; 508 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&cpg CPG_MOD 303>; 511 clock-names = "fck"; 512 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 513 resets = <&cpg 303>; 514 status = "disabled"; 515 }; 516 517 cmt1: timer@e6130000 { 518 compatible = "renesas,r8a7795-cmt1", 519 "renesas,rcar-gen3-cmt1"; 520 reg = <0 0xe6130000 0 0x1004>; 521 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&cpg CPG_MOD 302>; 530 clock-names = "fck"; 531 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 532 resets = <&cpg 302>; 533 status = "disabled"; 534 }; 535 536 cmt2: timer@e6140000 { 537 compatible = "renesas,r8a7795-cmt1", 538 "renesas,rcar-gen3-cmt1"; 539 reg = <0 0xe6140000 0 0x1004>; 540 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&cpg CPG_MOD 301>; 549 clock-names = "fck"; 550 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 551 resets = <&cpg 301>; 552 status = "disabled"; 553 }; 554 555 cmt3: timer@e6148000 { 556 compatible = "renesas,r8a7795-cmt1", 557 "renesas,rcar-gen3-cmt1"; 558 reg = <0 0xe6148000 0 0x1004>; 559 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&cpg CPG_MOD 300>; 568 clock-names = "fck"; 569 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 570 resets = <&cpg 300>; 571 status = "disabled"; 572 }; 573 574 cpg: clock-controller@e6150000 { 575 compatible = "renesas,r8a7795-cpg-mssr"; 576 reg = <0 0xe6150000 0 0x1000>; 577 clocks = <&extal_clk>, <&extalr_clk>; 578 clock-names = "extal", "extalr"; 579 #clock-cells = <2>; 580 #power-domain-cells = <0>; 581 #reset-cells = <1>; 582 }; 583 584 rst: reset-controller@e6160000 { 585 compatible = "renesas,r8a7795-rst"; 586 reg = <0 0xe6160000 0 0x0200>; 587 }; 588 589 sysc: system-controller@e6180000 { 590 compatible = "renesas,r8a7795-sysc"; 591 reg = <0 0xe6180000 0 0x0400>; 592 #power-domain-cells = <1>; 593 }; 594 595 tsc: thermal@e6198000 { 596 compatible = "renesas,r8a7795-thermal"; 597 reg = <0 0xe6198000 0 0x100>, 598 <0 0xe61a0000 0 0x100>, 599 <0 0xe61a8000 0 0x100>; 600 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 603 clocks = <&cpg CPG_MOD 522>; 604 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 605 resets = <&cpg 522>; 606 #thermal-sensor-cells = <1>; 607 }; 608 609 intc_ex: interrupt-controller@e61c0000 { 610 compatible = "renesas,intc-ex-r8a7795", "renesas,irqc"; 611 #interrupt-cells = <2>; 612 interrupt-controller; 613 reg = <0 0xe61c0000 0 0x200>; 614 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&cpg CPG_MOD 407>; 621 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 622 resets = <&cpg 407>; 623 }; 624 625 tmu0: timer@e61e0000 { 626 compatible = "renesas,tmu-r8a7795", "renesas,tmu"; 627 reg = <0 0xe61e0000 0 0x30>; 628 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 629 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 630 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&cpg CPG_MOD 125>; 632 clock-names = "fck"; 633 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 634 resets = <&cpg 125>; 635 status = "disabled"; 636 }; 637 638 tmu1: timer@e6fc0000 { 639 compatible = "renesas,tmu-r8a7795", "renesas,tmu"; 640 reg = <0 0xe6fc0000 0 0x30>; 641 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 644 clocks = <&cpg CPG_MOD 124>; 645 clock-names = "fck"; 646 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 647 resets = <&cpg 124>; 648 status = "disabled"; 649 }; 650 651 tmu2: timer@e6fd0000 { 652 compatible = "renesas,tmu-r8a7795", "renesas,tmu"; 653 reg = <0 0xe6fd0000 0 0x30>; 654 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&cpg CPG_MOD 123>; 658 clock-names = "fck"; 659 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 660 resets = <&cpg 123>; 661 status = "disabled"; 662 }; 663 664 tmu3: timer@e6fe0000 { 665 compatible = "renesas,tmu-r8a7795", "renesas,tmu"; 666 reg = <0 0xe6fe0000 0 0x30>; 667 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 670 clocks = <&cpg CPG_MOD 122>; 671 clock-names = "fck"; 672 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 673 resets = <&cpg 122>; 674 status = "disabled"; 675 }; 676 677 tmu4: timer@ffc00000 { 678 compatible = "renesas,tmu-r8a7795", "renesas,tmu"; 679 reg = <0 0xffc00000 0 0x30>; 680 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&cpg CPG_MOD 121>; 684 clock-names = "fck"; 685 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 686 resets = <&cpg 121>; 687 status = "disabled"; 688 }; 689 690 i2c0: i2c@e6500000 { 691 #address-cells = <1>; 692 #size-cells = <0>; 693 compatible = "renesas,i2c-r8a7795", 694 "renesas,rcar-gen3-i2c"; 695 reg = <0 0xe6500000 0 0x40>; 696 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&cpg CPG_MOD 931>; 698 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 699 resets = <&cpg 931>; 700 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 701 <&dmac2 0x91>, <&dmac2 0x90>; 702 dma-names = "tx", "rx", "tx", "rx"; 703 i2c-scl-internal-delay-ns = <110>; 704 status = "disabled"; 705 }; 706 707 i2c1: i2c@e6508000 { 708 #address-cells = <1>; 709 #size-cells = <0>; 710 compatible = "renesas,i2c-r8a7795", 711 "renesas,rcar-gen3-i2c"; 712 reg = <0 0xe6508000 0 0x40>; 713 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&cpg CPG_MOD 930>; 715 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 716 resets = <&cpg 930>; 717 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 718 <&dmac2 0x93>, <&dmac2 0x92>; 719 dma-names = "tx", "rx", "tx", "rx"; 720 i2c-scl-internal-delay-ns = <6>; 721 status = "disabled"; 722 }; 723 724 i2c2: i2c@e6510000 { 725 #address-cells = <1>; 726 #size-cells = <0>; 727 compatible = "renesas,i2c-r8a7795", 728 "renesas,rcar-gen3-i2c"; 729 reg = <0 0xe6510000 0 0x40>; 730 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&cpg CPG_MOD 929>; 732 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 733 resets = <&cpg 929>; 734 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 735 <&dmac2 0x95>, <&dmac2 0x94>; 736 dma-names = "tx", "rx", "tx", "rx"; 737 i2c-scl-internal-delay-ns = <6>; 738 status = "disabled"; 739 }; 740 741 i2c3: i2c@e66d0000 { 742 #address-cells = <1>; 743 #size-cells = <0>; 744 compatible = "renesas,i2c-r8a7795", 745 "renesas,rcar-gen3-i2c"; 746 reg = <0 0xe66d0000 0 0x40>; 747 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&cpg CPG_MOD 928>; 749 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 750 resets = <&cpg 928>; 751 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 752 dma-names = "tx", "rx"; 753 i2c-scl-internal-delay-ns = <110>; 754 status = "disabled"; 755 }; 756 757 i2c4: i2c@e66d8000 { 758 #address-cells = <1>; 759 #size-cells = <0>; 760 compatible = "renesas,i2c-r8a7795", 761 "renesas,rcar-gen3-i2c"; 762 reg = <0 0xe66d8000 0 0x40>; 763 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 764 clocks = <&cpg CPG_MOD 927>; 765 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 766 resets = <&cpg 927>; 767 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 768 dma-names = "tx", "rx"; 769 i2c-scl-internal-delay-ns = <110>; 770 status = "disabled"; 771 }; 772 773 i2c5: i2c@e66e0000 { 774 #address-cells = <1>; 775 #size-cells = <0>; 776 compatible = "renesas,i2c-r8a7795", 777 "renesas,rcar-gen3-i2c"; 778 reg = <0 0xe66e0000 0 0x40>; 779 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 780 clocks = <&cpg CPG_MOD 919>; 781 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 782 resets = <&cpg 919>; 783 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 784 dma-names = "tx", "rx"; 785 i2c-scl-internal-delay-ns = <110>; 786 status = "disabled"; 787 }; 788 789 i2c6: i2c@e66e8000 { 790 #address-cells = <1>; 791 #size-cells = <0>; 792 compatible = "renesas,i2c-r8a7795", 793 "renesas,rcar-gen3-i2c"; 794 reg = <0 0xe66e8000 0 0x40>; 795 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 796 clocks = <&cpg CPG_MOD 918>; 797 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 798 resets = <&cpg 918>; 799 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 800 dma-names = "tx", "rx"; 801 i2c-scl-internal-delay-ns = <6>; 802 status = "disabled"; 803 }; 804 805 i2c_dvfs: i2c@e60b0000 { 806 #address-cells = <1>; 807 #size-cells = <0>; 808 compatible = "renesas,iic-r8a7795", 809 "renesas,rcar-gen3-iic", 810 "renesas,rmobile-iic"; 811 reg = <0 0xe60b0000 0 0x425>; 812 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&cpg CPG_MOD 926>; 814 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 815 resets = <&cpg 926>; 816 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 817 dma-names = "tx", "rx"; 818 status = "disabled"; 819 }; 820 821 hscif0: serial@e6540000 { 822 compatible = "renesas,hscif-r8a7795", 823 "renesas,rcar-gen3-hscif", 824 "renesas,hscif"; 825 reg = <0 0xe6540000 0 96>; 826 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 827 clocks = <&cpg CPG_MOD 520>, 828 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 829 <&scif_clk>; 830 clock-names = "fck", "brg_int", "scif_clk"; 831 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 832 <&dmac2 0x31>, <&dmac2 0x30>; 833 dma-names = "tx", "rx", "tx", "rx"; 834 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 835 resets = <&cpg 520>; 836 status = "disabled"; 837 }; 838 839 hscif1: serial@e6550000 { 840 compatible = "renesas,hscif-r8a7795", 841 "renesas,rcar-gen3-hscif", 842 "renesas,hscif"; 843 reg = <0 0xe6550000 0 96>; 844 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&cpg CPG_MOD 519>, 846 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 847 <&scif_clk>; 848 clock-names = "fck", "brg_int", "scif_clk"; 849 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 850 <&dmac2 0x33>, <&dmac2 0x32>; 851 dma-names = "tx", "rx", "tx", "rx"; 852 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 853 resets = <&cpg 519>; 854 status = "disabled"; 855 }; 856 857 hscif2: serial@e6560000 { 858 compatible = "renesas,hscif-r8a7795", 859 "renesas,rcar-gen3-hscif", 860 "renesas,hscif"; 861 reg = <0 0xe6560000 0 96>; 862 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 863 clocks = <&cpg CPG_MOD 518>, 864 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 865 <&scif_clk>; 866 clock-names = "fck", "brg_int", "scif_clk"; 867 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 868 <&dmac2 0x35>, <&dmac2 0x34>; 869 dma-names = "tx", "rx", "tx", "rx"; 870 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 871 resets = <&cpg 518>; 872 status = "disabled"; 873 }; 874 875 hscif3: serial@e66a0000 { 876 compatible = "renesas,hscif-r8a7795", 877 "renesas,rcar-gen3-hscif", 878 "renesas,hscif"; 879 reg = <0 0xe66a0000 0 96>; 880 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 881 clocks = <&cpg CPG_MOD 517>, 882 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 883 <&scif_clk>; 884 clock-names = "fck", "brg_int", "scif_clk"; 885 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 886 dma-names = "tx", "rx"; 887 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 888 resets = <&cpg 517>; 889 status = "disabled"; 890 }; 891 892 hscif4: serial@e66b0000 { 893 compatible = "renesas,hscif-r8a7795", 894 "renesas,rcar-gen3-hscif", 895 "renesas,hscif"; 896 reg = <0 0xe66b0000 0 96>; 897 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 898 clocks = <&cpg CPG_MOD 516>, 899 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 900 <&scif_clk>; 901 clock-names = "fck", "brg_int", "scif_clk"; 902 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 903 dma-names = "tx", "rx"; 904 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 905 resets = <&cpg 516>; 906 status = "disabled"; 907 }; 908 909 hsusb: usb@e6590000 { 910 compatible = "renesas,usbhs-r8a7795", 911 "renesas,rcar-gen3-usbhs"; 912 reg = <0 0xe6590000 0 0x200>; 913 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 914 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 915 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 916 <&usb_dmac1 0>, <&usb_dmac1 1>; 917 dma-names = "ch0", "ch1", "ch2", "ch3"; 918 renesas,buswait = <11>; 919 phys = <&usb2_phy0 3>; 920 phy-names = "usb"; 921 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 922 resets = <&cpg 704>, <&cpg 703>; 923 status = "disabled"; 924 }; 925 926 hsusb3: usb@e659c000 { 927 compatible = "renesas,usbhs-r8a7795", 928 "renesas,rcar-gen3-usbhs"; 929 reg = <0 0xe659c000 0 0x200>; 930 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 931 clocks = <&cpg CPG_MOD 705>, <&cpg CPG_MOD 700>; 932 dmas = <&usb_dmac2 0>, <&usb_dmac2 1>, 933 <&usb_dmac3 0>, <&usb_dmac3 1>; 934 dma-names = "ch0", "ch1", "ch2", "ch3"; 935 renesas,buswait = <11>; 936 phys = <&usb2_phy3 3>; 937 phy-names = "usb"; 938 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 939 resets = <&cpg 705>, <&cpg 700>; 940 status = "disabled"; 941 }; 942 943 usb_dmac0: dma-controller@e65a0000 { 944 compatible = "renesas,r8a7795-usb-dmac", 945 "renesas,usb-dmac"; 946 reg = <0 0xe65a0000 0 0x100>; 947 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 949 interrupt-names = "ch0", "ch1"; 950 clocks = <&cpg CPG_MOD 330>; 951 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 952 resets = <&cpg 330>; 953 #dma-cells = <1>; 954 dma-channels = <2>; 955 }; 956 957 usb_dmac1: dma-controller@e65b0000 { 958 compatible = "renesas,r8a7795-usb-dmac", 959 "renesas,usb-dmac"; 960 reg = <0 0xe65b0000 0 0x100>; 961 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 963 interrupt-names = "ch0", "ch1"; 964 clocks = <&cpg CPG_MOD 331>; 965 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 966 resets = <&cpg 331>; 967 #dma-cells = <1>; 968 dma-channels = <2>; 969 }; 970 971 usb_dmac2: dma-controller@e6460000 { 972 compatible = "renesas,r8a7795-usb-dmac", 973 "renesas,usb-dmac"; 974 reg = <0 0xe6460000 0 0x100>; 975 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 976 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 977 interrupt-names = "ch0", "ch1"; 978 clocks = <&cpg CPG_MOD 326>; 979 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 980 resets = <&cpg 326>; 981 #dma-cells = <1>; 982 dma-channels = <2>; 983 }; 984 985 usb_dmac3: dma-controller@e6470000 { 986 compatible = "renesas,r8a7795-usb-dmac", 987 "renesas,usb-dmac"; 988 reg = <0 0xe6470000 0 0x100>; 989 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 991 interrupt-names = "ch0", "ch1"; 992 clocks = <&cpg CPG_MOD 329>; 993 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 994 resets = <&cpg 329>; 995 #dma-cells = <1>; 996 dma-channels = <2>; 997 }; 998 999 usb3_phy0: usb-phy@e65ee000 { 1000 compatible = "renesas,r8a7795-usb3-phy", 1001 "renesas,rcar-gen3-usb3-phy"; 1002 reg = <0 0xe65ee000 0 0x90>; 1003 clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, 1004 <&usb_extal_clk>; 1005 clock-names = "usb3-if", "usb3s_clk", "usb_extal"; 1006 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1007 resets = <&cpg 328>; 1008 #phy-cells = <0>; 1009 status = "disabled"; 1010 }; 1011 1012 arm_cc630p: crypto@e6601000 { 1013 compatible = "arm,cryptocell-630p-ree"; 1014 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1015 reg = <0x0 0xe6601000 0 0x1000>; 1016 clocks = <&cpg CPG_MOD 229>; 1017 resets = <&cpg 229>; 1018 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1019 }; 1020 1021 dmac0: dma-controller@e6700000 { 1022 compatible = "renesas,dmac-r8a7795", 1023 "renesas,rcar-dmac"; 1024 reg = <0 0xe6700000 0 0x10000>; 1025 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1037 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1038 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1039 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1040 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1041 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 1042 interrupt-names = "error", 1043 "ch0", "ch1", "ch2", "ch3", 1044 "ch4", "ch5", "ch6", "ch7", 1045 "ch8", "ch9", "ch10", "ch11", 1046 "ch12", "ch13", "ch14", "ch15"; 1047 clocks = <&cpg CPG_MOD 219>; 1048 clock-names = "fck"; 1049 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1050 resets = <&cpg 219>; 1051 #dma-cells = <1>; 1052 dma-channels = <16>; 1053 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 1054 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 1055 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 1056 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 1057 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 1058 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 1059 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 1060 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 1061 }; 1062 1063 dmac1: dma-controller@e7300000 { 1064 compatible = "renesas,dmac-r8a7795", 1065 "renesas,rcar-dmac"; 1066 reg = <0 0xe7300000 0 0x10000>; 1067 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 1075 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 1084 interrupt-names = "error", 1085 "ch0", "ch1", "ch2", "ch3", 1086 "ch4", "ch5", "ch6", "ch7", 1087 "ch8", "ch9", "ch10", "ch11", 1088 "ch12", "ch13", "ch14", "ch15"; 1089 clocks = <&cpg CPG_MOD 218>; 1090 clock-names = "fck"; 1091 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1092 resets = <&cpg 218>; 1093 #dma-cells = <1>; 1094 dma-channels = <16>; 1095 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 1096 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 1097 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 1098 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 1099 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 1100 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 1101 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 1102 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 1103 }; 1104 1105 dmac2: dma-controller@e7310000 { 1106 compatible = "renesas,dmac-r8a7795", 1107 "renesas,rcar-dmac"; 1108 reg = <0 0xe7310000 0 0x10000>; 1109 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 1126 interrupt-names = "error", 1127 "ch0", "ch1", "ch2", "ch3", 1128 "ch4", "ch5", "ch6", "ch7", 1129 "ch8", "ch9", "ch10", "ch11", 1130 "ch12", "ch13", "ch14", "ch15"; 1131 clocks = <&cpg CPG_MOD 217>; 1132 clock-names = "fck"; 1133 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1134 resets = <&cpg 217>; 1135 #dma-cells = <1>; 1136 dma-channels = <16>; 1137 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 1138 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 1139 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 1140 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 1141 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 1142 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 1143 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 1144 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 1145 }; 1146 1147 ipmmu_ds0: iommu@e6740000 { 1148 compatible = "renesas,ipmmu-r8a7795"; 1149 reg = <0 0xe6740000 0 0x1000>; 1150 renesas,ipmmu-main = <&ipmmu_mm 0>; 1151 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1152 #iommu-cells = <1>; 1153 }; 1154 1155 ipmmu_ds1: iommu@e7740000 { 1156 compatible = "renesas,ipmmu-r8a7795"; 1157 reg = <0 0xe7740000 0 0x1000>; 1158 renesas,ipmmu-main = <&ipmmu_mm 1>; 1159 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1160 #iommu-cells = <1>; 1161 }; 1162 1163 ipmmu_hc: iommu@e6570000 { 1164 compatible = "renesas,ipmmu-r8a7795"; 1165 reg = <0 0xe6570000 0 0x1000>; 1166 renesas,ipmmu-main = <&ipmmu_mm 2>; 1167 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1168 #iommu-cells = <1>; 1169 }; 1170 1171 ipmmu_ir: iommu@ff8b0000 { 1172 compatible = "renesas,ipmmu-r8a7795"; 1173 reg = <0 0xff8b0000 0 0x1000>; 1174 renesas,ipmmu-main = <&ipmmu_mm 3>; 1175 power-domains = <&sysc R8A7795_PD_A3IR>; 1176 #iommu-cells = <1>; 1177 }; 1178 1179 ipmmu_mm: iommu@e67b0000 { 1180 compatible = "renesas,ipmmu-r8a7795"; 1181 reg = <0 0xe67b0000 0 0x1000>; 1182 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1184 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1185 #iommu-cells = <1>; 1186 }; 1187 1188 ipmmu_mp0: iommu@ec670000 { 1189 compatible = "renesas,ipmmu-r8a7795"; 1190 reg = <0 0xec670000 0 0x1000>; 1191 renesas,ipmmu-main = <&ipmmu_mm 4>; 1192 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1193 #iommu-cells = <1>; 1194 }; 1195 1196 ipmmu_pv0: iommu@fd800000 { 1197 compatible = "renesas,ipmmu-r8a7795"; 1198 reg = <0 0xfd800000 0 0x1000>; 1199 renesas,ipmmu-main = <&ipmmu_mm 6>; 1200 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1201 #iommu-cells = <1>; 1202 }; 1203 1204 ipmmu_pv1: iommu@fd950000 { 1205 compatible = "renesas,ipmmu-r8a7795"; 1206 reg = <0 0xfd950000 0 0x1000>; 1207 renesas,ipmmu-main = <&ipmmu_mm 7>; 1208 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1209 #iommu-cells = <1>; 1210 }; 1211 1212 ipmmu_pv2: iommu@fd960000 { 1213 compatible = "renesas,ipmmu-r8a7795"; 1214 reg = <0 0xfd960000 0 0x1000>; 1215 renesas,ipmmu-main = <&ipmmu_mm 8>; 1216 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1217 #iommu-cells = <1>; 1218 }; 1219 1220 ipmmu_pv3: iommu@fd970000 { 1221 compatible = "renesas,ipmmu-r8a7795"; 1222 reg = <0 0xfd970000 0 0x1000>; 1223 renesas,ipmmu-main = <&ipmmu_mm 9>; 1224 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1225 #iommu-cells = <1>; 1226 }; 1227 1228 ipmmu_rt: iommu@ffc80000 { 1229 compatible = "renesas,ipmmu-r8a7795"; 1230 reg = <0 0xffc80000 0 0x1000>; 1231 renesas,ipmmu-main = <&ipmmu_mm 10>; 1232 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1233 #iommu-cells = <1>; 1234 }; 1235 1236 ipmmu_vc0: iommu@fe6b0000 { 1237 compatible = "renesas,ipmmu-r8a7795"; 1238 reg = <0 0xfe6b0000 0 0x1000>; 1239 renesas,ipmmu-main = <&ipmmu_mm 12>; 1240 power-domains = <&sysc R8A7795_PD_A3VC>; 1241 #iommu-cells = <1>; 1242 }; 1243 1244 ipmmu_vc1: iommu@fe6f0000 { 1245 compatible = "renesas,ipmmu-r8a7795"; 1246 reg = <0 0xfe6f0000 0 0x1000>; 1247 renesas,ipmmu-main = <&ipmmu_mm 13>; 1248 power-domains = <&sysc R8A7795_PD_A3VC>; 1249 #iommu-cells = <1>; 1250 }; 1251 1252 ipmmu_vi0: iommu@febd0000 { 1253 compatible = "renesas,ipmmu-r8a7795"; 1254 reg = <0 0xfebd0000 0 0x1000>; 1255 renesas,ipmmu-main = <&ipmmu_mm 14>; 1256 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1257 #iommu-cells = <1>; 1258 }; 1259 1260 ipmmu_vi1: iommu@febe0000 { 1261 compatible = "renesas,ipmmu-r8a7795"; 1262 reg = <0 0xfebe0000 0 0x1000>; 1263 renesas,ipmmu-main = <&ipmmu_mm 15>; 1264 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1265 #iommu-cells = <1>; 1266 }; 1267 1268 ipmmu_vp0: iommu@fe990000 { 1269 compatible = "renesas,ipmmu-r8a7795"; 1270 reg = <0 0xfe990000 0 0x1000>; 1271 renesas,ipmmu-main = <&ipmmu_mm 16>; 1272 power-domains = <&sysc R8A7795_PD_A3VP>; 1273 #iommu-cells = <1>; 1274 }; 1275 1276 ipmmu_vp1: iommu@fe980000 { 1277 compatible = "renesas,ipmmu-r8a7795"; 1278 reg = <0 0xfe980000 0 0x1000>; 1279 renesas,ipmmu-main = <&ipmmu_mm 17>; 1280 power-domains = <&sysc R8A7795_PD_A3VP>; 1281 #iommu-cells = <1>; 1282 }; 1283 1284 avb: ethernet@e6800000 { 1285 compatible = "renesas,etheravb-r8a7795", 1286 "renesas,etheravb-rcar-gen3"; 1287 reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; 1288 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1289 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1290 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1291 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1302 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1303 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1304 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1305 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1306 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1307 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 1308 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1309 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 1310 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 1311 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 1312 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1313 interrupt-names = "ch0", "ch1", "ch2", "ch3", 1314 "ch4", "ch5", "ch6", "ch7", 1315 "ch8", "ch9", "ch10", "ch11", 1316 "ch12", "ch13", "ch14", "ch15", 1317 "ch16", "ch17", "ch18", "ch19", 1318 "ch20", "ch21", "ch22", "ch23", 1319 "ch24"; 1320 clocks = <&cpg CPG_MOD 812>; 1321 clock-names = "fck"; 1322 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1323 resets = <&cpg 812>; 1324 phy-mode = "rgmii"; 1325 rx-internal-delay-ps = <0>; 1326 tx-internal-delay-ps = <0>; 1327 iommus = <&ipmmu_ds0 16>; 1328 #address-cells = <1>; 1329 #size-cells = <0>; 1330 status = "disabled"; 1331 }; 1332 1333 can0: can@e6c30000 { 1334 compatible = "renesas,can-r8a7795", 1335 "renesas,rcar-gen3-can"; 1336 reg = <0 0xe6c30000 0 0x1000>; 1337 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1338 clocks = <&cpg CPG_MOD 916>, 1339 <&cpg CPG_CORE R8A7795_CLK_CANFD>, 1340 <&can_clk>; 1341 clock-names = "clkp1", "clkp2", "can_clk"; 1342 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; 1343 assigned-clock-rates = <40000000>; 1344 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1345 resets = <&cpg 916>; 1346 status = "disabled"; 1347 }; 1348 1349 can1: can@e6c38000 { 1350 compatible = "renesas,can-r8a7795", 1351 "renesas,rcar-gen3-can"; 1352 reg = <0 0xe6c38000 0 0x1000>; 1353 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1354 clocks = <&cpg CPG_MOD 915>, 1355 <&cpg CPG_CORE R8A7795_CLK_CANFD>, 1356 <&can_clk>; 1357 clock-names = "clkp1", "clkp2", "can_clk"; 1358 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; 1359 assigned-clock-rates = <40000000>; 1360 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1361 resets = <&cpg 915>; 1362 status = "disabled"; 1363 }; 1364 1365 canfd: can@e66c0000 { 1366 compatible = "renesas,r8a7795-canfd", 1367 "renesas,rcar-gen3-canfd"; 1368 reg = <0 0xe66c0000 0 0x8000>; 1369 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1370 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1371 interrupt-names = "ch_int", "g_int"; 1372 clocks = <&cpg CPG_MOD 914>, 1373 <&cpg CPG_CORE R8A7795_CLK_CANFD>, 1374 <&can_clk>; 1375 clock-names = "fck", "canfd", "can_clk"; 1376 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; 1377 assigned-clock-rates = <40000000>; 1378 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1379 resets = <&cpg 914>; 1380 status = "disabled"; 1381 1382 channel0 { 1383 status = "disabled"; 1384 }; 1385 1386 channel1 { 1387 status = "disabled"; 1388 }; 1389 }; 1390 1391 pwm0: pwm@e6e30000 { 1392 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1393 reg = <0 0xe6e30000 0 0x8>; 1394 clocks = <&cpg CPG_MOD 523>; 1395 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1396 resets = <&cpg 523>; 1397 #pwm-cells = <2>; 1398 status = "disabled"; 1399 }; 1400 1401 pwm1: pwm@e6e31000 { 1402 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1403 reg = <0 0xe6e31000 0 0x8>; 1404 clocks = <&cpg CPG_MOD 523>; 1405 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1406 resets = <&cpg 523>; 1407 #pwm-cells = <2>; 1408 status = "disabled"; 1409 }; 1410 1411 pwm2: pwm@e6e32000 { 1412 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1413 reg = <0 0xe6e32000 0 0x8>; 1414 clocks = <&cpg CPG_MOD 523>; 1415 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1416 resets = <&cpg 523>; 1417 #pwm-cells = <2>; 1418 status = "disabled"; 1419 }; 1420 1421 pwm3: pwm@e6e33000 { 1422 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1423 reg = <0 0xe6e33000 0 0x8>; 1424 clocks = <&cpg CPG_MOD 523>; 1425 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1426 resets = <&cpg 523>; 1427 #pwm-cells = <2>; 1428 status = "disabled"; 1429 }; 1430 1431 pwm4: pwm@e6e34000 { 1432 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1433 reg = <0 0xe6e34000 0 0x8>; 1434 clocks = <&cpg CPG_MOD 523>; 1435 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1436 resets = <&cpg 523>; 1437 #pwm-cells = <2>; 1438 status = "disabled"; 1439 }; 1440 1441 pwm5: pwm@e6e35000 { 1442 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1443 reg = <0 0xe6e35000 0 0x8>; 1444 clocks = <&cpg CPG_MOD 523>; 1445 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1446 resets = <&cpg 523>; 1447 #pwm-cells = <2>; 1448 status = "disabled"; 1449 }; 1450 1451 pwm6: pwm@e6e36000 { 1452 compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; 1453 reg = <0 0xe6e36000 0 0x8>; 1454 clocks = <&cpg CPG_MOD 523>; 1455 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1456 resets = <&cpg 523>; 1457 #pwm-cells = <2>; 1458 status = "disabled"; 1459 }; 1460 1461 scif0: serial@e6e60000 { 1462 compatible = "renesas,scif-r8a7795", 1463 "renesas,rcar-gen3-scif", "renesas,scif"; 1464 reg = <0 0xe6e60000 0 64>; 1465 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1466 clocks = <&cpg CPG_MOD 207>, 1467 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1468 <&scif_clk>; 1469 clock-names = "fck", "brg_int", "scif_clk"; 1470 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1471 <&dmac2 0x51>, <&dmac2 0x50>; 1472 dma-names = "tx", "rx", "tx", "rx"; 1473 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1474 resets = <&cpg 207>; 1475 status = "disabled"; 1476 }; 1477 1478 scif1: serial@e6e68000 { 1479 compatible = "renesas,scif-r8a7795", 1480 "renesas,rcar-gen3-scif", "renesas,scif"; 1481 reg = <0 0xe6e68000 0 64>; 1482 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1483 clocks = <&cpg CPG_MOD 206>, 1484 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1485 <&scif_clk>; 1486 clock-names = "fck", "brg_int", "scif_clk"; 1487 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1488 <&dmac2 0x53>, <&dmac2 0x52>; 1489 dma-names = "tx", "rx", "tx", "rx"; 1490 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1491 resets = <&cpg 206>; 1492 status = "disabled"; 1493 }; 1494 1495 scif2: serial@e6e88000 { 1496 compatible = "renesas,scif-r8a7795", 1497 "renesas,rcar-gen3-scif", "renesas,scif"; 1498 reg = <0 0xe6e88000 0 64>; 1499 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1500 clocks = <&cpg CPG_MOD 310>, 1501 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1502 <&scif_clk>; 1503 clock-names = "fck", "brg_int", "scif_clk"; 1504 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1505 <&dmac2 0x13>, <&dmac2 0x12>; 1506 dma-names = "tx", "rx", "tx", "rx"; 1507 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1508 resets = <&cpg 310>; 1509 status = "disabled"; 1510 }; 1511 1512 scif3: serial@e6c50000 { 1513 compatible = "renesas,scif-r8a7795", 1514 "renesas,rcar-gen3-scif", "renesas,scif"; 1515 reg = <0 0xe6c50000 0 64>; 1516 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1517 clocks = <&cpg CPG_MOD 204>, 1518 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1519 <&scif_clk>; 1520 clock-names = "fck", "brg_int", "scif_clk"; 1521 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1522 dma-names = "tx", "rx"; 1523 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1524 resets = <&cpg 204>; 1525 status = "disabled"; 1526 }; 1527 1528 scif4: serial@e6c40000 { 1529 compatible = "renesas,scif-r8a7795", 1530 "renesas,rcar-gen3-scif", "renesas,scif"; 1531 reg = <0 0xe6c40000 0 64>; 1532 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1533 clocks = <&cpg CPG_MOD 203>, 1534 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1535 <&scif_clk>; 1536 clock-names = "fck", "brg_int", "scif_clk"; 1537 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1538 dma-names = "tx", "rx"; 1539 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1540 resets = <&cpg 203>; 1541 status = "disabled"; 1542 }; 1543 1544 scif5: serial@e6f30000 { 1545 compatible = "renesas,scif-r8a7795", 1546 "renesas,rcar-gen3-scif", "renesas,scif"; 1547 reg = <0 0xe6f30000 0 64>; 1548 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1549 clocks = <&cpg CPG_MOD 202>, 1550 <&cpg CPG_CORE R8A7795_CLK_S3D1>, 1551 <&scif_clk>; 1552 clock-names = "fck", "brg_int", "scif_clk"; 1553 dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, 1554 <&dmac2 0x5b>, <&dmac2 0x5a>; 1555 dma-names = "tx", "rx", "tx", "rx"; 1556 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1557 resets = <&cpg 202>; 1558 status = "disabled"; 1559 }; 1560 1561 tpu: pwm@e6e80000 { 1562 compatible = "renesas,tpu-r8a7795", "renesas,tpu"; 1563 reg = <0 0xe6e80000 0 0x148>; 1564 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 1565 clocks = <&cpg CPG_MOD 304>; 1566 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1567 resets = <&cpg 304>; 1568 #pwm-cells = <3>; 1569 status = "disabled"; 1570 }; 1571 1572 msiof0: spi@e6e90000 { 1573 compatible = "renesas,msiof-r8a7795", 1574 "renesas,rcar-gen3-msiof"; 1575 reg = <0 0xe6e90000 0 0x0064>; 1576 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1577 clocks = <&cpg CPG_MOD 211>; 1578 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1579 <&dmac2 0x41>, <&dmac2 0x40>; 1580 dma-names = "tx", "rx", "tx", "rx"; 1581 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1582 resets = <&cpg 211>; 1583 #address-cells = <1>; 1584 #size-cells = <0>; 1585 status = "disabled"; 1586 }; 1587 1588 msiof1: spi@e6ea0000 { 1589 compatible = "renesas,msiof-r8a7795", 1590 "renesas,rcar-gen3-msiof"; 1591 reg = <0 0xe6ea0000 0 0x0064>; 1592 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1593 clocks = <&cpg CPG_MOD 210>; 1594 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1595 <&dmac2 0x43>, <&dmac2 0x42>; 1596 dma-names = "tx", "rx", "tx", "rx"; 1597 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1598 resets = <&cpg 210>; 1599 #address-cells = <1>; 1600 #size-cells = <0>; 1601 status = "disabled"; 1602 }; 1603 1604 msiof2: spi@e6c00000 { 1605 compatible = "renesas,msiof-r8a7795", 1606 "renesas,rcar-gen3-msiof"; 1607 reg = <0 0xe6c00000 0 0x0064>; 1608 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1609 clocks = <&cpg CPG_MOD 209>; 1610 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1611 dma-names = "tx", "rx"; 1612 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1613 resets = <&cpg 209>; 1614 #address-cells = <1>; 1615 #size-cells = <0>; 1616 status = "disabled"; 1617 }; 1618 1619 msiof3: spi@e6c10000 { 1620 compatible = "renesas,msiof-r8a7795", 1621 "renesas,rcar-gen3-msiof"; 1622 reg = <0 0xe6c10000 0 0x0064>; 1623 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1624 clocks = <&cpg CPG_MOD 208>; 1625 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1626 dma-names = "tx", "rx"; 1627 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1628 resets = <&cpg 208>; 1629 #address-cells = <1>; 1630 #size-cells = <0>; 1631 status = "disabled"; 1632 }; 1633 1634 vin0: video@e6ef0000 { 1635 compatible = "renesas,vin-r8a7795"; 1636 reg = <0 0xe6ef0000 0 0x1000>; 1637 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1638 clocks = <&cpg CPG_MOD 811>; 1639 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1640 resets = <&cpg 811>; 1641 renesas,id = <0>; 1642 status = "disabled"; 1643 1644 ports { 1645 #address-cells = <1>; 1646 #size-cells = <0>; 1647 1648 port@1 { 1649 #address-cells = <1>; 1650 #size-cells = <0>; 1651 1652 reg = <1>; 1653 1654 vin0csi20: endpoint@0 { 1655 reg = <0>; 1656 remote-endpoint = <&csi20vin0>; 1657 }; 1658 vin0csi40: endpoint@2 { 1659 reg = <2>; 1660 remote-endpoint = <&csi40vin0>; 1661 }; 1662 }; 1663 }; 1664 }; 1665 1666 vin1: video@e6ef1000 { 1667 compatible = "renesas,vin-r8a7795"; 1668 reg = <0 0xe6ef1000 0 0x1000>; 1669 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1670 clocks = <&cpg CPG_MOD 810>; 1671 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1672 resets = <&cpg 810>; 1673 renesas,id = <1>; 1674 status = "disabled"; 1675 1676 ports { 1677 #address-cells = <1>; 1678 #size-cells = <0>; 1679 1680 port@1 { 1681 #address-cells = <1>; 1682 #size-cells = <0>; 1683 1684 reg = <1>; 1685 1686 vin1csi20: endpoint@0 { 1687 reg = <0>; 1688 remote-endpoint = <&csi20vin1>; 1689 }; 1690 vin1csi40: endpoint@2 { 1691 reg = <2>; 1692 remote-endpoint = <&csi40vin1>; 1693 }; 1694 }; 1695 }; 1696 }; 1697 1698 vin2: video@e6ef2000 { 1699 compatible = "renesas,vin-r8a7795"; 1700 reg = <0 0xe6ef2000 0 0x1000>; 1701 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1702 clocks = <&cpg CPG_MOD 809>; 1703 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1704 resets = <&cpg 809>; 1705 renesas,id = <2>; 1706 status = "disabled"; 1707 1708 ports { 1709 #address-cells = <1>; 1710 #size-cells = <0>; 1711 1712 port@1 { 1713 #address-cells = <1>; 1714 #size-cells = <0>; 1715 1716 reg = <1>; 1717 1718 vin2csi20: endpoint@0 { 1719 reg = <0>; 1720 remote-endpoint = <&csi20vin2>; 1721 }; 1722 vin2csi40: endpoint@2 { 1723 reg = <2>; 1724 remote-endpoint = <&csi40vin2>; 1725 }; 1726 }; 1727 }; 1728 }; 1729 1730 vin3: video@e6ef3000 { 1731 compatible = "renesas,vin-r8a7795"; 1732 reg = <0 0xe6ef3000 0 0x1000>; 1733 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1734 clocks = <&cpg CPG_MOD 808>; 1735 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1736 resets = <&cpg 808>; 1737 renesas,id = <3>; 1738 status = "disabled"; 1739 1740 ports { 1741 #address-cells = <1>; 1742 #size-cells = <0>; 1743 1744 port@1 { 1745 #address-cells = <1>; 1746 #size-cells = <0>; 1747 1748 reg = <1>; 1749 1750 vin3csi20: endpoint@0 { 1751 reg = <0>; 1752 remote-endpoint = <&csi20vin3>; 1753 }; 1754 vin3csi40: endpoint@2 { 1755 reg = <2>; 1756 remote-endpoint = <&csi40vin3>; 1757 }; 1758 }; 1759 }; 1760 }; 1761 1762 vin4: video@e6ef4000 { 1763 compatible = "renesas,vin-r8a7795"; 1764 reg = <0 0xe6ef4000 0 0x1000>; 1765 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1766 clocks = <&cpg CPG_MOD 807>; 1767 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1768 resets = <&cpg 807>; 1769 renesas,id = <4>; 1770 status = "disabled"; 1771 1772 ports { 1773 #address-cells = <1>; 1774 #size-cells = <0>; 1775 1776 port@1 { 1777 #address-cells = <1>; 1778 #size-cells = <0>; 1779 1780 reg = <1>; 1781 1782 vin4csi20: endpoint@0 { 1783 reg = <0>; 1784 remote-endpoint = <&csi20vin4>; 1785 }; 1786 vin4csi41: endpoint@3 { 1787 reg = <3>; 1788 remote-endpoint = <&csi41vin4>; 1789 }; 1790 }; 1791 }; 1792 }; 1793 1794 vin5: video@e6ef5000 { 1795 compatible = "renesas,vin-r8a7795"; 1796 reg = <0 0xe6ef5000 0 0x1000>; 1797 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1798 clocks = <&cpg CPG_MOD 806>; 1799 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1800 resets = <&cpg 806>; 1801 renesas,id = <5>; 1802 status = "disabled"; 1803 1804 ports { 1805 #address-cells = <1>; 1806 #size-cells = <0>; 1807 1808 port@1 { 1809 #address-cells = <1>; 1810 #size-cells = <0>; 1811 1812 reg = <1>; 1813 1814 vin5csi20: endpoint@0 { 1815 reg = <0>; 1816 remote-endpoint = <&csi20vin5>; 1817 }; 1818 vin5csi41: endpoint@3 { 1819 reg = <3>; 1820 remote-endpoint = <&csi41vin5>; 1821 }; 1822 }; 1823 }; 1824 }; 1825 1826 vin6: video@e6ef6000 { 1827 compatible = "renesas,vin-r8a7795"; 1828 reg = <0 0xe6ef6000 0 0x1000>; 1829 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1830 clocks = <&cpg CPG_MOD 805>; 1831 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1832 resets = <&cpg 805>; 1833 renesas,id = <6>; 1834 status = "disabled"; 1835 1836 ports { 1837 #address-cells = <1>; 1838 #size-cells = <0>; 1839 1840 port@1 { 1841 #address-cells = <1>; 1842 #size-cells = <0>; 1843 1844 reg = <1>; 1845 1846 vin6csi20: endpoint@0 { 1847 reg = <0>; 1848 remote-endpoint = <&csi20vin6>; 1849 }; 1850 vin6csi41: endpoint@3 { 1851 reg = <3>; 1852 remote-endpoint = <&csi41vin6>; 1853 }; 1854 }; 1855 }; 1856 }; 1857 1858 vin7: video@e6ef7000 { 1859 compatible = "renesas,vin-r8a7795"; 1860 reg = <0 0xe6ef7000 0 0x1000>; 1861 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1862 clocks = <&cpg CPG_MOD 804>; 1863 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1864 resets = <&cpg 804>; 1865 renesas,id = <7>; 1866 status = "disabled"; 1867 1868 ports { 1869 #address-cells = <1>; 1870 #size-cells = <0>; 1871 1872 port@1 { 1873 #address-cells = <1>; 1874 #size-cells = <0>; 1875 1876 reg = <1>; 1877 1878 vin7csi20: endpoint@0 { 1879 reg = <0>; 1880 remote-endpoint = <&csi20vin7>; 1881 }; 1882 vin7csi41: endpoint@3 { 1883 reg = <3>; 1884 remote-endpoint = <&csi41vin7>; 1885 }; 1886 }; 1887 }; 1888 }; 1889 1890 drif00: rif@e6f40000 { 1891 compatible = "renesas,r8a7795-drif", 1892 "renesas,rcar-gen3-drif"; 1893 reg = <0 0xe6f40000 0 0x64>; 1894 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1895 clocks = <&cpg CPG_MOD 515>; 1896 clock-names = "fck"; 1897 dmas = <&dmac1 0x20>, <&dmac2 0x20>; 1898 dma-names = "rx", "rx"; 1899 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1900 resets = <&cpg 515>; 1901 renesas,bonding = <&drif01>; 1902 status = "disabled"; 1903 }; 1904 1905 drif01: rif@e6f50000 { 1906 compatible = "renesas,r8a7795-drif", 1907 "renesas,rcar-gen3-drif"; 1908 reg = <0 0xe6f50000 0 0x64>; 1909 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1910 clocks = <&cpg CPG_MOD 514>; 1911 clock-names = "fck"; 1912 dmas = <&dmac1 0x22>, <&dmac2 0x22>; 1913 dma-names = "rx", "rx"; 1914 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1915 resets = <&cpg 514>; 1916 renesas,bonding = <&drif00>; 1917 status = "disabled"; 1918 }; 1919 1920 drif10: rif@e6f60000 { 1921 compatible = "renesas,r8a7795-drif", 1922 "renesas,rcar-gen3-drif"; 1923 reg = <0 0xe6f60000 0 0x64>; 1924 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1925 clocks = <&cpg CPG_MOD 513>; 1926 clock-names = "fck"; 1927 dmas = <&dmac1 0x24>, <&dmac2 0x24>; 1928 dma-names = "rx", "rx"; 1929 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1930 resets = <&cpg 513>; 1931 renesas,bonding = <&drif11>; 1932 status = "disabled"; 1933 }; 1934 1935 drif11: rif@e6f70000 { 1936 compatible = "renesas,r8a7795-drif", 1937 "renesas,rcar-gen3-drif"; 1938 reg = <0 0xe6f70000 0 0x64>; 1939 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1940 clocks = <&cpg CPG_MOD 512>; 1941 clock-names = "fck"; 1942 dmas = <&dmac1 0x26>, <&dmac2 0x26>; 1943 dma-names = "rx", "rx"; 1944 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1945 resets = <&cpg 512>; 1946 renesas,bonding = <&drif10>; 1947 status = "disabled"; 1948 }; 1949 1950 drif20: rif@e6f80000 { 1951 compatible = "renesas,r8a7795-drif", 1952 "renesas,rcar-gen3-drif"; 1953 reg = <0 0xe6f80000 0 0x64>; 1954 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1955 clocks = <&cpg CPG_MOD 511>; 1956 clock-names = "fck"; 1957 dmas = <&dmac1 0x28>, <&dmac2 0x28>; 1958 dma-names = "rx", "rx"; 1959 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1960 resets = <&cpg 511>; 1961 renesas,bonding = <&drif21>; 1962 status = "disabled"; 1963 }; 1964 1965 drif21: rif@e6f90000 { 1966 compatible = "renesas,r8a7795-drif", 1967 "renesas,rcar-gen3-drif"; 1968 reg = <0 0xe6f90000 0 0x64>; 1969 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1970 clocks = <&cpg CPG_MOD 510>; 1971 clock-names = "fck"; 1972 dmas = <&dmac1 0x2a>, <&dmac2 0x2a>; 1973 dma-names = "rx", "rx"; 1974 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1975 resets = <&cpg 510>; 1976 renesas,bonding = <&drif20>; 1977 status = "disabled"; 1978 }; 1979 1980 drif30: rif@e6fa0000 { 1981 compatible = "renesas,r8a7795-drif", 1982 "renesas,rcar-gen3-drif"; 1983 reg = <0 0xe6fa0000 0 0x64>; 1984 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1985 clocks = <&cpg CPG_MOD 509>; 1986 clock-names = "fck"; 1987 dmas = <&dmac1 0x2c>, <&dmac2 0x2c>; 1988 dma-names = "rx", "rx"; 1989 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 1990 resets = <&cpg 509>; 1991 renesas,bonding = <&drif31>; 1992 status = "disabled"; 1993 }; 1994 1995 drif31: rif@e6fb0000 { 1996 compatible = "renesas,r8a7795-drif", 1997 "renesas,rcar-gen3-drif"; 1998 reg = <0 0xe6fb0000 0 0x64>; 1999 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 2000 clocks = <&cpg CPG_MOD 508>; 2001 clock-names = "fck"; 2002 dmas = <&dmac1 0x2e>, <&dmac2 0x2e>; 2003 dma-names = "rx", "rx"; 2004 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2005 resets = <&cpg 508>; 2006 renesas,bonding = <&drif30>; 2007 status = "disabled"; 2008 }; 2009 2010 rcar_sound: sound@ec500000 { 2011 /* 2012 * #sound-dai-cells is required 2013 * 2014 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 2015 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 2016 */ 2017 /* 2018 * #clock-cells is required for audio_clkout0/1/2/3 2019 * 2020 * clkout : #clock-cells = <0>; <&rcar_sound>; 2021 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 2022 */ 2023 compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3"; 2024 reg = <0 0xec500000 0 0x1000>, /* SCU */ 2025 <0 0xec5a0000 0 0x100>, /* ADG */ 2026 <0 0xec540000 0 0x1000>, /* SSIU */ 2027 <0 0xec541000 0 0x280>, /* SSI */ 2028 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 2029 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 2030 2031 clocks = <&cpg CPG_MOD 1005>, 2032 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 2033 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 2034 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 2035 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 2036 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 2037 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 2038 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 2039 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 2040 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 2041 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 2042 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 2043 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 2044 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 2045 <&audio_clk_a>, <&audio_clk_b>, 2046 <&audio_clk_c>, 2047 <&cpg CPG_CORE R8A7795_CLK_S0D4>; 2048 clock-names = "ssi-all", 2049 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 2050 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 2051 "ssi.1", "ssi.0", 2052 "src.9", "src.8", "src.7", "src.6", 2053 "src.5", "src.4", "src.3", "src.2", 2054 "src.1", "src.0", 2055 "mix.1", "mix.0", 2056 "ctu.1", "ctu.0", 2057 "dvc.0", "dvc.1", 2058 "clk_a", "clk_b", "clk_c", "clk_i"; 2059 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2060 resets = <&cpg 1005>, 2061 <&cpg 1006>, <&cpg 1007>, 2062 <&cpg 1008>, <&cpg 1009>, 2063 <&cpg 1010>, <&cpg 1011>, 2064 <&cpg 1012>, <&cpg 1013>, 2065 <&cpg 1014>, <&cpg 1015>; 2066 reset-names = "ssi-all", 2067 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 2068 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 2069 "ssi.1", "ssi.0"; 2070 status = "disabled"; 2071 2072 rcar_sound,dvc { 2073 dvc0: dvc-0 { 2074 dmas = <&audma1 0xbc>; 2075 dma-names = "tx"; 2076 }; 2077 dvc1: dvc-1 { 2078 dmas = <&audma1 0xbe>; 2079 dma-names = "tx"; 2080 }; 2081 }; 2082 2083 rcar_sound,mix { 2084 mix0: mix-0 { }; 2085 mix1: mix-1 { }; 2086 }; 2087 2088 rcar_sound,ctu { 2089 ctu00: ctu-0 { }; 2090 ctu01: ctu-1 { }; 2091 ctu02: ctu-2 { }; 2092 ctu03: ctu-3 { }; 2093 ctu10: ctu-4 { }; 2094 ctu11: ctu-5 { }; 2095 ctu12: ctu-6 { }; 2096 ctu13: ctu-7 { }; 2097 }; 2098 2099 rcar_sound,src { 2100 src0: src-0 { 2101 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 2102 dmas = <&audma0 0x85>, <&audma1 0x9a>; 2103 dma-names = "rx", "tx"; 2104 }; 2105 src1: src-1 { 2106 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 2107 dmas = <&audma0 0x87>, <&audma1 0x9c>; 2108 dma-names = "rx", "tx"; 2109 }; 2110 src2: src-2 { 2111 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 2112 dmas = <&audma0 0x89>, <&audma1 0x9e>; 2113 dma-names = "rx", "tx"; 2114 }; 2115 src3: src-3 { 2116 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 2117 dmas = <&audma0 0x8b>, <&audma1 0xa0>; 2118 dma-names = "rx", "tx"; 2119 }; 2120 src4: src-4 { 2121 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 2122 dmas = <&audma0 0x8d>, <&audma1 0xb0>; 2123 dma-names = "rx", "tx"; 2124 }; 2125 src5: src-5 { 2126 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2127 dmas = <&audma0 0x8f>, <&audma1 0xb2>; 2128 dma-names = "rx", "tx"; 2129 }; 2130 src6: src-6 { 2131 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2132 dmas = <&audma0 0x91>, <&audma1 0xb4>; 2133 dma-names = "rx", "tx"; 2134 }; 2135 src7: src-7 { 2136 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 2137 dmas = <&audma0 0x93>, <&audma1 0xb6>; 2138 dma-names = "rx", "tx"; 2139 }; 2140 src8: src-8 { 2141 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 2142 dmas = <&audma0 0x95>, <&audma1 0xb8>; 2143 dma-names = "rx", "tx"; 2144 }; 2145 src9: src-9 { 2146 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 2147 dmas = <&audma0 0x97>, <&audma1 0xba>; 2148 dma-names = "rx", "tx"; 2149 }; 2150 }; 2151 2152 rcar_sound,ssiu { 2153 ssiu00: ssiu-0 { 2154 dmas = <&audma0 0x15>, <&audma1 0x16>; 2155 dma-names = "rx", "tx"; 2156 }; 2157 ssiu01: ssiu-1 { 2158 dmas = <&audma0 0x35>, <&audma1 0x36>; 2159 dma-names = "rx", "tx"; 2160 }; 2161 ssiu02: ssiu-2 { 2162 dmas = <&audma0 0x37>, <&audma1 0x38>; 2163 dma-names = "rx", "tx"; 2164 }; 2165 ssiu03: ssiu-3 { 2166 dmas = <&audma0 0x47>, <&audma1 0x48>; 2167 dma-names = "rx", "tx"; 2168 }; 2169 ssiu04: ssiu-4 { 2170 dmas = <&audma0 0x3F>, <&audma1 0x40>; 2171 dma-names = "rx", "tx"; 2172 }; 2173 ssiu05: ssiu-5 { 2174 dmas = <&audma0 0x43>, <&audma1 0x44>; 2175 dma-names = "rx", "tx"; 2176 }; 2177 ssiu06: ssiu-6 { 2178 dmas = <&audma0 0x4F>, <&audma1 0x50>; 2179 dma-names = "rx", "tx"; 2180 }; 2181 ssiu07: ssiu-7 { 2182 dmas = <&audma0 0x53>, <&audma1 0x54>; 2183 dma-names = "rx", "tx"; 2184 }; 2185 ssiu10: ssiu-8 { 2186 dmas = <&audma0 0x49>, <&audma1 0x4a>; 2187 dma-names = "rx", "tx"; 2188 }; 2189 ssiu11: ssiu-9 { 2190 dmas = <&audma0 0x4B>, <&audma1 0x4C>; 2191 dma-names = "rx", "tx"; 2192 }; 2193 ssiu12: ssiu-10 { 2194 dmas = <&audma0 0x57>, <&audma1 0x58>; 2195 dma-names = "rx", "tx"; 2196 }; 2197 ssiu13: ssiu-11 { 2198 dmas = <&audma0 0x59>, <&audma1 0x5A>; 2199 dma-names = "rx", "tx"; 2200 }; 2201 ssiu14: ssiu-12 { 2202 dmas = <&audma0 0x5F>, <&audma1 0x60>; 2203 dma-names = "rx", "tx"; 2204 }; 2205 ssiu15: ssiu-13 { 2206 dmas = <&audma0 0xC3>, <&audma1 0xC4>; 2207 dma-names = "rx", "tx"; 2208 }; 2209 ssiu16: ssiu-14 { 2210 dmas = <&audma0 0xC7>, <&audma1 0xC8>; 2211 dma-names = "rx", "tx"; 2212 }; 2213 ssiu17: ssiu-15 { 2214 dmas = <&audma0 0xCB>, <&audma1 0xCC>; 2215 dma-names = "rx", "tx"; 2216 }; 2217 ssiu20: ssiu-16 { 2218 dmas = <&audma0 0x63>, <&audma1 0x64>; 2219 dma-names = "rx", "tx"; 2220 }; 2221 ssiu21: ssiu-17 { 2222 dmas = <&audma0 0x67>, <&audma1 0x68>; 2223 dma-names = "rx", "tx"; 2224 }; 2225 ssiu22: ssiu-18 { 2226 dmas = <&audma0 0x6B>, <&audma1 0x6C>; 2227 dma-names = "rx", "tx"; 2228 }; 2229 ssiu23: ssiu-19 { 2230 dmas = <&audma0 0x6D>, <&audma1 0x6E>; 2231 dma-names = "rx", "tx"; 2232 }; 2233 ssiu24: ssiu-20 { 2234 dmas = <&audma0 0xCF>, <&audma1 0xCE>; 2235 dma-names = "rx", "tx"; 2236 }; 2237 ssiu25: ssiu-21 { 2238 dmas = <&audma0 0xEB>, <&audma1 0xEC>; 2239 dma-names = "rx", "tx"; 2240 }; 2241 ssiu26: ssiu-22 { 2242 dmas = <&audma0 0xED>, <&audma1 0xEE>; 2243 dma-names = "rx", "tx"; 2244 }; 2245 ssiu27: ssiu-23 { 2246 dmas = <&audma0 0xEF>, <&audma1 0xF0>; 2247 dma-names = "rx", "tx"; 2248 }; 2249 ssiu30: ssiu-24 { 2250 dmas = <&audma0 0x6f>, <&audma1 0x70>; 2251 dma-names = "rx", "tx"; 2252 }; 2253 ssiu31: ssiu-25 { 2254 dmas = <&audma0 0x21>, <&audma1 0x22>; 2255 dma-names = "rx", "tx"; 2256 }; 2257 ssiu32: ssiu-26 { 2258 dmas = <&audma0 0x23>, <&audma1 0x24>; 2259 dma-names = "rx", "tx"; 2260 }; 2261 ssiu33: ssiu-27 { 2262 dmas = <&audma0 0x25>, <&audma1 0x26>; 2263 dma-names = "rx", "tx"; 2264 }; 2265 ssiu34: ssiu-28 { 2266 dmas = <&audma0 0x27>, <&audma1 0x28>; 2267 dma-names = "rx", "tx"; 2268 }; 2269 ssiu35: ssiu-29 { 2270 dmas = <&audma0 0x29>, <&audma1 0x2A>; 2271 dma-names = "rx", "tx"; 2272 }; 2273 ssiu36: ssiu-30 { 2274 dmas = <&audma0 0x2B>, <&audma1 0x2C>; 2275 dma-names = "rx", "tx"; 2276 }; 2277 ssiu37: ssiu-31 { 2278 dmas = <&audma0 0x2D>, <&audma1 0x2E>; 2279 dma-names = "rx", "tx"; 2280 }; 2281 ssiu40: ssiu-32 { 2282 dmas = <&audma0 0x71>, <&audma1 0x72>; 2283 dma-names = "rx", "tx"; 2284 }; 2285 ssiu41: ssiu-33 { 2286 dmas = <&audma0 0x17>, <&audma1 0x18>; 2287 dma-names = "rx", "tx"; 2288 }; 2289 ssiu42: ssiu-34 { 2290 dmas = <&audma0 0x19>, <&audma1 0x1A>; 2291 dma-names = "rx", "tx"; 2292 }; 2293 ssiu43: ssiu-35 { 2294 dmas = <&audma0 0x1B>, <&audma1 0x1C>; 2295 dma-names = "rx", "tx"; 2296 }; 2297 ssiu44: ssiu-36 { 2298 dmas = <&audma0 0x1D>, <&audma1 0x1E>; 2299 dma-names = "rx", "tx"; 2300 }; 2301 ssiu45: ssiu-37 { 2302 dmas = <&audma0 0x1F>, <&audma1 0x20>; 2303 dma-names = "rx", "tx"; 2304 }; 2305 ssiu46: ssiu-38 { 2306 dmas = <&audma0 0x31>, <&audma1 0x32>; 2307 dma-names = "rx", "tx"; 2308 }; 2309 ssiu47: ssiu-39 { 2310 dmas = <&audma0 0x33>, <&audma1 0x34>; 2311 dma-names = "rx", "tx"; 2312 }; 2313 ssiu50: ssiu-40 { 2314 dmas = <&audma0 0x73>, <&audma1 0x74>; 2315 dma-names = "rx", "tx"; 2316 }; 2317 ssiu60: ssiu-41 { 2318 dmas = <&audma0 0x75>, <&audma1 0x76>; 2319 dma-names = "rx", "tx"; 2320 }; 2321 ssiu70: ssiu-42 { 2322 dmas = <&audma0 0x79>, <&audma1 0x7a>; 2323 dma-names = "rx", "tx"; 2324 }; 2325 ssiu80: ssiu-43 { 2326 dmas = <&audma0 0x7b>, <&audma1 0x7c>; 2327 dma-names = "rx", "tx"; 2328 }; 2329 ssiu90: ssiu-44 { 2330 dmas = <&audma0 0x7d>, <&audma1 0x7e>; 2331 dma-names = "rx", "tx"; 2332 }; 2333 ssiu91: ssiu-45 { 2334 dmas = <&audma0 0x7F>, <&audma1 0x80>; 2335 dma-names = "rx", "tx"; 2336 }; 2337 ssiu92: ssiu-46 { 2338 dmas = <&audma0 0x81>, <&audma1 0x82>; 2339 dma-names = "rx", "tx"; 2340 }; 2341 ssiu93: ssiu-47 { 2342 dmas = <&audma0 0x83>, <&audma1 0x84>; 2343 dma-names = "rx", "tx"; 2344 }; 2345 ssiu94: ssiu-48 { 2346 dmas = <&audma0 0xA3>, <&audma1 0xA4>; 2347 dma-names = "rx", "tx"; 2348 }; 2349 ssiu95: ssiu-49 { 2350 dmas = <&audma0 0xA5>, <&audma1 0xA6>; 2351 dma-names = "rx", "tx"; 2352 }; 2353 ssiu96: ssiu-50 { 2354 dmas = <&audma0 0xA7>, <&audma1 0xA8>; 2355 dma-names = "rx", "tx"; 2356 }; 2357 ssiu97: ssiu-51 { 2358 dmas = <&audma0 0xA9>, <&audma1 0xAA>; 2359 dma-names = "rx", "tx"; 2360 }; 2361 }; 2362 2363 rcar_sound,ssi { 2364 ssi0: ssi-0 { 2365 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 2366 dmas = <&audma0 0x01>, <&audma1 0x02>; 2367 dma-names = "rx", "tx"; 2368 }; 2369 ssi1: ssi-1 { 2370 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 2371 dmas = <&audma0 0x03>, <&audma1 0x04>; 2372 dma-names = "rx", "tx"; 2373 }; 2374 ssi2: ssi-2 { 2375 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 2376 dmas = <&audma0 0x05>, <&audma1 0x06>; 2377 dma-names = "rx", "tx"; 2378 }; 2379 ssi3: ssi-3 { 2380 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 2381 dmas = <&audma0 0x07>, <&audma1 0x08>; 2382 dma-names = "rx", "tx"; 2383 }; 2384 ssi4: ssi-4 { 2385 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 2386 dmas = <&audma0 0x09>, <&audma1 0x0a>; 2387 dma-names = "rx", "tx"; 2388 }; 2389 ssi5: ssi-5 { 2390 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 2391 dmas = <&audma0 0x0b>, <&audma1 0x0c>; 2392 dma-names = "rx", "tx"; 2393 }; 2394 ssi6: ssi-6 { 2395 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 2396 dmas = <&audma0 0x0d>, <&audma1 0x0e>; 2397 dma-names = "rx", "tx"; 2398 }; 2399 ssi7: ssi-7 { 2400 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 2401 dmas = <&audma0 0x0f>, <&audma1 0x10>; 2402 dma-names = "rx", "tx"; 2403 }; 2404 ssi8: ssi-8 { 2405 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 2406 dmas = <&audma0 0x11>, <&audma1 0x12>; 2407 dma-names = "rx", "tx"; 2408 }; 2409 ssi9: ssi-9 { 2410 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 2411 dmas = <&audma0 0x13>, <&audma1 0x14>; 2412 dma-names = "rx", "tx"; 2413 }; 2414 }; 2415 }; 2416 2417 mlp: mlp@ec520000 { 2418 compatible = "renesas,r8a7795-mlp", 2419 "renesas,rcar-gen3-mlp"; 2420 reg = <0 0xec520000 0 0x800>; 2421 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 2422 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>; 2423 clocks = <&cpg CPG_MOD 802>; 2424 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2425 resets = <&cpg 802>; 2426 status = "disabled"; 2427 }; 2428 2429 audma0: dma-controller@ec700000 { 2430 compatible = "renesas,dmac-r8a7795", 2431 "renesas,rcar-dmac"; 2432 reg = <0 0xec700000 0 0x10000>; 2433 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 2434 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2435 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2436 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2437 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2438 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2439 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2440 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2441 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2442 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2443 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2444 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2445 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2446 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2447 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2448 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2449 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 2450 interrupt-names = "error", 2451 "ch0", "ch1", "ch2", "ch3", 2452 "ch4", "ch5", "ch6", "ch7", 2453 "ch8", "ch9", "ch10", "ch11", 2454 "ch12", "ch13", "ch14", "ch15"; 2455 clocks = <&cpg CPG_MOD 502>; 2456 clock-names = "fck"; 2457 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2458 resets = <&cpg 502>; 2459 #dma-cells = <1>; 2460 dma-channels = <16>; 2461 iommus = <&ipmmu_mp0 0>, <&ipmmu_mp0 1>, 2462 <&ipmmu_mp0 2>, <&ipmmu_mp0 3>, 2463 <&ipmmu_mp0 4>, <&ipmmu_mp0 5>, 2464 <&ipmmu_mp0 6>, <&ipmmu_mp0 7>, 2465 <&ipmmu_mp0 8>, <&ipmmu_mp0 9>, 2466 <&ipmmu_mp0 10>, <&ipmmu_mp0 11>, 2467 <&ipmmu_mp0 12>, <&ipmmu_mp0 13>, 2468 <&ipmmu_mp0 14>, <&ipmmu_mp0 15>; 2469 }; 2470 2471 audma1: dma-controller@ec720000 { 2472 compatible = "renesas,dmac-r8a7795", 2473 "renesas,rcar-dmac"; 2474 reg = <0 0xec720000 0 0x10000>; 2475 interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 2476 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2477 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2478 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2479 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2480 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2481 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2482 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2483 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2484 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2485 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2486 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 2487 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2488 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 2489 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 2490 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 2491 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; 2492 interrupt-names = "error", 2493 "ch0", "ch1", "ch2", "ch3", 2494 "ch4", "ch5", "ch6", "ch7", 2495 "ch8", "ch9", "ch10", "ch11", 2496 "ch12", "ch13", "ch14", "ch15"; 2497 clocks = <&cpg CPG_MOD 501>; 2498 clock-names = "fck"; 2499 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2500 resets = <&cpg 501>; 2501 #dma-cells = <1>; 2502 dma-channels = <16>; 2503 iommus = <&ipmmu_mp0 16>, <&ipmmu_mp0 17>, 2504 <&ipmmu_mp0 18>, <&ipmmu_mp0 19>, 2505 <&ipmmu_mp0 20>, <&ipmmu_mp0 21>, 2506 <&ipmmu_mp0 22>, <&ipmmu_mp0 23>, 2507 <&ipmmu_mp0 24>, <&ipmmu_mp0 25>, 2508 <&ipmmu_mp0 26>, <&ipmmu_mp0 27>, 2509 <&ipmmu_mp0 28>, <&ipmmu_mp0 29>, 2510 <&ipmmu_mp0 30>, <&ipmmu_mp0 31>; 2511 }; 2512 2513 xhci0: usb@ee000000 { 2514 compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; 2515 reg = <0 0xee000000 0 0xc00>; 2516 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2517 clocks = <&cpg CPG_MOD 328>; 2518 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2519 resets = <&cpg 328>; 2520 status = "disabled"; 2521 }; 2522 2523 usb3_peri0: usb@ee020000 { 2524 compatible = "renesas,r8a7795-usb3-peri", 2525 "renesas,rcar-gen3-usb3-peri"; 2526 reg = <0 0xee020000 0 0x400>; 2527 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2528 clocks = <&cpg CPG_MOD 328>; 2529 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2530 resets = <&cpg 328>; 2531 status = "disabled"; 2532 }; 2533 2534 ohci0: usb@ee080000 { 2535 compatible = "generic-ohci"; 2536 reg = <0 0xee080000 0 0x100>; 2537 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2538 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2539 phys = <&usb2_phy0 1>; 2540 phy-names = "usb"; 2541 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2542 resets = <&cpg 703>, <&cpg 704>; 2543 status = "disabled"; 2544 }; 2545 2546 ohci1: usb@ee0a0000 { 2547 compatible = "generic-ohci"; 2548 reg = <0 0xee0a0000 0 0x100>; 2549 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2550 clocks = <&cpg CPG_MOD 702>; 2551 phys = <&usb2_phy1 1>; 2552 phy-names = "usb"; 2553 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2554 resets = <&cpg 702>; 2555 status = "disabled"; 2556 }; 2557 2558 ohci2: usb@ee0c0000 { 2559 compatible = "generic-ohci"; 2560 reg = <0 0xee0c0000 0 0x100>; 2561 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 2562 clocks = <&cpg CPG_MOD 701>; 2563 phys = <&usb2_phy2 1>; 2564 phy-names = "usb"; 2565 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2566 resets = <&cpg 701>; 2567 status = "disabled"; 2568 }; 2569 2570 ohci3: usb@ee0e0000 { 2571 compatible = "generic-ohci"; 2572 reg = <0 0xee0e0000 0 0x100>; 2573 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2574 clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; 2575 phys = <&usb2_phy3 1>; 2576 phy-names = "usb"; 2577 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2578 resets = <&cpg 700>, <&cpg 705>; 2579 status = "disabled"; 2580 }; 2581 2582 ehci0: usb@ee080100 { 2583 compatible = "generic-ehci"; 2584 reg = <0 0xee080100 0 0x100>; 2585 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2586 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2587 phys = <&usb2_phy0 2>; 2588 phy-names = "usb"; 2589 companion = <&ohci0>; 2590 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2591 resets = <&cpg 703>, <&cpg 704>; 2592 status = "disabled"; 2593 }; 2594 2595 ehci1: usb@ee0a0100 { 2596 compatible = "generic-ehci"; 2597 reg = <0 0xee0a0100 0 0x100>; 2598 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 2599 clocks = <&cpg CPG_MOD 702>; 2600 phys = <&usb2_phy1 2>; 2601 phy-names = "usb"; 2602 companion = <&ohci1>; 2603 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2604 resets = <&cpg 702>; 2605 status = "disabled"; 2606 }; 2607 2608 ehci2: usb@ee0c0100 { 2609 compatible = "generic-ehci"; 2610 reg = <0 0xee0c0100 0 0x100>; 2611 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 2612 clocks = <&cpg CPG_MOD 701>; 2613 phys = <&usb2_phy2 2>; 2614 phy-names = "usb"; 2615 companion = <&ohci2>; 2616 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2617 resets = <&cpg 701>; 2618 status = "disabled"; 2619 }; 2620 2621 ehci3: usb@ee0e0100 { 2622 compatible = "generic-ehci"; 2623 reg = <0 0xee0e0100 0 0x100>; 2624 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2625 clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; 2626 phys = <&usb2_phy3 2>; 2627 phy-names = "usb"; 2628 companion = <&ohci3>; 2629 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2630 resets = <&cpg 700>, <&cpg 705>; 2631 status = "disabled"; 2632 }; 2633 2634 usb2_phy0: usb-phy@ee080200 { 2635 compatible = "renesas,usb2-phy-r8a7795", 2636 "renesas,rcar-gen3-usb2-phy"; 2637 reg = <0 0xee080200 0 0x700>; 2638 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 2639 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 2640 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2641 resets = <&cpg 703>, <&cpg 704>; 2642 #phy-cells = <1>; 2643 status = "disabled"; 2644 }; 2645 2646 usb2_phy1: usb-phy@ee0a0200 { 2647 compatible = "renesas,usb2-phy-r8a7795", 2648 "renesas,rcar-gen3-usb2-phy"; 2649 reg = <0 0xee0a0200 0 0x700>; 2650 clocks = <&cpg CPG_MOD 702>; 2651 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2652 resets = <&cpg 702>; 2653 #phy-cells = <1>; 2654 status = "disabled"; 2655 }; 2656 2657 usb2_phy2: usb-phy@ee0c0200 { 2658 compatible = "renesas,usb2-phy-r8a7795", 2659 "renesas,rcar-gen3-usb2-phy"; 2660 reg = <0 0xee0c0200 0 0x700>; 2661 clocks = <&cpg CPG_MOD 701>; 2662 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2663 resets = <&cpg 701>; 2664 #phy-cells = <1>; 2665 status = "disabled"; 2666 }; 2667 2668 usb2_phy3: usb-phy@ee0e0200 { 2669 compatible = "renesas,usb2-phy-r8a7795", 2670 "renesas,rcar-gen3-usb2-phy"; 2671 reg = <0 0xee0e0200 0 0x700>; 2672 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 2673 clocks = <&cpg CPG_MOD 700>, <&cpg CPG_MOD 705>; 2674 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2675 resets = <&cpg 700>, <&cpg 705>; 2676 #phy-cells = <1>; 2677 status = "disabled"; 2678 }; 2679 2680 sdhi0: mmc@ee100000 { 2681 compatible = "renesas,sdhi-r8a7795", 2682 "renesas,rcar-gen3-sdhi"; 2683 reg = <0 0xee100000 0 0x2000>; 2684 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 2685 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A7795_CLK_SD0H>; 2686 clock-names = "core", "clkh"; 2687 max-frequency = <200000000>; 2688 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2689 resets = <&cpg 314>; 2690 iommus = <&ipmmu_ds1 32>; 2691 status = "disabled"; 2692 }; 2693 2694 sdhi1: mmc@ee120000 { 2695 compatible = "renesas,sdhi-r8a7795", 2696 "renesas,rcar-gen3-sdhi"; 2697 reg = <0 0xee120000 0 0x2000>; 2698 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 2699 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A7795_CLK_SD1H>; 2700 clock-names = "core", "clkh"; 2701 max-frequency = <200000000>; 2702 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2703 resets = <&cpg 313>; 2704 iommus = <&ipmmu_ds1 33>; 2705 status = "disabled"; 2706 }; 2707 2708 sdhi2: mmc@ee140000 { 2709 compatible = "renesas,sdhi-r8a7795", 2710 "renesas,rcar-gen3-sdhi"; 2711 reg = <0 0xee140000 0 0x2000>; 2712 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 2713 clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A7795_CLK_SD2H>; 2714 clock-names = "core", "clkh"; 2715 max-frequency = <200000000>; 2716 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2717 resets = <&cpg 312>; 2718 iommus = <&ipmmu_ds1 34>; 2719 status = "disabled"; 2720 }; 2721 2722 sdhi3: mmc@ee160000 { 2723 compatible = "renesas,sdhi-r8a7795", 2724 "renesas,rcar-gen3-sdhi"; 2725 reg = <0 0xee160000 0 0x2000>; 2726 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 2727 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A7795_CLK_SD3H>; 2728 clock-names = "core", "clkh"; 2729 max-frequency = <200000000>; 2730 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2731 resets = <&cpg 311>; 2732 iommus = <&ipmmu_ds1 35>; 2733 status = "disabled"; 2734 }; 2735 2736 rpc: spi@ee200000 { 2737 compatible = "renesas,r8a7795-rpc-if", 2738 "renesas,rcar-gen3-rpc-if"; 2739 reg = <0 0xee200000 0 0x200>, 2740 <0 0x08000000 0 0x04000000>, 2741 <0 0xee208000 0 0x100>; 2742 reg-names = "regs", "dirmap", "wbuf"; 2743 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 2744 clocks = <&cpg CPG_MOD 917>; 2745 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2746 resets = <&cpg 917>; 2747 #address-cells = <1>; 2748 #size-cells = <0>; 2749 status = "disabled"; 2750 }; 2751 2752 sata: sata@ee300000 { 2753 compatible = "renesas,sata-r8a7795", 2754 "renesas,rcar-gen3-sata"; 2755 reg = <0 0xee300000 0 0x200000>; 2756 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2757 clocks = <&cpg CPG_MOD 815>; 2758 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2759 resets = <&cpg 815>; 2760 status = "disabled"; 2761 iommus = <&ipmmu_hc 2>; 2762 }; 2763 2764 gic: interrupt-controller@f1010000 { 2765 compatible = "arm,gic-400"; 2766 #interrupt-cells = <3>; 2767 #address-cells = <0>; 2768 interrupt-controller; 2769 reg = <0x0 0xf1010000 0 0x1000>, 2770 <0x0 0xf1020000 0 0x20000>, 2771 <0x0 0xf1040000 0 0x20000>, 2772 <0x0 0xf1060000 0 0x20000>; 2773 interrupts = <GIC_PPI 9 2774 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2775 clocks = <&cpg CPG_MOD 408>; 2776 clock-names = "clk"; 2777 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2778 resets = <&cpg 408>; 2779 }; 2780 2781 pciec0: pcie@fe000000 { 2782 compatible = "renesas,pcie-r8a7795", 2783 "renesas,pcie-rcar-gen3"; 2784 reg = <0 0xfe000000 0 0x80000>; 2785 #address-cells = <3>; 2786 #size-cells = <2>; 2787 bus-range = <0x00 0xff>; 2788 device_type = "pci"; 2789 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 2790 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 2791 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 2792 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 2793 /* Map all possible DDR as inbound ranges */ 2794 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; 2795 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2796 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2797 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2798 #interrupt-cells = <1>; 2799 interrupt-map-mask = <0 0 0 0>; 2800 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2801 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 2802 clock-names = "pcie", "pcie_bus"; 2803 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2804 resets = <&cpg 319>; 2805 status = "disabled"; 2806 }; 2807 2808 pciec1: pcie@ee800000 { 2809 compatible = "renesas,pcie-r8a7795", 2810 "renesas,pcie-rcar-gen3"; 2811 reg = <0 0xee800000 0 0x80000>; 2812 #address-cells = <3>; 2813 #size-cells = <2>; 2814 bus-range = <0x00 0xff>; 2815 device_type = "pci"; 2816 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, 2817 <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, 2818 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, 2819 <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; 2820 /* Map all possible DDR as inbound ranges */ 2821 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; 2822 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2823 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2824 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2825 #interrupt-cells = <1>; 2826 interrupt-map-mask = <0 0 0 0>; 2827 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2828 clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; 2829 clock-names = "pcie", "pcie_bus"; 2830 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2831 resets = <&cpg 318>; 2832 status = "disabled"; 2833 }; 2834 2835 pciec0_ep: pcie-ep@fe000000 { 2836 compatible = "renesas,r8a7795-pcie-ep", 2837 "renesas,rcar-gen3-pcie-ep"; 2838 reg = <0x0 0xfe000000 0 0x80000>, 2839 <0x0 0xfe100000 0 0x100000>, 2840 <0x0 0xfe200000 0 0x200000>, 2841 <0x0 0x30000000 0 0x8000000>, 2842 <0x0 0x38000000 0 0x8000000>; 2843 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 2844 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2845 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2846 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 2847 clocks = <&cpg CPG_MOD 319>; 2848 clock-names = "pcie"; 2849 resets = <&cpg 319>; 2850 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2851 status = "disabled"; 2852 }; 2853 2854 pciec1_ep: pcie-ep@ee800000 { 2855 compatible = "renesas,r8a7795-pcie-ep", 2856 "renesas,rcar-gen3-pcie-ep"; 2857 reg = <0x0 0xee800000 0 0x80000>, 2858 <0x0 0xee900000 0 0x100000>, 2859 <0x0 0xeea00000 0 0x200000>, 2860 <0x0 0xc0000000 0 0x8000000>, 2861 <0x0 0xc8000000 0 0x8000000>; 2862 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 2863 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2864 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2865 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2866 clocks = <&cpg CPG_MOD 318>; 2867 clock-names = "pcie"; 2868 resets = <&cpg 318>; 2869 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2870 status = "disabled"; 2871 }; 2872 2873 imr-lx4@fe860000 { 2874 compatible = "renesas,r8a7795-imr-lx4", 2875 "renesas,imr-lx4"; 2876 reg = <0 0xfe860000 0 0x2000>; 2877 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 2878 clocks = <&cpg CPG_MOD 823>; 2879 power-domains = <&sysc R8A7795_PD_A3VC>; 2880 resets = <&cpg 823>; 2881 }; 2882 2883 imr-lx4@fe870000 { 2884 compatible = "renesas,r8a7795-imr-lx4", 2885 "renesas,imr-lx4"; 2886 reg = <0 0xfe870000 0 0x2000>; 2887 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 2888 clocks = <&cpg CPG_MOD 822>; 2889 power-domains = <&sysc R8A7795_PD_A3VC>; 2890 resets = <&cpg 822>; 2891 }; 2892 2893 imr-lx4@fe880000 { 2894 compatible = "renesas,r8a7795-imr-lx4", 2895 "renesas,imr-lx4"; 2896 reg = <0 0xfe880000 0 0x2000>; 2897 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 2898 clocks = <&cpg CPG_MOD 821>; 2899 power-domains = <&sysc R8A7795_PD_A3VC>; 2900 resets = <&cpg 821>; 2901 }; 2902 2903 imr-lx4@fe890000 { 2904 compatible = "renesas,r8a7795-imr-lx4", 2905 "renesas,imr-lx4"; 2906 reg = <0 0xfe890000 0 0x2000>; 2907 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 2908 clocks = <&cpg CPG_MOD 820>; 2909 power-domains = <&sysc R8A7795_PD_A3VC>; 2910 resets = <&cpg 820>; 2911 }; 2912 2913 vspbc: vsp@fe920000 { 2914 compatible = "renesas,vsp2"; 2915 reg = <0 0xfe920000 0 0x8000>; 2916 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 2917 clocks = <&cpg CPG_MOD 624>; 2918 power-domains = <&sysc R8A7795_PD_A3VP>; 2919 resets = <&cpg 624>; 2920 2921 renesas,fcp = <&fcpvb1>; 2922 }; 2923 2924 vspbd: vsp@fe960000 { 2925 compatible = "renesas,vsp2"; 2926 reg = <0 0xfe960000 0 0x8000>; 2927 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 2928 clocks = <&cpg CPG_MOD 626>; 2929 power-domains = <&sysc R8A7795_PD_A3VP>; 2930 resets = <&cpg 626>; 2931 2932 renesas,fcp = <&fcpvb0>; 2933 }; 2934 2935 vspd0: vsp@fea20000 { 2936 compatible = "renesas,vsp2"; 2937 reg = <0 0xfea20000 0 0x5000>; 2938 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 2939 clocks = <&cpg CPG_MOD 623>; 2940 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2941 resets = <&cpg 623>; 2942 2943 renesas,fcp = <&fcpvd0>; 2944 }; 2945 2946 vspd1: vsp@fea28000 { 2947 compatible = "renesas,vsp2"; 2948 reg = <0 0xfea28000 0 0x5000>; 2949 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 2950 clocks = <&cpg CPG_MOD 622>; 2951 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2952 resets = <&cpg 622>; 2953 2954 renesas,fcp = <&fcpvd1>; 2955 }; 2956 2957 vspd2: vsp@fea30000 { 2958 compatible = "renesas,vsp2"; 2959 reg = <0 0xfea30000 0 0x5000>; 2960 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 2961 clocks = <&cpg CPG_MOD 621>; 2962 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 2963 resets = <&cpg 621>; 2964 2965 renesas,fcp = <&fcpvd2>; 2966 }; 2967 2968 vspi0: vsp@fe9a0000 { 2969 compatible = "renesas,vsp2"; 2970 reg = <0 0xfe9a0000 0 0x8000>; 2971 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 2972 clocks = <&cpg CPG_MOD 631>; 2973 power-domains = <&sysc R8A7795_PD_A3VP>; 2974 resets = <&cpg 631>; 2975 2976 renesas,fcp = <&fcpvi0>; 2977 }; 2978 2979 vspi1: vsp@fe9b0000 { 2980 compatible = "renesas,vsp2"; 2981 reg = <0 0xfe9b0000 0 0x8000>; 2982 interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 2983 clocks = <&cpg CPG_MOD 630>; 2984 power-domains = <&sysc R8A7795_PD_A3VP>; 2985 resets = <&cpg 630>; 2986 2987 renesas,fcp = <&fcpvi1>; 2988 }; 2989 2990 fdp1@fe940000 { 2991 compatible = "renesas,fdp1"; 2992 reg = <0 0xfe940000 0 0x2400>; 2993 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 2994 clocks = <&cpg CPG_MOD 119>; 2995 power-domains = <&sysc R8A7795_PD_A3VP>; 2996 resets = <&cpg 119>; 2997 renesas,fcp = <&fcpf0>; 2998 }; 2999 3000 fdp1@fe944000 { 3001 compatible = "renesas,fdp1"; 3002 reg = <0 0xfe944000 0 0x2400>; 3003 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 3004 clocks = <&cpg CPG_MOD 118>; 3005 power-domains = <&sysc R8A7795_PD_A3VP>; 3006 resets = <&cpg 118>; 3007 renesas,fcp = <&fcpf1>; 3008 }; 3009 3010 fcpf0: fcp@fe950000 { 3011 compatible = "renesas,fcpf"; 3012 reg = <0 0xfe950000 0 0x200>; 3013 clocks = <&cpg CPG_MOD 615>; 3014 power-domains = <&sysc R8A7795_PD_A3VP>; 3015 resets = <&cpg 615>; 3016 iommus = <&ipmmu_vp0 0>; 3017 }; 3018 3019 fcpf1: fcp@fe951000 { 3020 compatible = "renesas,fcpf"; 3021 reg = <0 0xfe951000 0 0x200>; 3022 clocks = <&cpg CPG_MOD 614>; 3023 power-domains = <&sysc R8A7795_PD_A3VP>; 3024 resets = <&cpg 614>; 3025 iommus = <&ipmmu_vp1 1>; 3026 }; 3027 3028 fcpvb0: fcp@fe96f000 { 3029 compatible = "renesas,fcpv"; 3030 reg = <0 0xfe96f000 0 0x200>; 3031 clocks = <&cpg CPG_MOD 607>; 3032 power-domains = <&sysc R8A7795_PD_A3VP>; 3033 resets = <&cpg 607>; 3034 iommus = <&ipmmu_vp0 5>; 3035 }; 3036 3037 fcpvb1: fcp@fe92f000 { 3038 compatible = "renesas,fcpv"; 3039 reg = <0 0xfe92f000 0 0x200>; 3040 clocks = <&cpg CPG_MOD 606>; 3041 power-domains = <&sysc R8A7795_PD_A3VP>; 3042 resets = <&cpg 606>; 3043 iommus = <&ipmmu_vp1 7>; 3044 }; 3045 3046 fcpvi0: fcp@fe9af000 { 3047 compatible = "renesas,fcpv"; 3048 reg = <0 0xfe9af000 0 0x200>; 3049 clocks = <&cpg CPG_MOD 611>; 3050 power-domains = <&sysc R8A7795_PD_A3VP>; 3051 resets = <&cpg 611>; 3052 iommus = <&ipmmu_vp0 8>; 3053 }; 3054 3055 fcpvi1: fcp@fe9bf000 { 3056 compatible = "renesas,fcpv"; 3057 reg = <0 0xfe9bf000 0 0x200>; 3058 clocks = <&cpg CPG_MOD 610>; 3059 power-domains = <&sysc R8A7795_PD_A3VP>; 3060 resets = <&cpg 610>; 3061 iommus = <&ipmmu_vp1 9>; 3062 }; 3063 3064 fcpvd0: fcp@fea27000 { 3065 compatible = "renesas,fcpv"; 3066 reg = <0 0xfea27000 0 0x200>; 3067 clocks = <&cpg CPG_MOD 603>; 3068 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3069 resets = <&cpg 603>; 3070 iommus = <&ipmmu_vi0 8>; 3071 }; 3072 3073 fcpvd1: fcp@fea2f000 { 3074 compatible = "renesas,fcpv"; 3075 reg = <0 0xfea2f000 0 0x200>; 3076 clocks = <&cpg CPG_MOD 602>; 3077 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3078 resets = <&cpg 602>; 3079 iommus = <&ipmmu_vi0 9>; 3080 }; 3081 3082 fcpvd2: fcp@fea37000 { 3083 compatible = "renesas,fcpv"; 3084 reg = <0 0xfea37000 0 0x200>; 3085 clocks = <&cpg CPG_MOD 601>; 3086 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3087 resets = <&cpg 601>; 3088 iommus = <&ipmmu_vi1 10>; 3089 }; 3090 3091 cmm0: cmm@fea40000 { 3092 compatible = "renesas,r8a7795-cmm", 3093 "renesas,rcar-gen3-cmm"; 3094 reg = <0 0xfea40000 0 0x1000>; 3095 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3096 clocks = <&cpg CPG_MOD 711>; 3097 resets = <&cpg 711>; 3098 }; 3099 3100 cmm1: cmm@fea50000 { 3101 compatible = "renesas,r8a7795-cmm", 3102 "renesas,rcar-gen3-cmm"; 3103 reg = <0 0xfea50000 0 0x1000>; 3104 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3105 clocks = <&cpg CPG_MOD 710>; 3106 resets = <&cpg 710>; 3107 }; 3108 3109 cmm2: cmm@fea60000 { 3110 compatible = "renesas,r8a7795-cmm", 3111 "renesas,rcar-gen3-cmm"; 3112 reg = <0 0xfea60000 0 0x1000>; 3113 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3114 clocks = <&cpg CPG_MOD 709>; 3115 resets = <&cpg 709>; 3116 }; 3117 3118 cmm3: cmm@fea70000 { 3119 compatible = "renesas,r8a7795-cmm", 3120 "renesas,rcar-gen3-cmm"; 3121 reg = <0 0xfea70000 0 0x1000>; 3122 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3123 clocks = <&cpg CPG_MOD 708>; 3124 resets = <&cpg 708>; 3125 }; 3126 3127 csi20: csi2@fea80000 { 3128 compatible = "renesas,r8a7795-csi2"; 3129 reg = <0 0xfea80000 0 0x10000>; 3130 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 3131 clocks = <&cpg CPG_MOD 714>; 3132 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3133 resets = <&cpg 714>; 3134 status = "disabled"; 3135 3136 ports { 3137 #address-cells = <1>; 3138 #size-cells = <0>; 3139 3140 port@0 { 3141 reg = <0>; 3142 }; 3143 3144 port@1 { 3145 #address-cells = <1>; 3146 #size-cells = <0>; 3147 3148 reg = <1>; 3149 3150 csi20vin0: endpoint@0 { 3151 reg = <0>; 3152 remote-endpoint = <&vin0csi20>; 3153 }; 3154 csi20vin1: endpoint@1 { 3155 reg = <1>; 3156 remote-endpoint = <&vin1csi20>; 3157 }; 3158 csi20vin2: endpoint@2 { 3159 reg = <2>; 3160 remote-endpoint = <&vin2csi20>; 3161 }; 3162 csi20vin3: endpoint@3 { 3163 reg = <3>; 3164 remote-endpoint = <&vin3csi20>; 3165 }; 3166 csi20vin4: endpoint@4 { 3167 reg = <4>; 3168 remote-endpoint = <&vin4csi20>; 3169 }; 3170 csi20vin5: endpoint@5 { 3171 reg = <5>; 3172 remote-endpoint = <&vin5csi20>; 3173 }; 3174 csi20vin6: endpoint@6 { 3175 reg = <6>; 3176 remote-endpoint = <&vin6csi20>; 3177 }; 3178 csi20vin7: endpoint@7 { 3179 reg = <7>; 3180 remote-endpoint = <&vin7csi20>; 3181 }; 3182 }; 3183 }; 3184 }; 3185 3186 csi40: csi2@feaa0000 { 3187 compatible = "renesas,r8a7795-csi2"; 3188 reg = <0 0xfeaa0000 0 0x10000>; 3189 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 3190 clocks = <&cpg CPG_MOD 716>; 3191 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3192 resets = <&cpg 716>; 3193 status = "disabled"; 3194 3195 ports { 3196 #address-cells = <1>; 3197 #size-cells = <0>; 3198 3199 port@0 { 3200 reg = <0>; 3201 }; 3202 3203 port@1 { 3204 #address-cells = <1>; 3205 #size-cells = <0>; 3206 3207 reg = <1>; 3208 3209 csi40vin0: endpoint@0 { 3210 reg = <0>; 3211 remote-endpoint = <&vin0csi40>; 3212 }; 3213 csi40vin1: endpoint@1 { 3214 reg = <1>; 3215 remote-endpoint = <&vin1csi40>; 3216 }; 3217 csi40vin2: endpoint@2 { 3218 reg = <2>; 3219 remote-endpoint = <&vin2csi40>; 3220 }; 3221 csi40vin3: endpoint@3 { 3222 reg = <3>; 3223 remote-endpoint = <&vin3csi40>; 3224 }; 3225 }; 3226 }; 3227 }; 3228 3229 csi41: csi2@feab0000 { 3230 compatible = "renesas,r8a7795-csi2"; 3231 reg = <0 0xfeab0000 0 0x10000>; 3232 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 3233 clocks = <&cpg CPG_MOD 715>; 3234 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3235 resets = <&cpg 715>; 3236 status = "disabled"; 3237 3238 ports { 3239 #address-cells = <1>; 3240 #size-cells = <0>; 3241 3242 port@0 { 3243 reg = <0>; 3244 }; 3245 3246 port@1 { 3247 #address-cells = <1>; 3248 #size-cells = <0>; 3249 3250 reg = <1>; 3251 3252 csi41vin4: endpoint@0 { 3253 reg = <0>; 3254 remote-endpoint = <&vin4csi41>; 3255 }; 3256 csi41vin5: endpoint@1 { 3257 reg = <1>; 3258 remote-endpoint = <&vin5csi41>; 3259 }; 3260 csi41vin6: endpoint@2 { 3261 reg = <2>; 3262 remote-endpoint = <&vin6csi41>; 3263 }; 3264 csi41vin7: endpoint@3 { 3265 reg = <3>; 3266 remote-endpoint = <&vin7csi41>; 3267 }; 3268 }; 3269 }; 3270 }; 3271 3272 hdmi0: hdmi@fead0000 { 3273 compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; 3274 reg = <0 0xfead0000 0 0x10000>; 3275 interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; 3276 clocks = <&cpg CPG_MOD 729>, <&cpg CPG_CORE R8A7795_CLK_HDMI>; 3277 clock-names = "iahb", "isfr"; 3278 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3279 resets = <&cpg 729>; 3280 status = "disabled"; 3281 3282 ports { 3283 #address-cells = <1>; 3284 #size-cells = <0>; 3285 port@0 { 3286 reg = <0>; 3287 dw_hdmi0_in: endpoint { 3288 remote-endpoint = <&du_out_hdmi0>; 3289 }; 3290 }; 3291 port@1 { 3292 reg = <1>; 3293 }; 3294 port@2 { 3295 /* HDMI sound */ 3296 reg = <2>; 3297 }; 3298 }; 3299 }; 3300 3301 hdmi1: hdmi@feae0000 { 3302 compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi"; 3303 reg = <0 0xfeae0000 0 0x10000>; 3304 interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>; 3305 clocks = <&cpg CPG_MOD 728>, <&cpg CPG_CORE R8A7795_CLK_HDMI>; 3306 clock-names = "iahb", "isfr"; 3307 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3308 resets = <&cpg 728>; 3309 status = "disabled"; 3310 3311 ports { 3312 #address-cells = <1>; 3313 #size-cells = <0>; 3314 port@0 { 3315 reg = <0>; 3316 dw_hdmi1_in: endpoint { 3317 remote-endpoint = <&du_out_hdmi1>; 3318 }; 3319 }; 3320 port@1 { 3321 reg = <1>; 3322 }; 3323 port@2 { 3324 /* HDMI sound */ 3325 reg = <2>; 3326 }; 3327 }; 3328 }; 3329 3330 du: display@feb00000 { 3331 compatible = "renesas,du-r8a7795"; 3332 reg = <0 0xfeb00000 0 0x80000>; 3333 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 3334 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 3335 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 3336 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; 3337 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, 3338 <&cpg CPG_MOD 722>, <&cpg CPG_MOD 721>; 3339 clock-names = "du.0", "du.1", "du.2", "du.3"; 3340 resets = <&cpg 724>, <&cpg 722>; 3341 reset-names = "du.0", "du.2"; 3342 3343 renesas,cmms = <&cmm0>, <&cmm1>, <&cmm2>, <&cmm3>; 3344 renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>, 3345 <&vspd0 1>; 3346 3347 status = "disabled"; 3348 3349 ports { 3350 #address-cells = <1>; 3351 #size-cells = <0>; 3352 3353 port@0 { 3354 reg = <0>; 3355 }; 3356 port@1 { 3357 reg = <1>; 3358 du_out_hdmi0: endpoint { 3359 remote-endpoint = <&dw_hdmi0_in>; 3360 }; 3361 }; 3362 port@2 { 3363 reg = <2>; 3364 du_out_hdmi1: endpoint { 3365 remote-endpoint = <&dw_hdmi1_in>; 3366 }; 3367 }; 3368 port@3 { 3369 reg = <3>; 3370 du_out_lvds0: endpoint { 3371 remote-endpoint = <&lvds0_in>; 3372 }; 3373 }; 3374 }; 3375 }; 3376 3377 lvds0: lvds@feb90000 { 3378 compatible = "renesas,r8a7795-lvds"; 3379 reg = <0 0xfeb90000 0 0x14>; 3380 clocks = <&cpg CPG_MOD 727>; 3381 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; 3382 resets = <&cpg 727>; 3383 status = "disabled"; 3384 3385 ports { 3386 #address-cells = <1>; 3387 #size-cells = <0>; 3388 3389 port@0 { 3390 reg = <0>; 3391 lvds0_in: endpoint { 3392 remote-endpoint = <&du_out_lvds0>; 3393 }; 3394 }; 3395 port@1 { 3396 reg = <1>; 3397 }; 3398 }; 3399 }; 3400 3401 prr: chipid@fff00044 { 3402 compatible = "renesas,prr"; 3403 reg = <0 0xfff00044 0 4>; 3404 }; 3405 }; 3406 3407 thermal-zones { 3408 sensor1_thermal: sensor1-thermal { 3409 polling-delay-passive = <250>; 3410 polling-delay = <1000>; 3411 thermal-sensors = <&tsc 0>; 3412 sustainable-power = <6313>; 3413 3414 trips { 3415 sensor1_crit: sensor1-crit { 3416 temperature = <120000>; 3417 hysteresis = <1000>; 3418 type = "critical"; 3419 }; 3420 }; 3421 }; 3422 3423 sensor2_thermal: sensor2-thermal { 3424 polling-delay-passive = <250>; 3425 polling-delay = <1000>; 3426 thermal-sensors = <&tsc 1>; 3427 sustainable-power = <6313>; 3428 3429 trips { 3430 sensor2_crit: sensor2-crit { 3431 temperature = <120000>; 3432 hysteresis = <1000>; 3433 type = "critical"; 3434 }; 3435 }; 3436 }; 3437 3438 sensor3_thermal: sensor3-thermal { 3439 polling-delay-passive = <250>; 3440 polling-delay = <1000>; 3441 thermal-sensors = <&tsc 2>; 3442 3443 trips { 3444 target: trip-point1 { 3445 temperature = <100000>; 3446 hysteresis = <1000>; 3447 type = "passive"; 3448 }; 3449 3450 sensor3_crit: sensor3-crit { 3451 temperature = <120000>; 3452 hysteresis = <1000>; 3453 type = "critical"; 3454 }; 3455 }; 3456 3457 cooling-maps { 3458 map0 { 3459 trip = <&target>; 3460 cooling-device = <&a57_0 2 4>; 3461 contribution = <1024>; 3462 }; 3463 3464 map1 { 3465 trip = <&target>; 3466 cooling-device = <&a53_0 0 2>; 3467 contribution = <1024>; 3468 }; 3469 }; 3470 }; 3471 }; 3472 3473 timer { 3474 compatible = "arm,armv8-timer"; 3475 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3476 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3477 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 3478 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 3479 }; 3480 3481 /* External USB clocks - can be overridden by the board */ 3482 usb3s0_clk: usb3s0 { 3483 compatible = "fixed-clock"; 3484 #clock-cells = <0>; 3485 clock-frequency = <0>; 3486 }; 3487 3488 usb_extal_clk: usb_extal { 3489 compatible = "fixed-clock"; 3490 #clock-cells = <0>; 3491 clock-frequency = <0>; 3492 }; 3493}; 3494