1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the RZ/G2E (R8A774C0) SoC 4 * 5 * Copyright (C) 2018-2019 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a774c0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a774c0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a774c0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 /* 18 * The external audio clocks are configured as 0 Hz fixed frequency 19 * clocks by default. 20 * Boards that provide audio clocks should override them. 21 */ 22 audio_clk_a: audio_clk_a { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <0>; 26 }; 27 28 audio_clk_b: audio_clk_b { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <0>; 32 }; 33 34 audio_clk_c: audio_clk_c { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <0>; 38 }; 39 40 /* External CAN clock - to be overridden by boards that provide it */ 41 can_clk: can { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 45 }; 46 47 cluster1_opp: opp-table-1 { 48 compatible = "operating-points-v2"; 49 opp-shared; 50 opp-800000000 { 51 opp-hz = /bits/ 64 <800000000>; 52 opp-microvolt = <820000>; 53 clock-latency-ns = <300000>; 54 }; 55 opp-1000000000 { 56 opp-hz = /bits/ 64 <1000000000>; 57 opp-microvolt = <820000>; 58 clock-latency-ns = <300000>; 59 }; 60 opp-1200000000 { 61 opp-hz = /bits/ 64 <1200000000>; 62 opp-microvolt = <820000>; 63 clock-latency-ns = <300000>; 64 opp-suspend; 65 }; 66 }; 67 68 cpus { 69 #address-cells = <1>; 70 #size-cells = <0>; 71 72 a53_0: cpu@0 { 73 compatible = "arm,cortex-a53"; 74 reg = <0>; 75 device_type = "cpu"; 76 #cooling-cells = <2>; 77 power-domains = <&sysc R8A774C0_PD_CA53_CPU0>; 78 next-level-cache = <&L2_CA53>; 79 enable-method = "psci"; 80 dynamic-power-coefficient = <277>; 81 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; 82 operating-points-v2 = <&cluster1_opp>; 83 }; 84 85 a53_1: cpu@1 { 86 compatible = "arm,cortex-a53"; 87 reg = <1>; 88 device_type = "cpu"; 89 power-domains = <&sysc R8A774C0_PD_CA53_CPU1>; 90 next-level-cache = <&L2_CA53>; 91 enable-method = "psci"; 92 clocks = <&cpg CPG_CORE R8A774C0_CLK_Z2>; 93 operating-points-v2 = <&cluster1_opp>; 94 }; 95 96 L2_CA53: cache-controller-0 { 97 compatible = "cache"; 98 power-domains = <&sysc R8A774C0_PD_CA53_SCU>; 99 cache-unified; 100 cache-level = <2>; 101 }; 102 }; 103 104 extal_clk: extal { 105 compatible = "fixed-clock"; 106 #clock-cells = <0>; 107 /* This value must be overridden by the board */ 108 clock-frequency = <0>; 109 }; 110 111 /* External PCIe clock - can be overridden by the board */ 112 pcie_bus_clk: pcie_bus { 113 compatible = "fixed-clock"; 114 #clock-cells = <0>; 115 clock-frequency = <0>; 116 }; 117 118 pmu_a53 { 119 compatible = "arm,cortex-a53-pmu"; 120 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 121 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 122 interrupt-affinity = <&a53_0>, <&a53_1>; 123 }; 124 125 psci { 126 compatible = "arm,psci-1.0", "arm,psci-0.2"; 127 method = "smc"; 128 }; 129 130 /* External SCIF clock - to be overridden by boards that provide it */ 131 scif_clk: scif { 132 compatible = "fixed-clock"; 133 #clock-cells = <0>; 134 clock-frequency = <0>; 135 }; 136 137 soc: soc { 138 compatible = "simple-bus"; 139 interrupt-parent = <&gic>; 140 #address-cells = <2>; 141 #size-cells = <2>; 142 ranges; 143 144 rwdt: watchdog@e6020000 { 145 compatible = "renesas,r8a774c0-wdt", 146 "renesas,rcar-gen3-wdt"; 147 reg = <0 0xe6020000 0 0x0c>; 148 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 149 clocks = <&cpg CPG_MOD 402>; 150 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 151 resets = <&cpg 402>; 152 status = "disabled"; 153 }; 154 155 gpio0: gpio@e6050000 { 156 compatible = "renesas,gpio-r8a774c0", 157 "renesas,rcar-gen3-gpio"; 158 reg = <0 0xe6050000 0 0x50>; 159 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 160 #gpio-cells = <2>; 161 gpio-controller; 162 gpio-ranges = <&pfc 0 0 18>; 163 #interrupt-cells = <2>; 164 interrupt-controller; 165 clocks = <&cpg CPG_MOD 912>; 166 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 167 resets = <&cpg 912>; 168 }; 169 170 gpio1: gpio@e6051000 { 171 compatible = "renesas,gpio-r8a774c0", 172 "renesas,rcar-gen3-gpio"; 173 reg = <0 0xe6051000 0 0x50>; 174 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 175 #gpio-cells = <2>; 176 gpio-controller; 177 gpio-ranges = <&pfc 0 32 23>; 178 #interrupt-cells = <2>; 179 interrupt-controller; 180 clocks = <&cpg CPG_MOD 911>; 181 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 182 resets = <&cpg 911>; 183 }; 184 185 gpio2: gpio@e6052000 { 186 compatible = "renesas,gpio-r8a774c0", 187 "renesas,rcar-gen3-gpio"; 188 reg = <0 0xe6052000 0 0x50>; 189 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 190 #gpio-cells = <2>; 191 gpio-controller; 192 gpio-ranges = <&pfc 0 64 26>; 193 #interrupt-cells = <2>; 194 interrupt-controller; 195 clocks = <&cpg CPG_MOD 910>; 196 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 197 resets = <&cpg 910>; 198 }; 199 200 gpio3: gpio@e6053000 { 201 compatible = "renesas,gpio-r8a774c0", 202 "renesas,rcar-gen3-gpio"; 203 reg = <0 0xe6053000 0 0x50>; 204 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 205 #gpio-cells = <2>; 206 gpio-controller; 207 gpio-ranges = <&pfc 0 96 16>; 208 #interrupt-cells = <2>; 209 interrupt-controller; 210 clocks = <&cpg CPG_MOD 909>; 211 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 212 resets = <&cpg 909>; 213 }; 214 215 gpio4: gpio@e6054000 { 216 compatible = "renesas,gpio-r8a774c0", 217 "renesas,rcar-gen3-gpio"; 218 reg = <0 0xe6054000 0 0x50>; 219 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 220 #gpio-cells = <2>; 221 gpio-controller; 222 gpio-ranges = <&pfc 0 128 11>; 223 #interrupt-cells = <2>; 224 interrupt-controller; 225 clocks = <&cpg CPG_MOD 908>; 226 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 227 resets = <&cpg 908>; 228 }; 229 230 gpio5: gpio@e6055000 { 231 compatible = "renesas,gpio-r8a774c0", 232 "renesas,rcar-gen3-gpio"; 233 reg = <0 0xe6055000 0 0x50>; 234 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 235 #gpio-cells = <2>; 236 gpio-controller; 237 gpio-ranges = <&pfc 0 160 20>; 238 #interrupt-cells = <2>; 239 interrupt-controller; 240 clocks = <&cpg CPG_MOD 907>; 241 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 242 resets = <&cpg 907>; 243 }; 244 245 gpio6: gpio@e6055400 { 246 compatible = "renesas,gpio-r8a774c0", 247 "renesas,rcar-gen3-gpio"; 248 reg = <0 0xe6055400 0 0x50>; 249 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 250 #gpio-cells = <2>; 251 gpio-controller; 252 gpio-ranges = <&pfc 0 192 18>; 253 #interrupt-cells = <2>; 254 interrupt-controller; 255 clocks = <&cpg CPG_MOD 906>; 256 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 257 resets = <&cpg 906>; 258 }; 259 260 pfc: pinctrl@e6060000 { 261 compatible = "renesas,pfc-r8a774c0"; 262 reg = <0 0xe6060000 0 0x508>; 263 }; 264 265 cmt0: timer@e60f0000 { 266 compatible = "renesas,r8a774c0-cmt0", 267 "renesas,rcar-gen3-cmt0"; 268 reg = <0 0xe60f0000 0 0x1004>; 269 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&cpg CPG_MOD 303>; 272 clock-names = "fck"; 273 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 274 resets = <&cpg 303>; 275 status = "disabled"; 276 }; 277 278 cmt1: timer@e6130000 { 279 compatible = "renesas,r8a774c0-cmt1", 280 "renesas,rcar-gen3-cmt1"; 281 reg = <0 0xe6130000 0 0x1004>; 282 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&cpg CPG_MOD 302>; 291 clock-names = "fck"; 292 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 293 resets = <&cpg 302>; 294 status = "disabled"; 295 }; 296 297 cmt2: timer@e6140000 { 298 compatible = "renesas,r8a774c0-cmt1", 299 "renesas,rcar-gen3-cmt1"; 300 reg = <0 0xe6140000 0 0x1004>; 301 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&cpg CPG_MOD 301>; 310 clock-names = "fck"; 311 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 312 resets = <&cpg 301>; 313 status = "disabled"; 314 }; 315 316 cmt3: timer@e6148000 { 317 compatible = "renesas,r8a774c0-cmt1", 318 "renesas,rcar-gen3-cmt1"; 319 reg = <0 0xe6148000 0 0x1004>; 320 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 323 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 324 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 325 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 326 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; 328 clocks = <&cpg CPG_MOD 300>; 329 clock-names = "fck"; 330 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 331 resets = <&cpg 300>; 332 status = "disabled"; 333 }; 334 335 cpg: clock-controller@e6150000 { 336 compatible = "renesas,r8a774c0-cpg-mssr"; 337 reg = <0 0xe6150000 0 0x1000>; 338 clocks = <&extal_clk>; 339 clock-names = "extal"; 340 #clock-cells = <2>; 341 #power-domain-cells = <0>; 342 #reset-cells = <1>; 343 }; 344 345 rst: reset-controller@e6160000 { 346 compatible = "renesas,r8a774c0-rst"; 347 reg = <0 0xe6160000 0 0x0200>; 348 }; 349 350 sysc: system-controller@e6180000 { 351 compatible = "renesas,r8a774c0-sysc"; 352 reg = <0 0xe6180000 0 0x0400>; 353 #power-domain-cells = <1>; 354 }; 355 356 thermal: thermal@e6190000 { 357 compatible = "renesas,thermal-r8a774c0"; 358 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>; 359 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&cpg CPG_MOD 522>; 363 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 364 resets = <&cpg 522>; 365 #thermal-sensor-cells = <0>; 366 }; 367 368 intc_ex: interrupt-controller@e61c0000 { 369 compatible = "renesas,intc-ex-r8a774c0", "renesas,irqc"; 370 #interrupt-cells = <2>; 371 interrupt-controller; 372 reg = <0 0xe61c0000 0 0x200>; 373 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 377 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&cpg CPG_MOD 407>; 380 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 381 resets = <&cpg 407>; 382 }; 383 384 tmu0: timer@e61e0000 { 385 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 386 reg = <0 0xe61e0000 0 0x30>; 387 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 388 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 390 clocks = <&cpg CPG_MOD 125>; 391 clock-names = "fck"; 392 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 393 resets = <&cpg 125>; 394 status = "disabled"; 395 }; 396 397 tmu1: timer@e6fc0000 { 398 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 399 reg = <0 0xe6fc0000 0 0x30>; 400 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&cpg CPG_MOD 124>; 404 clock-names = "fck"; 405 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 406 resets = <&cpg 124>; 407 status = "disabled"; 408 }; 409 410 tmu2: timer@e6fd0000 { 411 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 412 reg = <0 0xe6fd0000 0 0x30>; 413 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 416 clocks = <&cpg CPG_MOD 123>; 417 clock-names = "fck"; 418 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 419 resets = <&cpg 123>; 420 status = "disabled"; 421 }; 422 423 tmu3: timer@e6fe0000 { 424 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 425 reg = <0 0xe6fe0000 0 0x30>; 426 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&cpg CPG_MOD 122>; 430 clock-names = "fck"; 431 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 432 resets = <&cpg 122>; 433 status = "disabled"; 434 }; 435 436 tmu4: timer@ffc00000 { 437 compatible = "renesas,tmu-r8a774c0", "renesas,tmu"; 438 reg = <0 0xffc00000 0 0x30>; 439 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&cpg CPG_MOD 121>; 443 clock-names = "fck"; 444 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 445 resets = <&cpg 121>; 446 status = "disabled"; 447 }; 448 449 i2c0: i2c@e6500000 { 450 #address-cells = <1>; 451 #size-cells = <0>; 452 compatible = "renesas,i2c-r8a774c0", 453 "renesas,rcar-gen3-i2c"; 454 reg = <0 0xe6500000 0 0x40>; 455 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&cpg CPG_MOD 931>; 457 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 458 resets = <&cpg 931>; 459 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 460 <&dmac2 0x91>, <&dmac2 0x90>; 461 dma-names = "tx", "rx", "tx", "rx"; 462 i2c-scl-internal-delay-ns = <110>; 463 status = "disabled"; 464 }; 465 466 i2c1: i2c@e6508000 { 467 #address-cells = <1>; 468 #size-cells = <0>; 469 compatible = "renesas,i2c-r8a774c0", 470 "renesas,rcar-gen3-i2c"; 471 reg = <0 0xe6508000 0 0x40>; 472 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&cpg CPG_MOD 930>; 474 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 475 resets = <&cpg 930>; 476 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 477 <&dmac2 0x93>, <&dmac2 0x92>; 478 dma-names = "tx", "rx", "tx", "rx"; 479 i2c-scl-internal-delay-ns = <6>; 480 status = "disabled"; 481 }; 482 483 i2c2: i2c@e6510000 { 484 #address-cells = <1>; 485 #size-cells = <0>; 486 compatible = "renesas,i2c-r8a774c0", 487 "renesas,rcar-gen3-i2c"; 488 reg = <0 0xe6510000 0 0x40>; 489 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&cpg CPG_MOD 929>; 491 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 492 resets = <&cpg 929>; 493 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 494 <&dmac2 0x95>, <&dmac2 0x94>; 495 dma-names = "tx", "rx", "tx", "rx"; 496 i2c-scl-internal-delay-ns = <6>; 497 status = "disabled"; 498 }; 499 500 i2c3: i2c@e66d0000 { 501 #address-cells = <1>; 502 #size-cells = <0>; 503 compatible = "renesas,i2c-r8a774c0", 504 "renesas,rcar-gen3-i2c"; 505 reg = <0 0xe66d0000 0 0x40>; 506 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&cpg CPG_MOD 928>; 508 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 509 resets = <&cpg 928>; 510 dmas = <&dmac0 0x97>, <&dmac0 0x96>; 511 dma-names = "tx", "rx"; 512 i2c-scl-internal-delay-ns = <110>; 513 status = "disabled"; 514 }; 515 516 i2c4: i2c@e66d8000 { 517 #address-cells = <1>; 518 #size-cells = <0>; 519 compatible = "renesas,i2c-r8a774c0", 520 "renesas,rcar-gen3-i2c"; 521 reg = <0 0xe66d8000 0 0x40>; 522 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 523 clocks = <&cpg CPG_MOD 927>; 524 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 525 resets = <&cpg 927>; 526 dmas = <&dmac0 0x99>, <&dmac0 0x98>; 527 dma-names = "tx", "rx"; 528 i2c-scl-internal-delay-ns = <6>; 529 status = "disabled"; 530 }; 531 532 i2c5: i2c@e66e0000 { 533 #address-cells = <1>; 534 #size-cells = <0>; 535 compatible = "renesas,i2c-r8a774c0", 536 "renesas,rcar-gen3-i2c"; 537 reg = <0 0xe66e0000 0 0x40>; 538 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 539 clocks = <&cpg CPG_MOD 919>; 540 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 541 resets = <&cpg 919>; 542 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; 543 dma-names = "tx", "rx"; 544 i2c-scl-internal-delay-ns = <6>; 545 status = "disabled"; 546 }; 547 548 i2c6: i2c@e66e8000 { 549 #address-cells = <1>; 550 #size-cells = <0>; 551 compatible = "renesas,i2c-r8a774c0", 552 "renesas,rcar-gen3-i2c"; 553 reg = <0 0xe66e8000 0 0x40>; 554 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&cpg CPG_MOD 918>; 556 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 557 resets = <&cpg 918>; 558 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; 559 dma-names = "tx", "rx"; 560 i2c-scl-internal-delay-ns = <6>; 561 status = "disabled"; 562 }; 563 564 i2c7: i2c@e6690000 { 565 #address-cells = <1>; 566 #size-cells = <0>; 567 compatible = "renesas,i2c-r8a774c0", 568 "renesas,rcar-gen3-i2c"; 569 reg = <0 0xe6690000 0 0x40>; 570 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 571 clocks = <&cpg CPG_MOD 1003>; 572 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 573 resets = <&cpg 1003>; 574 i2c-scl-internal-delay-ns = <6>; 575 status = "disabled"; 576 }; 577 578 iic_pmic: i2c@e60b0000 { 579 #address-cells = <1>; 580 #size-cells = <0>; 581 compatible = "renesas,iic-r8a774c0", 582 "renesas,rcar-gen3-iic", 583 "renesas,rmobile-iic"; 584 reg = <0 0xe60b0000 0 0x425>; 585 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&cpg CPG_MOD 926>; 587 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 588 resets = <&cpg 926>; 589 dmas = <&dmac0 0x11>, <&dmac0 0x10>; 590 dma-names = "tx", "rx"; 591 status = "disabled"; 592 }; 593 594 hscif0: serial@e6540000 { 595 compatible = "renesas,hscif-r8a774c0", 596 "renesas,rcar-gen3-hscif", 597 "renesas,hscif"; 598 reg = <0 0xe6540000 0 0x60>; 599 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 600 clocks = <&cpg CPG_MOD 520>, 601 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 602 <&scif_clk>; 603 clock-names = "fck", "brg_int", "scif_clk"; 604 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 605 <&dmac2 0x31>, <&dmac2 0x30>; 606 dma-names = "tx", "rx", "tx", "rx"; 607 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 608 resets = <&cpg 520>; 609 status = "disabled"; 610 }; 611 612 hscif1: serial@e6550000 { 613 compatible = "renesas,hscif-r8a774c0", 614 "renesas,rcar-gen3-hscif", 615 "renesas,hscif"; 616 reg = <0 0xe6550000 0 0x60>; 617 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 618 clocks = <&cpg CPG_MOD 519>, 619 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 620 <&scif_clk>; 621 clock-names = "fck", "brg_int", "scif_clk"; 622 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 623 <&dmac2 0x33>, <&dmac2 0x32>; 624 dma-names = "tx", "rx", "tx", "rx"; 625 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 626 resets = <&cpg 519>; 627 status = "disabled"; 628 }; 629 630 hscif2: serial@e6560000 { 631 compatible = "renesas,hscif-r8a774c0", 632 "renesas,rcar-gen3-hscif", 633 "renesas,hscif"; 634 reg = <0 0xe6560000 0 0x60>; 635 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&cpg CPG_MOD 518>, 637 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 638 <&scif_clk>; 639 clock-names = "fck", "brg_int", "scif_clk"; 640 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 641 <&dmac2 0x35>, <&dmac2 0x34>; 642 dma-names = "tx", "rx", "tx", "rx"; 643 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 644 resets = <&cpg 518>; 645 status = "disabled"; 646 }; 647 648 hscif3: serial@e66a0000 { 649 compatible = "renesas,hscif-r8a774c0", 650 "renesas,rcar-gen3-hscif", 651 "renesas,hscif"; 652 reg = <0 0xe66a0000 0 0x60>; 653 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&cpg CPG_MOD 517>, 655 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 656 <&scif_clk>; 657 clock-names = "fck", "brg_int", "scif_clk"; 658 dmas = <&dmac0 0x37>, <&dmac0 0x36>; 659 dma-names = "tx", "rx"; 660 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 661 resets = <&cpg 517>; 662 status = "disabled"; 663 }; 664 665 hscif4: serial@e66b0000 { 666 compatible = "renesas,hscif-r8a774c0", 667 "renesas,rcar-gen3-hscif", 668 "renesas,hscif"; 669 reg = <0 0xe66b0000 0 0x60>; 670 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&cpg CPG_MOD 516>, 672 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 673 <&scif_clk>; 674 clock-names = "fck", "brg_int", "scif_clk"; 675 dmas = <&dmac0 0x39>, <&dmac0 0x38>; 676 dma-names = "tx", "rx"; 677 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 678 resets = <&cpg 516>; 679 status = "disabled"; 680 }; 681 682 hsusb: usb@e6590000 { 683 compatible = "renesas,usbhs-r8a774c0", 684 "renesas,rcar-gen3-usbhs"; 685 reg = <0 0xe6590000 0 0x200>; 686 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; 688 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, 689 <&usb_dmac1 0>, <&usb_dmac1 1>; 690 dma-names = "ch0", "ch1", "ch2", "ch3"; 691 renesas,buswait = <11>; 692 phys = <&usb2_phy0 3>; 693 phy-names = "usb"; 694 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 695 resets = <&cpg 704>, <&cpg 703>; 696 status = "disabled"; 697 }; 698 699 usb_dmac0: dma-controller@e65a0000 { 700 compatible = "renesas,r8a774c0-usb-dmac", 701 "renesas,usb-dmac"; 702 reg = <0 0xe65a0000 0 0x100>; 703 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 705 interrupt-names = "ch0", "ch1"; 706 clocks = <&cpg CPG_MOD 330>; 707 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 708 resets = <&cpg 330>; 709 #dma-cells = <1>; 710 dma-channels = <2>; 711 }; 712 713 usb_dmac1: dma-controller@e65b0000 { 714 compatible = "renesas,r8a774c0-usb-dmac", 715 "renesas,usb-dmac"; 716 reg = <0 0xe65b0000 0 0x100>; 717 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 719 interrupt-names = "ch0", "ch1"; 720 clocks = <&cpg CPG_MOD 331>; 721 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 722 resets = <&cpg 331>; 723 #dma-cells = <1>; 724 dma-channels = <2>; 725 }; 726 727 dmac0: dma-controller@e6700000 { 728 compatible = "renesas,dmac-r8a774c0", 729 "renesas,rcar-dmac"; 730 reg = <0 0xe6700000 0 0x10000>; 731 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 748 interrupt-names = "error", 749 "ch0", "ch1", "ch2", "ch3", 750 "ch4", "ch5", "ch6", "ch7", 751 "ch8", "ch9", "ch10", "ch11", 752 "ch12", "ch13", "ch14", "ch15"; 753 clocks = <&cpg CPG_MOD 219>; 754 clock-names = "fck"; 755 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 756 resets = <&cpg 219>; 757 #dma-cells = <1>; 758 dma-channels = <16>; 759 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 760 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 761 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 762 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 763 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 764 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 765 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 766 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 767 }; 768 769 dmac1: dma-controller@e7300000 { 770 compatible = "renesas,dmac-r8a774c0", 771 "renesas,rcar-dmac"; 772 reg = <0 0xe7300000 0 0x10000>; 773 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 790 interrupt-names = "error", 791 "ch0", "ch1", "ch2", "ch3", 792 "ch4", "ch5", "ch6", "ch7", 793 "ch8", "ch9", "ch10", "ch11", 794 "ch12", "ch13", "ch14", "ch15"; 795 clocks = <&cpg CPG_MOD 218>; 796 clock-names = "fck"; 797 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 798 resets = <&cpg 218>; 799 #dma-cells = <1>; 800 dma-channels = <16>; 801 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 802 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 803 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 804 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 805 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 806 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 807 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 808 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 809 }; 810 811 dmac2: dma-controller@e7310000 { 812 compatible = "renesas,dmac-r8a774c0", 813 "renesas,rcar-dmac"; 814 reg = <0 0xe7310000 0 0x10000>; 815 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 816 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 832 interrupt-names = "error", 833 "ch0", "ch1", "ch2", "ch3", 834 "ch4", "ch5", "ch6", "ch7", 835 "ch8", "ch9", "ch10", "ch11", 836 "ch12", "ch13", "ch14", "ch15"; 837 clocks = <&cpg CPG_MOD 217>; 838 clock-names = "fck"; 839 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 840 resets = <&cpg 217>; 841 #dma-cells = <1>; 842 dma-channels = <16>; 843 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 844 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 845 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 846 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 847 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 848 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 849 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 850 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 851 }; 852 853 ipmmu_ds0: iommu@e6740000 { 854 compatible = "renesas,ipmmu-r8a774c0"; 855 reg = <0 0xe6740000 0 0x1000>; 856 renesas,ipmmu-main = <&ipmmu_mm 0>; 857 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 858 #iommu-cells = <1>; 859 }; 860 861 ipmmu_ds1: iommu@e7740000 { 862 compatible = "renesas,ipmmu-r8a774c0"; 863 reg = <0 0xe7740000 0 0x1000>; 864 renesas,ipmmu-main = <&ipmmu_mm 1>; 865 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 866 #iommu-cells = <1>; 867 }; 868 869 ipmmu_hc: iommu@e6570000 { 870 compatible = "renesas,ipmmu-r8a774c0"; 871 reg = <0 0xe6570000 0 0x1000>; 872 renesas,ipmmu-main = <&ipmmu_mm 2>; 873 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 874 #iommu-cells = <1>; 875 }; 876 877 ipmmu_mm: iommu@e67b0000 { 878 compatible = "renesas,ipmmu-r8a774c0"; 879 reg = <0 0xe67b0000 0 0x1000>; 880 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 882 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 883 #iommu-cells = <1>; 884 }; 885 886 ipmmu_mp: iommu@ec670000 { 887 compatible = "renesas,ipmmu-r8a774c0"; 888 reg = <0 0xec670000 0 0x1000>; 889 renesas,ipmmu-main = <&ipmmu_mm 4>; 890 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 891 #iommu-cells = <1>; 892 }; 893 894 ipmmu_pv0: iommu@fd800000 { 895 compatible = "renesas,ipmmu-r8a774c0"; 896 reg = <0 0xfd800000 0 0x1000>; 897 renesas,ipmmu-main = <&ipmmu_mm 6>; 898 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 899 #iommu-cells = <1>; 900 }; 901 902 ipmmu_vc0: iommu@fe6b0000 { 903 compatible = "renesas,ipmmu-r8a774c0"; 904 reg = <0 0xfe6b0000 0 0x1000>; 905 renesas,ipmmu-main = <&ipmmu_mm 12>; 906 power-domains = <&sysc R8A774C0_PD_A3VC>; 907 #iommu-cells = <1>; 908 }; 909 910 ipmmu_vi0: iommu@febd0000 { 911 compatible = "renesas,ipmmu-r8a774c0"; 912 reg = <0 0xfebd0000 0 0x1000>; 913 renesas,ipmmu-main = <&ipmmu_mm 14>; 914 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 915 #iommu-cells = <1>; 916 }; 917 918 ipmmu_vp0: iommu@fe990000 { 919 compatible = "renesas,ipmmu-r8a774c0"; 920 reg = <0 0xfe990000 0 0x1000>; 921 renesas,ipmmu-main = <&ipmmu_mm 16>; 922 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 923 #iommu-cells = <1>; 924 }; 925 926 avb: ethernet@e6800000 { 927 compatible = "renesas,etheravb-r8a774c0", 928 "renesas,etheravb-rcar-gen3"; 929 reg = <0 0xe6800000 0 0x800>; 930 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 955 interrupt-names = "ch0", "ch1", "ch2", "ch3", 956 "ch4", "ch5", "ch6", "ch7", 957 "ch8", "ch9", "ch10", "ch11", 958 "ch12", "ch13", "ch14", "ch15", 959 "ch16", "ch17", "ch18", "ch19", 960 "ch20", "ch21", "ch22", "ch23", 961 "ch24"; 962 clocks = <&cpg CPG_MOD 812>; 963 clock-names = "fck"; 964 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 965 resets = <&cpg 812>; 966 phy-mode = "rgmii"; 967 rx-internal-delay-ps = <0>; 968 iommus = <&ipmmu_ds0 16>; 969 #address-cells = <1>; 970 #size-cells = <0>; 971 status = "disabled"; 972 }; 973 974 can0: can@e6c30000 { 975 compatible = "renesas,can-r8a774c0", 976 "renesas,rcar-gen3-can"; 977 reg = <0 0xe6c30000 0 0x1000>; 978 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&cpg CPG_MOD 916>, 980 <&cpg CPG_CORE R8A774C0_CLK_CANFD>, 981 <&can_clk>; 982 clock-names = "clkp1", "clkp2", "can_clk"; 983 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; 984 assigned-clock-rates = <40000000>; 985 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 986 resets = <&cpg 916>; 987 status = "disabled"; 988 }; 989 990 can1: can@e6c38000 { 991 compatible = "renesas,can-r8a774c0", 992 "renesas,rcar-gen3-can"; 993 reg = <0 0xe6c38000 0 0x1000>; 994 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 995 clocks = <&cpg CPG_MOD 915>, 996 <&cpg CPG_CORE R8A774C0_CLK_CANFD>, 997 <&can_clk>; 998 clock-names = "clkp1", "clkp2", "can_clk"; 999 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; 1000 assigned-clock-rates = <40000000>; 1001 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1002 resets = <&cpg 915>; 1003 status = "disabled"; 1004 }; 1005 1006 canfd: can@e66c0000 { 1007 compatible = "renesas,r8a774c0-canfd", 1008 "renesas,rcar-gen3-canfd"; 1009 reg = <0 0xe66c0000 0 0x8000>; 1010 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1011 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1012 interrupt-names = "ch_int", "g_int"; 1013 clocks = <&cpg CPG_MOD 914>, 1014 <&cpg CPG_CORE R8A774C0_CLK_CANFD>, 1015 <&can_clk>; 1016 clock-names = "fck", "canfd", "can_clk"; 1017 assigned-clocks = <&cpg CPG_CORE R8A774C0_CLK_CANFD>; 1018 assigned-clock-rates = <40000000>; 1019 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1020 resets = <&cpg 914>; 1021 status = "disabled"; 1022 1023 channel0 { 1024 status = "disabled"; 1025 }; 1026 1027 channel1 { 1028 status = "disabled"; 1029 }; 1030 }; 1031 1032 pwm0: pwm@e6e30000 { 1033 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1034 reg = <0 0xe6e30000 0 0x8>; 1035 clocks = <&cpg CPG_MOD 523>; 1036 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1037 resets = <&cpg 523>; 1038 #pwm-cells = <2>; 1039 status = "disabled"; 1040 }; 1041 1042 pwm1: pwm@e6e31000 { 1043 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1044 reg = <0 0xe6e31000 0 0x8>; 1045 clocks = <&cpg CPG_MOD 523>; 1046 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1047 resets = <&cpg 523>; 1048 #pwm-cells = <2>; 1049 status = "disabled"; 1050 }; 1051 1052 pwm2: pwm@e6e32000 { 1053 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1054 reg = <0 0xe6e32000 0 0x8>; 1055 clocks = <&cpg CPG_MOD 523>; 1056 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1057 resets = <&cpg 523>; 1058 #pwm-cells = <2>; 1059 status = "disabled"; 1060 }; 1061 1062 pwm3: pwm@e6e33000 { 1063 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1064 reg = <0 0xe6e33000 0 0x8>; 1065 clocks = <&cpg CPG_MOD 523>; 1066 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1067 resets = <&cpg 523>; 1068 #pwm-cells = <2>; 1069 status = "disabled"; 1070 }; 1071 1072 pwm4: pwm@e6e34000 { 1073 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1074 reg = <0 0xe6e34000 0 0x8>; 1075 clocks = <&cpg CPG_MOD 523>; 1076 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1077 resets = <&cpg 523>; 1078 #pwm-cells = <2>; 1079 status = "disabled"; 1080 }; 1081 1082 pwm5: pwm@e6e35000 { 1083 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1084 reg = <0 0xe6e35000 0 0x8>; 1085 clocks = <&cpg CPG_MOD 523>; 1086 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1087 resets = <&cpg 523>; 1088 #pwm-cells = <2>; 1089 status = "disabled"; 1090 }; 1091 1092 pwm6: pwm@e6e36000 { 1093 compatible = "renesas,pwm-r8a774c0", "renesas,pwm-rcar"; 1094 reg = <0 0xe6e36000 0 0x8>; 1095 clocks = <&cpg CPG_MOD 523>; 1096 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1097 resets = <&cpg 523>; 1098 #pwm-cells = <2>; 1099 status = "disabled"; 1100 }; 1101 1102 scif0: serial@e6e60000 { 1103 compatible = "renesas,scif-r8a774c0", 1104 "renesas,rcar-gen3-scif", "renesas,scif"; 1105 reg = <0 0xe6e60000 0 64>; 1106 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1107 clocks = <&cpg CPG_MOD 207>, 1108 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1109 <&scif_clk>; 1110 clock-names = "fck", "brg_int", "scif_clk"; 1111 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 1112 <&dmac2 0x51>, <&dmac2 0x50>; 1113 dma-names = "tx", "rx", "tx", "rx"; 1114 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1115 resets = <&cpg 207>; 1116 status = "disabled"; 1117 }; 1118 1119 scif1: serial@e6e68000 { 1120 compatible = "renesas,scif-r8a774c0", 1121 "renesas,rcar-gen3-scif", "renesas,scif"; 1122 reg = <0 0xe6e68000 0 64>; 1123 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1124 clocks = <&cpg CPG_MOD 206>, 1125 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1126 <&scif_clk>; 1127 clock-names = "fck", "brg_int", "scif_clk"; 1128 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 1129 <&dmac2 0x53>, <&dmac2 0x52>; 1130 dma-names = "tx", "rx", "tx", "rx"; 1131 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1132 resets = <&cpg 206>; 1133 status = "disabled"; 1134 }; 1135 1136 scif2: serial@e6e88000 { 1137 compatible = "renesas,scif-r8a774c0", 1138 "renesas,rcar-gen3-scif", "renesas,scif"; 1139 reg = <0 0xe6e88000 0 64>; 1140 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 1141 clocks = <&cpg CPG_MOD 310>, 1142 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1143 <&scif_clk>; 1144 clock-names = "fck", "brg_int", "scif_clk"; 1145 dmas = <&dmac1 0x13>, <&dmac1 0x12>, 1146 <&dmac2 0x13>, <&dmac2 0x12>; 1147 dma-names = "tx", "rx", "tx", "rx"; 1148 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1149 resets = <&cpg 310>; 1150 status = "disabled"; 1151 }; 1152 1153 scif3: serial@e6c50000 { 1154 compatible = "renesas,scif-r8a774c0", 1155 "renesas,rcar-gen3-scif", "renesas,scif"; 1156 reg = <0 0xe6c50000 0 64>; 1157 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1158 clocks = <&cpg CPG_MOD 204>, 1159 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1160 <&scif_clk>; 1161 clock-names = "fck", "brg_int", "scif_clk"; 1162 dmas = <&dmac0 0x57>, <&dmac0 0x56>; 1163 dma-names = "tx", "rx"; 1164 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1165 resets = <&cpg 204>; 1166 status = "disabled"; 1167 }; 1168 1169 scif4: serial@e6c40000 { 1170 compatible = "renesas,scif-r8a774c0", 1171 "renesas,rcar-gen3-scif", "renesas,scif"; 1172 reg = <0 0xe6c40000 0 64>; 1173 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1174 clocks = <&cpg CPG_MOD 203>, 1175 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1176 <&scif_clk>; 1177 clock-names = "fck", "brg_int", "scif_clk"; 1178 dmas = <&dmac0 0x59>, <&dmac0 0x58>; 1179 dma-names = "tx", "rx"; 1180 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1181 resets = <&cpg 203>; 1182 status = "disabled"; 1183 }; 1184 1185 scif5: serial@e6f30000 { 1186 compatible = "renesas,scif-r8a774c0", 1187 "renesas,rcar-gen3-scif", "renesas,scif"; 1188 reg = <0 0xe6f30000 0 64>; 1189 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1190 clocks = <&cpg CPG_MOD 202>, 1191 <&cpg CPG_CORE R8A774C0_CLK_S3D1C>, 1192 <&scif_clk>; 1193 clock-names = "fck", "brg_int", "scif_clk"; 1194 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>; 1195 dma-names = "tx", "rx"; 1196 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1197 resets = <&cpg 202>; 1198 status = "disabled"; 1199 }; 1200 1201 msiof0: spi@e6e90000 { 1202 compatible = "renesas,msiof-r8a774c0", 1203 "renesas,rcar-gen3-msiof"; 1204 reg = <0 0xe6e90000 0 0x0064>; 1205 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1206 clocks = <&cpg CPG_MOD 211>; 1207 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1208 <&dmac2 0x41>, <&dmac2 0x40>; 1209 dma-names = "tx", "rx", "tx", "rx"; 1210 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1211 resets = <&cpg 211>; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 status = "disabled"; 1215 }; 1216 1217 msiof1: spi@e6ea0000 { 1218 compatible = "renesas,msiof-r8a774c0", 1219 "renesas,rcar-gen3-msiof"; 1220 reg = <0 0xe6ea0000 0 0x0064>; 1221 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1222 clocks = <&cpg CPG_MOD 210>; 1223 dmas = <&dmac0 0x43>, <&dmac0 0x42>; 1224 dma-names = "tx", "rx"; 1225 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1226 resets = <&cpg 210>; 1227 #address-cells = <1>; 1228 #size-cells = <0>; 1229 status = "disabled"; 1230 }; 1231 1232 msiof2: spi@e6c00000 { 1233 compatible = "renesas,msiof-r8a774c0", 1234 "renesas,rcar-gen3-msiof"; 1235 reg = <0 0xe6c00000 0 0x0064>; 1236 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1237 clocks = <&cpg CPG_MOD 209>; 1238 dmas = <&dmac0 0x45>, <&dmac0 0x44>; 1239 dma-names = "tx", "rx"; 1240 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1241 resets = <&cpg 209>; 1242 #address-cells = <1>; 1243 #size-cells = <0>; 1244 status = "disabled"; 1245 }; 1246 1247 msiof3: spi@e6c10000 { 1248 compatible = "renesas,msiof-r8a774c0", 1249 "renesas,rcar-gen3-msiof"; 1250 reg = <0 0xe6c10000 0 0x0064>; 1251 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 1252 clocks = <&cpg CPG_MOD 208>; 1253 dmas = <&dmac0 0x47>, <&dmac0 0x46>; 1254 dma-names = "tx", "rx"; 1255 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1256 resets = <&cpg 208>; 1257 #address-cells = <1>; 1258 #size-cells = <0>; 1259 status = "disabled"; 1260 }; 1261 1262 vin4: video@e6ef4000 { 1263 compatible = "renesas,vin-r8a774c0"; 1264 reg = <0 0xe6ef4000 0 0x1000>; 1265 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1266 clocks = <&cpg CPG_MOD 807>; 1267 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1268 resets = <&cpg 807>; 1269 renesas,id = <4>; 1270 status = "disabled"; 1271 1272 ports { 1273 #address-cells = <1>; 1274 #size-cells = <0>; 1275 1276 port@1 { 1277 #address-cells = <1>; 1278 #size-cells = <0>; 1279 1280 reg = <1>; 1281 1282 vin4csi40: endpoint@2 { 1283 reg = <2>; 1284 remote-endpoint = <&csi40vin4>; 1285 }; 1286 }; 1287 }; 1288 }; 1289 1290 vin5: video@e6ef5000 { 1291 compatible = "renesas,vin-r8a774c0"; 1292 reg = <0 0xe6ef5000 0 0x1000>; 1293 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1294 clocks = <&cpg CPG_MOD 806>; 1295 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1296 resets = <&cpg 806>; 1297 renesas,id = <5>; 1298 status = "disabled"; 1299 1300 ports { 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 1304 port@1 { 1305 #address-cells = <1>; 1306 #size-cells = <0>; 1307 1308 reg = <1>; 1309 1310 vin5csi40: endpoint@2 { 1311 reg = <2>; 1312 remote-endpoint = <&csi40vin5>; 1313 }; 1314 }; 1315 }; 1316 }; 1317 1318 rcar_sound: sound@ec500000 { 1319 /* 1320 * #sound-dai-cells is required if simple-card 1321 * 1322 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; 1323 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; 1324 */ 1325 /* 1326 * #clock-cells is required for audio_clkout0/1/2/3 1327 * 1328 * clkout : #clock-cells = <0>; <&rcar_sound>; 1329 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; 1330 */ 1331 compatible = "renesas,rcar_sound-r8a774c0", 1332 "renesas,rcar_sound-gen3"; 1333 reg = <0 0xec500000 0 0x1000>, /* SCU */ 1334 <0 0xec5a0000 0 0x100>, /* ADG */ 1335 <0 0xec540000 0 0x1000>, /* SSIU */ 1336 <0 0xec541000 0 0x280>, /* SSI */ 1337 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ 1338 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; 1339 1340 clocks = <&cpg CPG_MOD 1005>, 1341 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 1342 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 1343 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 1344 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 1345 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 1346 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 1347 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 1348 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 1349 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 1350 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 1351 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1352 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 1353 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 1354 <&audio_clk_a>, <&audio_clk_b>, 1355 <&audio_clk_c>, 1356 <&cpg CPG_CORE R8A774C0_CLK_ZA2>; 1357 clock-names = "ssi-all", 1358 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1359 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1360 "ssi.1", "ssi.0", 1361 "src.9", "src.8", "src.7", "src.6", 1362 "src.5", "src.4", "src.3", "src.2", 1363 "src.1", "src.0", 1364 "mix.1", "mix.0", 1365 "ctu.1", "ctu.0", 1366 "dvc.0", "dvc.1", 1367 "clk_a", "clk_b", "clk_c", "clk_i"; 1368 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1369 resets = <&cpg 1005>, 1370 <&cpg 1006>, <&cpg 1007>, 1371 <&cpg 1008>, <&cpg 1009>, 1372 <&cpg 1010>, <&cpg 1011>, 1373 <&cpg 1012>, <&cpg 1013>, 1374 <&cpg 1014>, <&cpg 1015>; 1375 reset-names = "ssi-all", 1376 "ssi.9", "ssi.8", "ssi.7", "ssi.6", 1377 "ssi.5", "ssi.4", "ssi.3", "ssi.2", 1378 "ssi.1", "ssi.0"; 1379 status = "disabled"; 1380 1381 rcar_sound,ctu { 1382 ctu00: ctu-0 { }; 1383 ctu01: ctu-1 { }; 1384 ctu02: ctu-2 { }; 1385 ctu03: ctu-3 { }; 1386 ctu10: ctu-4 { }; 1387 ctu11: ctu-5 { }; 1388 ctu12: ctu-6 { }; 1389 ctu13: ctu-7 { }; 1390 }; 1391 1392 rcar_sound,dvc { 1393 dvc0: dvc-0 { 1394 dmas = <&audma0 0xbc>; 1395 dma-names = "tx"; 1396 }; 1397 dvc1: dvc-1 { 1398 dmas = <&audma0 0xbe>; 1399 dma-names = "tx"; 1400 }; 1401 }; 1402 1403 rcar_sound,mix { 1404 mix0: mix-0 { }; 1405 mix1: mix-1 { }; 1406 }; 1407 1408 rcar_sound,src { 1409 src0: src-0 { 1410 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 1411 dmas = <&audma0 0x85>, <&audma0 0x9a>; 1412 dma-names = "rx", "tx"; 1413 }; 1414 src1: src-1 { 1415 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1416 dmas = <&audma0 0x87>, <&audma0 0x9c>; 1417 dma-names = "rx", "tx"; 1418 }; 1419 src2: src-2 { 1420 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1421 dmas = <&audma0 0x89>, <&audma0 0x9e>; 1422 dma-names = "rx", "tx"; 1423 }; 1424 src3: src-3 { 1425 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1426 dmas = <&audma0 0x8b>, <&audma0 0xa0>; 1427 dma-names = "rx", "tx"; 1428 }; 1429 src4: src-4 { 1430 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1431 dmas = <&audma0 0x8d>, <&audma0 0xb0>; 1432 dma-names = "rx", "tx"; 1433 }; 1434 src5: src-5 { 1435 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1436 dmas = <&audma0 0x8f>, <&audma0 0xb2>; 1437 dma-names = "rx", "tx"; 1438 }; 1439 src6: src-6 { 1440 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1441 dmas = <&audma0 0x91>, <&audma0 0xb4>; 1442 dma-names = "rx", "tx"; 1443 }; 1444 src7: src-7 { 1445 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1446 dmas = <&audma0 0x93>, <&audma0 0xb6>; 1447 dma-names = "rx", "tx"; 1448 }; 1449 src8: src-8 { 1450 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1451 dmas = <&audma0 0x95>, <&audma0 0xb8>; 1452 dma-names = "rx", "tx"; 1453 }; 1454 src9: src-9 { 1455 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 1456 dmas = <&audma0 0x97>, <&audma0 0xba>; 1457 dma-names = "rx", "tx"; 1458 }; 1459 }; 1460 1461 rcar_sound,ssi { 1462 ssi0: ssi-0 { 1463 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 1464 dmas = <&audma0 0x01>, <&audma0 0x02>, 1465 <&audma0 0x15>, <&audma0 0x16>; 1466 dma-names = "rx", "tx", "rxu", "txu"; 1467 }; 1468 ssi1: ssi-1 { 1469 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 1470 dmas = <&audma0 0x03>, <&audma0 0x04>, 1471 <&audma0 0x49>, <&audma0 0x4a>; 1472 dma-names = "rx", "tx", "rxu", "txu"; 1473 }; 1474 ssi2: ssi-2 { 1475 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; 1476 dmas = <&audma0 0x05>, <&audma0 0x06>, 1477 <&audma0 0x63>, <&audma0 0x64>; 1478 dma-names = "rx", "tx", "rxu", "txu"; 1479 }; 1480 ssi3: ssi-3 { 1481 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1482 dmas = <&audma0 0x07>, <&audma0 0x08>, 1483 <&audma0 0x6f>, <&audma0 0x70>; 1484 dma-names = "rx", "tx", "rxu", "txu"; 1485 }; 1486 ssi4: ssi-4 { 1487 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 1488 dmas = <&audma0 0x09>, <&audma0 0x0a>, 1489 <&audma0 0x71>, <&audma0 0x72>; 1490 dma-names = "rx", "tx", "rxu", "txu"; 1491 }; 1492 ssi5: ssi-5 { 1493 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1494 dmas = <&audma0 0x0b>, <&audma0 0x0c>, 1495 <&audma0 0x73>, <&audma0 0x74>; 1496 dma-names = "rx", "tx", "rxu", "txu"; 1497 }; 1498 ssi6: ssi-6 { 1499 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 1500 dmas = <&audma0 0x0d>, <&audma0 0x0e>, 1501 <&audma0 0x75>, <&audma0 0x76>; 1502 dma-names = "rx", "tx", "rxu", "txu"; 1503 }; 1504 ssi7: ssi-7 { 1505 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; 1506 dmas = <&audma0 0x0f>, <&audma0 0x10>, 1507 <&audma0 0x79>, <&audma0 0x7a>; 1508 dma-names = "rx", "tx", "rxu", "txu"; 1509 }; 1510 ssi8: ssi-8 { 1511 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; 1512 dmas = <&audma0 0x11>, <&audma0 0x12>, 1513 <&audma0 0x7b>, <&audma0 0x7c>; 1514 dma-names = "rx", "tx", "rxu", "txu"; 1515 }; 1516 ssi9: ssi-9 { 1517 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 1518 dmas = <&audma0 0x13>, <&audma0 0x14>, 1519 <&audma0 0x7d>, <&audma0 0x7e>; 1520 dma-names = "rx", "tx", "rxu", "txu"; 1521 }; 1522 }; 1523 }; 1524 1525 audma0: dma-controller@ec700000 { 1526 compatible = "renesas,dmac-r8a774c0", 1527 "renesas,rcar-dmac"; 1528 reg = <0 0xec700000 0 0x10000>; 1529 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1530 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1531 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1532 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1540 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1544 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 1546 interrupt-names = "error", 1547 "ch0", "ch1", "ch2", "ch3", 1548 "ch4", "ch5", "ch6", "ch7", 1549 "ch8", "ch9", "ch10", "ch11", 1550 "ch12", "ch13", "ch14", "ch15"; 1551 clocks = <&cpg CPG_MOD 502>; 1552 clock-names = "fck"; 1553 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1554 resets = <&cpg 502>; 1555 #dma-cells = <1>; 1556 dma-channels = <16>; 1557 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>, 1558 <&ipmmu_mp 2>, <&ipmmu_mp 3>, 1559 <&ipmmu_mp 4>, <&ipmmu_mp 5>, 1560 <&ipmmu_mp 6>, <&ipmmu_mp 7>, 1561 <&ipmmu_mp 8>, <&ipmmu_mp 9>, 1562 <&ipmmu_mp 10>, <&ipmmu_mp 11>, 1563 <&ipmmu_mp 12>, <&ipmmu_mp 13>, 1564 <&ipmmu_mp 14>, <&ipmmu_mp 15>; 1565 }; 1566 1567 xhci0: usb@ee000000 { 1568 compatible = "renesas,xhci-r8a774c0", 1569 "renesas,rcar-gen3-xhci"; 1570 reg = <0 0xee000000 0 0xc00>; 1571 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1572 clocks = <&cpg CPG_MOD 328>; 1573 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1574 resets = <&cpg 328>; 1575 status = "disabled"; 1576 }; 1577 1578 usb3_peri0: usb@ee020000 { 1579 compatible = "renesas,r8a774c0-usb3-peri", 1580 "renesas,rcar-gen3-usb3-peri"; 1581 reg = <0 0xee020000 0 0x400>; 1582 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1583 clocks = <&cpg CPG_MOD 328>; 1584 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1585 resets = <&cpg 328>; 1586 status = "disabled"; 1587 }; 1588 1589 ohci0: usb@ee080000 { 1590 compatible = "generic-ohci"; 1591 reg = <0 0xee080000 0 0x100>; 1592 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1593 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1594 phys = <&usb2_phy0 1>; 1595 phy-names = "usb"; 1596 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1597 resets = <&cpg 703>, <&cpg 704>; 1598 status = "disabled"; 1599 }; 1600 1601 ehci0: usb@ee080100 { 1602 compatible = "generic-ehci"; 1603 reg = <0 0xee080100 0 0x100>; 1604 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1605 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1606 phys = <&usb2_phy0 2>; 1607 phy-names = "usb"; 1608 companion = <&ohci0>; 1609 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1610 resets = <&cpg 703>, <&cpg 704>; 1611 status = "disabled"; 1612 }; 1613 1614 usb2_phy0: usb-phy@ee080200 { 1615 compatible = "renesas,usb2-phy-r8a774c0", 1616 "renesas,rcar-gen3-usb2-phy"; 1617 reg = <0 0xee080200 0 0x700>; 1618 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1619 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; 1620 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1621 resets = <&cpg 703>, <&cpg 704>; 1622 #phy-cells = <1>; 1623 status = "disabled"; 1624 }; 1625 1626 sdhi0: mmc@ee100000 { 1627 compatible = "renesas,sdhi-r8a774c0", 1628 "renesas,rcar-gen3-sdhi"; 1629 reg = <0 0xee100000 0 0x2000>; 1630 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1631 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774C0_CLK_SD0H>; 1632 clock-names = "core", "clkh"; 1633 max-frequency = <200000000>; 1634 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1635 resets = <&cpg 314>; 1636 status = "disabled"; 1637 }; 1638 1639 sdhi1: mmc@ee120000 { 1640 compatible = "renesas,sdhi-r8a774c0", 1641 "renesas,rcar-gen3-sdhi"; 1642 reg = <0 0xee120000 0 0x2000>; 1643 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 1644 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774C0_CLK_SD1H>; 1645 clock-names = "core", "clkh"; 1646 max-frequency = <200000000>; 1647 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1648 resets = <&cpg 313>; 1649 status = "disabled"; 1650 }; 1651 1652 sdhi3: mmc@ee160000 { 1653 compatible = "renesas,sdhi-r8a774c0", 1654 "renesas,rcar-gen3-sdhi"; 1655 reg = <0 0xee160000 0 0x2000>; 1656 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 1657 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774C0_CLK_SD3H>; 1658 clock-names = "core", "clkh"; 1659 max-frequency = <200000000>; 1660 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1661 resets = <&cpg 311>; 1662 status = "disabled"; 1663 }; 1664 1665 rpc: spi@ee200000 { 1666 compatible = "renesas,r8a774c0-rpc-if", 1667 "renesas,rcar-gen3-rpc-if"; 1668 reg = <0 0xee200000 0 0x200>, 1669 <0 0x08000000 0 0x4000000>, 1670 <0 0xee208000 0 0x100>; 1671 reg-names = "regs", "dirmap", "wbuf"; 1672 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1673 clocks = <&cpg CPG_MOD 917>; 1674 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1675 resets = <&cpg 917>; 1676 #address-cells = <1>; 1677 #size-cells = <0>; 1678 status = "disabled"; 1679 }; 1680 1681 gic: interrupt-controller@f1010000 { 1682 compatible = "arm,gic-400"; 1683 #interrupt-cells = <3>; 1684 #address-cells = <0>; 1685 interrupt-controller; 1686 reg = <0x0 0xf1010000 0 0x1000>, 1687 <0x0 0xf1020000 0 0x20000>, 1688 <0x0 0xf1040000 0 0x20000>, 1689 <0x0 0xf1060000 0 0x20000>; 1690 interrupts = <GIC_PPI 9 1691 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 1692 clocks = <&cpg CPG_MOD 408>; 1693 clock-names = "clk"; 1694 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1695 resets = <&cpg 408>; 1696 }; 1697 1698 pciec0: pcie@fe000000 { 1699 compatible = "renesas,pcie-r8a774c0", 1700 "renesas,pcie-rcar-gen3"; 1701 reg = <0 0xfe000000 0 0x80000>; 1702 #address-cells = <3>; 1703 #size-cells = <2>; 1704 bus-range = <0x00 0xff>; 1705 device_type = "pci"; 1706 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, 1707 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, 1708 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, 1709 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; 1710 /* Map all possible DDR as inbound ranges */ 1711 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; 1712 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1713 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1714 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1715 #interrupt-cells = <1>; 1716 interrupt-map-mask = <0 0 0 0>; 1717 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1718 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1719 clock-names = "pcie", "pcie_bus"; 1720 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1721 resets = <&cpg 319>; 1722 status = "disabled"; 1723 }; 1724 1725 pciec0_ep: pcie-ep@fe000000 { 1726 compatible = "renesas,r8a774c0-pcie-ep", 1727 "renesas,rcar-gen3-pcie-ep"; 1728 reg = <0x0 0xfe000000 0 0x80000>, 1729 <0x0 0xfe100000 0 0x100000>, 1730 <0x0 0xfe200000 0 0x200000>, 1731 <0x0 0x30000000 0 0x8000000>, 1732 <0x0 0x38000000 0 0x8000000>; 1733 reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; 1734 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1735 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1736 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1737 clocks = <&cpg CPG_MOD 319>; 1738 clock-names = "pcie"; 1739 resets = <&cpg 319>; 1740 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1741 status = "disabled"; 1742 }; 1743 1744 vspb0: vsp@fe960000 { 1745 compatible = "renesas,vsp2"; 1746 reg = <0 0xfe960000 0 0x8000>; 1747 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1748 clocks = <&cpg CPG_MOD 626>; 1749 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1750 resets = <&cpg 626>; 1751 renesas,fcp = <&fcpvb0>; 1752 }; 1753 1754 vspd0: vsp@fea20000 { 1755 compatible = "renesas,vsp2"; 1756 reg = <0 0xfea20000 0 0x7000>; 1757 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1758 clocks = <&cpg CPG_MOD 623>; 1759 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1760 resets = <&cpg 623>; 1761 renesas,fcp = <&fcpvd0>; 1762 }; 1763 1764 vspd1: vsp@fea28000 { 1765 compatible = "renesas,vsp2"; 1766 reg = <0 0xfea28000 0 0x7000>; 1767 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1768 clocks = <&cpg CPG_MOD 622>; 1769 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1770 resets = <&cpg 622>; 1771 renesas,fcp = <&fcpvd1>; 1772 }; 1773 1774 vspi0: vsp@fe9a0000 { 1775 compatible = "renesas,vsp2"; 1776 reg = <0 0xfe9a0000 0 0x8000>; 1777 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; 1778 clocks = <&cpg CPG_MOD 631>; 1779 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1780 resets = <&cpg 631>; 1781 renesas,fcp = <&fcpvi0>; 1782 }; 1783 1784 fcpvb0: fcp@fe96f000 { 1785 compatible = "renesas,fcpv"; 1786 reg = <0 0xfe96f000 0 0x200>; 1787 clocks = <&cpg CPG_MOD 607>; 1788 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1789 resets = <&cpg 607>; 1790 iommus = <&ipmmu_vp0 5>; 1791 }; 1792 1793 fcpvd0: fcp@fea27000 { 1794 compatible = "renesas,fcpv"; 1795 reg = <0 0xfea27000 0 0x200>; 1796 clocks = <&cpg CPG_MOD 603>; 1797 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1798 resets = <&cpg 603>; 1799 iommus = <&ipmmu_vi0 8>; 1800 }; 1801 1802 fcpvd1: fcp@fea2f000 { 1803 compatible = "renesas,fcpv"; 1804 reg = <0 0xfea2f000 0 0x200>; 1805 clocks = <&cpg CPG_MOD 602>; 1806 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1807 resets = <&cpg 602>; 1808 iommus = <&ipmmu_vi0 9>; 1809 }; 1810 1811 fcpvi0: fcp@fe9af000 { 1812 compatible = "renesas,fcpv"; 1813 reg = <0 0xfe9af000 0 0x200>; 1814 clocks = <&cpg CPG_MOD 611>; 1815 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1816 resets = <&cpg 611>; 1817 iommus = <&ipmmu_vp0 8>; 1818 }; 1819 1820 csi40: csi2@feaa0000 { 1821 compatible = "renesas,r8a774c0-csi2"; 1822 reg = <0 0xfeaa0000 0 0x10000>; 1823 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1824 clocks = <&cpg CPG_MOD 716>; 1825 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1826 resets = <&cpg 716>; 1827 status = "disabled"; 1828 1829 ports { 1830 #address-cells = <1>; 1831 #size-cells = <0>; 1832 1833 port@0 { 1834 reg = <0>; 1835 }; 1836 1837 port@1 { 1838 #address-cells = <1>; 1839 #size-cells = <0>; 1840 1841 reg = <1>; 1842 1843 csi40vin4: endpoint@0 { 1844 reg = <0>; 1845 remote-endpoint = <&vin4csi40>; 1846 }; 1847 csi40vin5: endpoint@1 { 1848 reg = <1>; 1849 remote-endpoint = <&vin5csi40>; 1850 }; 1851 }; 1852 }; 1853 }; 1854 1855 du: display@feb00000 { 1856 compatible = "renesas,du-r8a774c0"; 1857 reg = <0 0xfeb00000 0 0x40000>; 1858 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 1859 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1860 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; 1861 clock-names = "du.0", "du.1"; 1862 resets = <&cpg 724>; 1863 reset-names = "du.0"; 1864 renesas,vsps = <&vspd0 0>, <&vspd1 0>; 1865 1866 status = "disabled"; 1867 1868 ports { 1869 #address-cells = <1>; 1870 #size-cells = <0>; 1871 1872 port@0 { 1873 reg = <0>; 1874 }; 1875 1876 port@1 { 1877 reg = <1>; 1878 du_out_lvds0: endpoint { 1879 remote-endpoint = <&lvds0_in>; 1880 }; 1881 }; 1882 1883 port@2 { 1884 reg = <2>; 1885 du_out_lvds1: endpoint { 1886 remote-endpoint = <&lvds1_in>; 1887 }; 1888 }; 1889 }; 1890 }; 1891 1892 lvds0: lvds-encoder@feb90000 { 1893 compatible = "renesas,r8a774c0-lvds"; 1894 reg = <0 0xfeb90000 0 0x20>; 1895 clocks = <&cpg CPG_MOD 727>; 1896 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1897 resets = <&cpg 727>; 1898 status = "disabled"; 1899 1900 renesas,companion = <&lvds1>; 1901 1902 ports { 1903 #address-cells = <1>; 1904 #size-cells = <0>; 1905 1906 port@0 { 1907 reg = <0>; 1908 lvds0_in: endpoint { 1909 remote-endpoint = <&du_out_lvds0>; 1910 }; 1911 }; 1912 1913 port@1 { 1914 reg = <1>; 1915 }; 1916 }; 1917 }; 1918 1919 lvds1: lvds-encoder@feb90100 { 1920 compatible = "renesas,r8a774c0-lvds"; 1921 reg = <0 0xfeb90100 0 0x20>; 1922 clocks = <&cpg CPG_MOD 727>; 1923 power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; 1924 resets = <&cpg 726>; 1925 status = "disabled"; 1926 1927 ports { 1928 #address-cells = <1>; 1929 #size-cells = <0>; 1930 1931 port@0 { 1932 reg = <0>; 1933 lvds1_in: endpoint { 1934 remote-endpoint = <&du_out_lvds1>; 1935 }; 1936 }; 1937 1938 port@1 { 1939 reg = <1>; 1940 }; 1941 }; 1942 }; 1943 1944 prr: chipid@fff00044 { 1945 compatible = "renesas,prr"; 1946 reg = <0 0xfff00044 0 4>; 1947 }; 1948 }; 1949 1950 thermal-zones { 1951 cpu-thermal { 1952 polling-delay-passive = <250>; 1953 polling-delay = <0>; 1954 thermal-sensors = <&thermal>; 1955 sustainable-power = <717>; 1956 1957 cooling-maps { 1958 map0 { 1959 trip = <&target>; 1960 cooling-device = <&a53_0 0 2>; 1961 contribution = <1024>; 1962 }; 1963 }; 1964 1965 trips { 1966 sensor1_crit: sensor1-crit { 1967 temperature = <120000>; 1968 hysteresis = <2000>; 1969 type = "critical"; 1970 }; 1971 1972 target: trip-point1 { 1973 temperature = <100000>; 1974 hysteresis = <2000>; 1975 type = "passive"; 1976 }; 1977 }; 1978 }; 1979 }; 1980 1981 timer { 1982 compatible = "arm,armv8-timer"; 1983 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1984 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1985 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1986 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 1987 }; 1988 1989 /* External USB clocks - can be overridden by the board */ 1990 usb3s0_clk: usb3s0 { 1991 compatible = "fixed-clock"; 1992 #clock-cells = <0>; 1993 clock-frequency = <0>; 1994 }; 1995 1996 usb_extal_clk: usb_extal { 1997 compatible = "fixed-clock"; 1998 #clock-cells = <0>; 1999 clock-frequency = <0>; 2000 }; 2001}; 2002