1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the Ebisu board 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10 11/ { 12 model = "Renesas Ebisu board"; 13 compatible = "renesas,ebisu"; 14 15 aliases { 16 i2c0 = &i2c0; 17 i2c1 = &i2c1; 18 i2c2 = &i2c2; 19 i2c3 = &i2c3; 20 i2c4 = &i2c4; 21 i2c5 = &i2c5; 22 i2c6 = &i2c6; 23 i2c7 = &i2c7; 24 serial0 = &scif2; 25 ethernet0 = &avb; 26 mmc0 = &sdhi3; 27 mmc1 = &sdhi0; 28 mmc2 = &sdhi1; 29 }; 30 31 chosen { 32 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 33 stdout-path = "serial0:115200n8"; 34 }; 35 36 audio_clkout: audio-clkout { 37 /* 38 * This is same as <&rcar_sound 0> 39 * but needed to avoid cs2000/rcar_sound probe dead-lock 40 */ 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <11289600>; 44 }; 45 46 backlight: backlight { 47 compatible = "pwm-backlight"; 48 pwms = <&pwm3 0 50000>; 49 50 brightness-levels = <512 511 505 494 473 440 392 327 241 133 0>; 51 default-brightness-level = <10>; 52 53 power-supply = <®_12p0v>; 54 }; 55 56 cvbs-in { 57 compatible = "composite-video-connector"; 58 label = "CVBS IN"; 59 60 port { 61 cvbs_con: endpoint { 62 remote-endpoint = <&adv7482_ain7>; 63 }; 64 }; 65 }; 66 67 hdmi-in { 68 compatible = "hdmi-connector"; 69 label = "HDMI IN"; 70 type = "a"; 71 72 port { 73 hdmi_in_con: endpoint { 74 remote-endpoint = <&adv7482_hdmi>; 75 }; 76 }; 77 }; 78 79 hdmi-out { 80 compatible = "hdmi-connector"; 81 type = "a"; 82 83 port { 84 hdmi_con_out: endpoint { 85 remote-endpoint = <&adv7511_out>; 86 }; 87 }; 88 }; 89 90 keys { 91 compatible = "gpio-keys"; 92 93 pinctrl-0 = <&keys_pins>; 94 pinctrl-names = "default"; 95 96 key-1 { 97 gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; 98 linux,code = <KEY_1>; 99 label = "SW4-1"; 100 wakeup-source; 101 debounce-interval = <20>; 102 }; 103 key-2 { 104 gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 105 linux,code = <KEY_2>; 106 label = "SW4-2"; 107 wakeup-source; 108 debounce-interval = <20>; 109 }; 110 key-3 { 111 gpios = <&gpio5 12 GPIO_ACTIVE_LOW>; 112 linux,code = <KEY_3>; 113 label = "SW4-3"; 114 wakeup-source; 115 debounce-interval = <20>; 116 }; 117 key-4 { 118 gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; 119 linux,code = <KEY_4>; 120 label = "SW4-4"; 121 wakeup-source; 122 debounce-interval = <20>; 123 }; 124 }; 125 126 lvds-decoder { 127 compatible = "thine,thc63lvd1024"; 128 vcc-supply = <®_3p3v>; 129 130 ports { 131 #address-cells = <1>; 132 #size-cells = <0>; 133 134 port@0 { 135 reg = <0>; 136 thc63lvd1024_in: endpoint { 137 remote-endpoint = <&lvds0_out>; 138 }; 139 }; 140 141 port@2 { 142 reg = <2>; 143 thc63lvd1024_out: endpoint { 144 remote-endpoint = <&adv7511_in>; 145 }; 146 }; 147 }; 148 }; 149 150 memory@48000000 { 151 device_type = "memory"; 152 /* first 128MB is reserved for secure area. */ 153 reg = <0x0 0x48000000 0x0 0x38000000>; 154 }; 155 156 reg_1p8v: regulator-1p8v { 157 compatible = "regulator-fixed"; 158 regulator-name = "fixed-1.8V"; 159 regulator-min-microvolt = <1800000>; 160 regulator-max-microvolt = <1800000>; 161 regulator-boot-on; 162 regulator-always-on; 163 }; 164 165 reg_3p3v: regulator-3p3v { 166 compatible = "regulator-fixed"; 167 regulator-name = "fixed-3.3V"; 168 regulator-min-microvolt = <3300000>; 169 regulator-max-microvolt = <3300000>; 170 regulator-boot-on; 171 regulator-always-on; 172 }; 173 174 reg_12p0v: regulator-12p0v { 175 compatible = "regulator-fixed"; 176 regulator-name = "D12.0V"; 177 regulator-min-microvolt = <12000000>; 178 regulator-max-microvolt = <12000000>; 179 regulator-boot-on; 180 regulator-always-on; 181 }; 182 183 rsnd_ak4613: sound { 184 compatible = "simple-audio-card"; 185 186 simple-audio-card,name = "rsnd-ak4613"; 187 simple-audio-card,format = "left_j"; 188 simple-audio-card,bitclock-master = <&sndcpu>; 189 simple-audio-card,frame-master = <&sndcpu>; 190 191 sndcodec: simple-audio-card,codec { 192 sound-dai = <&ak4613>; 193 }; 194 195 sndcpu: simple-audio-card,cpu { 196 sound-dai = <&rcar_sound>; 197 }; 198 }; 199 200 vbus0_usb2: regulator-vbus0-usb2 { 201 compatible = "regulator-fixed"; 202 203 regulator-name = "USB20_VBUS_CN"; 204 regulator-min-microvolt = <5000000>; 205 regulator-max-microvolt = <5000000>; 206 207 gpio = <&gpio6 4 GPIO_ACTIVE_HIGH>; 208 enable-active-high; 209 }; 210 211 vcc_sdhi0: regulator-vcc-sdhi0 { 212 compatible = "regulator-fixed"; 213 214 regulator-name = "SDHI0 Vcc"; 215 regulator-min-microvolt = <3300000>; 216 regulator-max-microvolt = <3300000>; 217 218 gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>; 219 enable-active-high; 220 }; 221 222 vccq_sdhi0: regulator-vccq-sdhi0 { 223 compatible = "regulator-gpio"; 224 225 regulator-name = "SDHI0 VccQ"; 226 regulator-min-microvolt = <1800000>; 227 regulator-max-microvolt = <3300000>; 228 229 gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>; 230 gpios-states = <1>; 231 states = <3300000 1>, <1800000 0>; 232 }; 233 234 vcc_sdhi1: regulator-vcc-sdhi1 { 235 compatible = "regulator-fixed"; 236 237 regulator-name = "SDHI1 Vcc"; 238 regulator-min-microvolt = <3300000>; 239 regulator-max-microvolt = <3300000>; 240 241 gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; 242 enable-active-high; 243 }; 244 245 vccq_sdhi1: regulator-vccq-sdhi1 { 246 compatible = "regulator-gpio"; 247 248 regulator-name = "SDHI1 VccQ"; 249 regulator-min-microvolt = <1800000>; 250 regulator-max-microvolt = <3300000>; 251 252 gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; 253 gpios-states = <1>; 254 states = <3300000 1>, <1800000 0>; 255 }; 256 257 vga { 258 compatible = "vga-connector"; 259 260 port { 261 vga_in: endpoint { 262 remote-endpoint = <&adv7123_out>; 263 }; 264 }; 265 }; 266 267 vga-encoder { 268 compatible = "adi,adv7123"; 269 270 ports { 271 #address-cells = <1>; 272 #size-cells = <0>; 273 274 port@0 { 275 reg = <0>; 276 adv7123_in: endpoint { 277 remote-endpoint = <&du_out_rgb>; 278 }; 279 }; 280 port@1 { 281 reg = <1>; 282 adv7123_out: endpoint { 283 remote-endpoint = <&vga_in>; 284 }; 285 }; 286 }; 287 }; 288 289 x12_clk: x12 { 290 compatible = "fixed-clock"; 291 #clock-cells = <0>; 292 clock-frequency = <24576000>; 293 }; 294 295 x13_clk: x13 { 296 compatible = "fixed-clock"; 297 #clock-cells = <0>; 298 clock-frequency = <74250000>; 299 }; 300}; 301 302&audio_clk_a { 303 clock-frequency = <22579200>; 304}; 305 306&avb { 307 pinctrl-0 = <&avb_pins>; 308 pinctrl-names = "default"; 309 phy-handle = <&phy0>; 310 status = "okay"; 311 312 phy0: ethernet-phy@0 { 313 compatible = "ethernet-phy-id0022.1622", 314 "ethernet-phy-ieee802.3-c22"; 315 rxc-skew-ps = <1500>; 316 reg = <0>; 317 interrupt-parent = <&gpio2>; 318 interrupts = <21 IRQ_TYPE_LEVEL_LOW>; 319 reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; 320 /* 321 * TX clock internal delay mode is required for reliable 322 * 1Gbps communication using the KSZ9031RNX phy present on 323 * the Ebisu board, however, TX clock internal delay mode 324 * isn't supported on R-Car E3(e). Thus, limit speed to 325 * 100Mbps for reliable communication. 326 */ 327 max-speed = <100>; 328 }; 329}; 330 331&canfd { 332 pinctrl-0 = <&canfd0_pins>; 333 pinctrl-names = "default"; 334 status = "okay"; 335 336 channel0 { 337 status = "okay"; 338 }; 339}; 340 341&csi40 { 342 status = "okay"; 343 344 ports { 345 port@0 { 346 csi40_in: endpoint { 347 clock-lanes = <0>; 348 data-lanes = <1 2>; 349 remote-endpoint = <&adv7482_txa>; 350 }; 351 }; 352 }; 353}; 354 355&du { 356 pinctrl-0 = <&du_pins>; 357 pinctrl-names = "default"; 358 status = "okay"; 359 360 clocks = <&cpg CPG_MOD 724>, 361 <&cpg CPG_MOD 723>, 362 <&x13_clk>; 363 clock-names = "du.0", "du.1", "dclkin.0"; 364 365 ports { 366 port@0 { 367 du_out_rgb: endpoint { 368 remote-endpoint = <&adv7123_in>; 369 }; 370 }; 371 }; 372}; 373 374&ehci0 { 375 dr_mode = "otg"; 376 status = "okay"; 377}; 378 379&extal_clk { 380 clock-frequency = <48000000>; 381}; 382 383&hsusb { 384 dr_mode = "otg"; 385 status = "okay"; 386}; 387 388&i2c0 { 389 status = "okay"; 390 391 io_expander: gpio@20 { 392 compatible = "onnn,pca9654"; 393 reg = <0x20>; 394 gpio-controller; 395 #gpio-cells = <2>; 396 interrupt-parent = <&gpio2>; 397 interrupts = <22 IRQ_TYPE_LEVEL_LOW>; 398 }; 399 400 hdmi-encoder@39 { 401 compatible = "adi,adv7511w"; 402 reg = <0x39>; 403 interrupt-parent = <&gpio1>; 404 interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 405 406 adi,input-depth = <8>; 407 adi,input-colorspace = "rgb"; 408 adi,input-clock = "1x"; 409 410 ports { 411 #address-cells = <1>; 412 #size-cells = <0>; 413 414 port@0 { 415 reg = <0>; 416 adv7511_in: endpoint { 417 remote-endpoint = <&thc63lvd1024_out>; 418 }; 419 }; 420 421 port@1 { 422 reg = <1>; 423 adv7511_out: endpoint { 424 remote-endpoint = <&hdmi_con_out>; 425 }; 426 }; 427 }; 428 }; 429 430 video-receiver@70 { 431 compatible = "adi,adv7482"; 432 reg = <0x70>; 433 434 interrupt-parent = <&gpio0>; 435 interrupt-names = "intrq1", "intrq2"; 436 interrupts = <7 IRQ_TYPE_LEVEL_LOW>, 437 <17 IRQ_TYPE_LEVEL_LOW>; 438 439 ports { 440 #address-cells = <1>; 441 #size-cells = <0>; 442 443 port@7 { 444 reg = <7>; 445 446 adv7482_ain7: endpoint { 447 remote-endpoint = <&cvbs_con>; 448 }; 449 }; 450 451 port@8 { 452 reg = <8>; 453 454 adv7482_hdmi: endpoint { 455 remote-endpoint = <&hdmi_in_con>; 456 }; 457 }; 458 459 port@a { 460 reg = <10>; 461 462 adv7482_txa: endpoint { 463 clock-lanes = <0>; 464 data-lanes = <1 2>; 465 remote-endpoint = <&csi40_in>; 466 }; 467 }; 468 }; 469 }; 470}; 471 472&i2c3 { 473 status = "okay"; 474 475 ak4613: codec@10 { 476 compatible = "asahi-kasei,ak4613"; 477 #sound-dai-cells = <0>; 478 reg = <0x10>; 479 clocks = <&rcar_sound 3>; 480 481 asahi-kasei,in1-single-end; 482 asahi-kasei,in2-single-end; 483 asahi-kasei,out1-single-end; 484 asahi-kasei,out2-single-end; 485 asahi-kasei,out3-single-end; 486 asahi-kasei,out4-single-end; 487 asahi-kasei,out5-single-end; 488 asahi-kasei,out6-single-end; 489 }; 490 491 cs2000: clk-multiplier@4f { 492 #clock-cells = <0>; 493 compatible = "cirrus,cs2000-cp"; 494 reg = <0x4f>; 495 clocks = <&audio_clkout>, <&x12_clk>; 496 clock-names = "clk_in", "ref_clk"; 497 498 assigned-clocks = <&cs2000>; 499 assigned-clock-rates = <24576000>; /* 1/1 divide */ 500 }; 501}; 502 503&i2c_dvfs { 504 status = "okay"; 505 506 clock-frequency = <400000>; 507 508 pmic: pmic@30 { 509 pinctrl-0 = <&irq0_pins>; 510 pinctrl-names = "default"; 511 512 compatible = "rohm,bd9571mwv"; 513 reg = <0x30>; 514 interrupt-parent = <&intc_ex>; 515 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 516 interrupt-controller; 517 #interrupt-cells = <2>; 518 gpio-controller; 519 #gpio-cells = <2>; 520 rohm,ddr-backup-power = <0x1>; 521 rohm,rstbmode-level; 522 }; 523 524 eeprom@50 { 525 compatible = "rohm,br24t01", "atmel,24c01"; 526 reg = <0x50>; 527 pagesize = <8>; 528 }; 529}; 530 531&lvds0 { 532 status = "okay"; 533 534 clocks = <&cpg CPG_MOD 727>, 535 <&x13_clk>, 536 <&extal_clk>; 537 clock-names = "fck", "dclkin.0", "extal"; 538 539 ports { 540 port@1 { 541 lvds0_out: endpoint { 542 remote-endpoint = <&thc63lvd1024_in>; 543 }; 544 }; 545 }; 546}; 547 548&lvds1 { 549 /* 550 * Even though the LVDS1 output is not connected, the encoder must be 551 * enabled to supply a pixel clock to the DU for the DPAD output when 552 * LVDS0 is in use. 553 */ 554 status = "okay"; 555 556 clocks = <&cpg CPG_MOD 727>, 557 <&x13_clk>, 558 <&extal_clk>; 559 clock-names = "fck", "dclkin.0", "extal"; 560}; 561 562&ohci0 { 563 dr_mode = "otg"; 564 status = "okay"; 565}; 566 567&pcie_bus_clk { 568 clock-frequency = <100000000>; 569}; 570 571&pciec0 { 572 status = "okay"; 573}; 574 575&pfc { 576 avb_pins: avb { 577 groups = "avb_link", "avb_mii"; 578 function = "avb"; 579 }; 580 581 canfd0_pins: canfd0 { 582 groups = "canfd0_data"; 583 function = "canfd0"; 584 }; 585 586 du_pins: du { 587 groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; 588 function = "du"; 589 }; 590 591 irq0_pins: irq0 { 592 groups = "intc_ex_irq0"; 593 function = "intc_ex"; 594 }; 595 596 keys_pins: keys { 597 pins = "GP_5_10", "GP_5_11", "GP_5_12", "GP_5_13"; 598 bias-pull-up; 599 }; 600 601 pwm3_pins: pwm3 { 602 groups = "pwm3_b"; 603 function = "pwm3"; 604 }; 605 606 pwm5_pins: pwm5 { 607 groups = "pwm5_a"; 608 function = "pwm5"; 609 }; 610 611 rpc_pins: rpc { 612 groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset", 613 "rpc_int"; 614 function = "rpc"; 615 }; 616 617 scif2_pins: scif2 { 618 groups = "scif2_data_a"; 619 function = "scif2"; 620 }; 621 622 sdhi0_pins: sd0 { 623 groups = "sdhi0_data4", "sdhi0_ctrl"; 624 function = "sdhi0"; 625 power-source = <3300>; 626 }; 627 628 sdhi0_pins_uhs: sd0_uhs { 629 groups = "sdhi0_data4", "sdhi0_ctrl"; 630 function = "sdhi0"; 631 power-source = <1800>; 632 }; 633 634 sdhi1_pins: sd1 { 635 groups = "sdhi1_data4", "sdhi1_ctrl"; 636 function = "sdhi1"; 637 power-source = <3300>; 638 }; 639 640 sdhi1_pins_uhs: sd1_uhs { 641 groups = "sdhi1_data4", "sdhi1_ctrl"; 642 function = "sdhi1"; 643 power-source = <1800>; 644 }; 645 646 sdhi3_pins: sd3 { 647 groups = "sdhi3_data8", "sdhi3_ctrl", "sdhi3_ds"; 648 function = "sdhi3"; 649 power-source = <1800>; 650 }; 651 652 sound_clk_pins: sound_clk { 653 groups = "audio_clk_a", "audio_clk_b_a", "audio_clk_c_a", 654 "audio_clkout_a", "audio_clkout1_a"; 655 function = "audio_clk"; 656 }; 657 658 sound_pins: sound { 659 groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data"; 660 function = "ssi"; 661 }; 662 663 usb0_pins: usb { 664 groups = "usb0_b", "usb0_id"; 665 function = "usb0"; 666 }; 667 668 usb30_pins: usb30 { 669 groups = "usb30"; 670 function = "usb30"; 671 }; 672}; 673 674&pwm3 { 675 pinctrl-0 = <&pwm3_pins>; 676 pinctrl-names = "default"; 677 678 status = "okay"; 679}; 680 681&pwm5 { 682 pinctrl-0 = <&pwm5_pins>; 683 pinctrl-names = "default"; 684 685 status = "okay"; 686}; 687 688&rcar_sound { 689 pinctrl-0 = <&sound_pins>, <&sound_clk_pins>; 690 pinctrl-names = "default"; 691 692 /* Single DAI */ 693 #sound-dai-cells = <0>; 694 695 /* audio_clkout0/1/2/3 */ 696 #clock-cells = <1>; 697 clock-frequency = <12288000 11289600>; 698 699 status = "okay"; 700 701 /* update <audio_clk_b> to <cs2000> */ 702 clocks = <&cpg CPG_MOD 1005>, 703 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, 704 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, 705 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, 706 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, 707 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, 708 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, 709 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, 710 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, 711 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, 712 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, 713 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 714 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, 715 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, 716 <&audio_clk_a>, <&cs2000>, <&audio_clk_c>, 717 <&cpg CPG_CORE R8A77990_CLK_ZA2>; 718 719 rcar_sound,dai { 720 dai0 { 721 playback = <&ssi0>, <&src0>, <&dvc0>; 722 capture = <&ssi1>, <&src1>, <&dvc1>; 723 }; 724 }; 725 726}; 727 728&rpc { 729 pinctrl-0 = <&rpc_pins>; 730 pinctrl-names = "default"; 731 732 /* Left disabled. To be enabled by firmware when unlocked. */ 733 734 flash@0 { 735 compatible = "cypress,hyperflash", "cfi-flash"; 736 reg = <0>; 737 738 partitions { 739 compatible = "fixed-partitions"; 740 #address-cells = <1>; 741 #size-cells = <1>; 742 743 bootparam@0 { 744 reg = <0x00000000 0x040000>; 745 read-only; 746 }; 747 bl2@40000 { 748 reg = <0x00040000 0x140000>; 749 read-only; 750 }; 751 cert_header_sa6@180000 { 752 reg = <0x00180000 0x040000>; 753 read-only; 754 }; 755 bl31@1c0000 { 756 reg = <0x001c0000 0x040000>; 757 read-only; 758 }; 759 tee@200000 { 760 reg = <0x00200000 0x440000>; 761 read-only; 762 }; 763 uboot@640000 { 764 reg = <0x00640000 0x100000>; 765 read-only; 766 }; 767 dtb@740000 { 768 reg = <0x00740000 0x080000>; 769 }; 770 kernel@7c0000 { 771 reg = <0x007c0000 0x1400000>; 772 }; 773 user@1bc0000 { 774 reg = <0x01bc0000 0x2440000>; 775 }; 776 }; 777 }; 778}; 779 780&rwdt { 781 timeout-sec = <60>; 782 status = "okay"; 783}; 784 785&scif2 { 786 pinctrl-0 = <&scif2_pins>; 787 pinctrl-names = "default"; 788 789 status = "okay"; 790}; 791 792&sdhi0 { 793 pinctrl-0 = <&sdhi0_pins>; 794 pinctrl-1 = <&sdhi0_pins_uhs>; 795 pinctrl-names = "default", "state_uhs"; 796 797 vmmc-supply = <&vcc_sdhi0>; 798 vqmmc-supply = <&vccq_sdhi0>; 799 cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; 800 wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; 801 bus-width = <4>; 802 sd-uhs-sdr50; 803 sd-uhs-sdr104; 804 status = "okay"; 805}; 806 807&sdhi1 { 808 pinctrl-0 = <&sdhi1_pins>; 809 pinctrl-1 = <&sdhi1_pins_uhs>; 810 pinctrl-names = "default", "state_uhs"; 811 812 vmmc-supply = <&vcc_sdhi1>; 813 vqmmc-supply = <&vccq_sdhi1>; 814 cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>; 815 bus-width = <4>; 816 sd-uhs-sdr50; 817 sd-uhs-sdr104; 818 status = "okay"; 819}; 820 821&sdhi3 { 822 /* used for on-board 8bit eMMC */ 823 pinctrl-0 = <&sdhi3_pins>; 824 pinctrl-1 = <&sdhi3_pins>; 825 pinctrl-names = "default", "state_uhs"; 826 827 vmmc-supply = <®_3p3v>; 828 vqmmc-supply = <®_1p8v>; 829 mmc-hs200-1_8v; 830 mmc-hs400-1_8v; 831 bus-width = <8>; 832 no-sd; 833 no-sdio; 834 non-removable; 835 full-pwr-cycle-in-suspend; 836 status = "okay"; 837}; 838 839&ssi1 { 840 shared-pin; 841}; 842 843&usb2_phy0 { 844 pinctrl-0 = <&usb0_pins>; 845 pinctrl-names = "default"; 846 847 vbus-supply = <&vbus0_usb2>; 848 status = "okay"; 849}; 850 851&usb3_peri0 { 852 companion = <&xhci0>; 853 status = "okay"; 854}; 855 856&vin4 { 857 status = "okay"; 858}; 859 860&vin5 { 861 status = "okay"; 862}; 863 864&xhci0 { 865 pinctrl-0 = <&usb30_pins>; 866 pinctrl-names = "default"; 867 868 status = "okay"; 869}; 870